(19)
(11)EP 3 435 422 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.05.2020 Bulletin 2020/19

(21)Application number: 17183326.2

(22)Date of filing:  26.07.2017
(51)Int. Cl.: 
H01L 31/02  (2006.01)
H01L 27/144  (2006.01)
H01L 31/107  (2006.01)

(54)

SPAD DEVICE FOR EXCESS BIAS MONITORING

SPAD-VORRICHTUNG ZUR ÜBERWACHUNG VON ÜBERMÄSSIGER VORSPANNUNG

DISPOSITIF SPAD POUR LA SURVEILLANCE DE LA POLARISATION EN EXCÈS


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
30.01.2019 Bulletin 2019/05

(73)Proprietor: ams AG
8141 Premstätten (AT)

(72)Inventors:
  • Röhrer, Georg
    8141 Premstätten (AT)
  • Kappel, Robert
    8141 Premstätten (AT)
  • Lilic, Nenad
    8141 Premstätten (AT)

(74)Representative: Epping - Hermann - Fischer 
Patentanwaltsgesellschaft mbH Schloßschmidstraße 5
80639 München
80639 München (DE)


(56)References cited: : 
US-A1- 2002 195 545
US-A1- 2013 334 411
US-A1- 2011 248 175
US-A1- 2016 182 902
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present disclosure is related to single-photon avalanche diodes.

    [0002] Single-photon avalanche diodes (SPADs) are semiconductor devices with a p-n junction. A reverse bias is used to increase the width of the depletion region. When the operating voltage providing the reverse bias exceeds the breakdown voltage of the p-n junction by the so-called excess bias voltage, a single charge carrier injected into the depletion layer triggers a self-sustaining avalanche. The current rises swiftly unless the operating voltage is decreased to the breakdown voltage or below. The avalanche is initiated by pairs of electrons and holes, which are generated by photons from a light source or by a forward biased p-n junction.

    [0003] The breakdown voltage changes with temperature and can be different for individual devices at the same temperature because of tolerances of the manufacturing process. It is important to control the excess bias voltage by a suitable circuit, because all key parameters of a single-photon avalanche diode, including photon detection probability PDP, dark count rate DCR, after pulsing probability, cross talk probability, timing jitter and capacitance, depend on the excess bias voltage. A low dark count rate is desired, but it causes tardy triggering and may therefore prevent the undelayed control of the excess bias voltage.

    [0004] US 2016/0182902 A1 discloses a silicon photomultiplier with a plurality of microcells containing avalanche photodiodes. A self-test is performed to identify microcells with dark count rate above a predetermined threshold, and such microcells are disabled.

    [0005] Faster triggering for calibration can be enabled by the use of a light source to illuminate the single-photon avalanche diode, but a light source may not be easily available for some types of applications.

    [0006] It is an object of the present invention to present a single-photon avalanche diode device allowing a fast measurement of the breakdown voltage at relatively low temperatures and in the dark.

    [0007] This object is achieved with the SPAD device according to claim 1. Embodiments derive from the dependent claims.

    [0008] The definitions as described above also apply to the following description unless stated otherwise.

    [0009] The SPAD device comprises a single-photon avalanche diode and a further single-photon avalanche diode having breakdown voltages, the single-photon avalanche diodes being integrated in the same device, the breakdown voltages being equal or differing by less than 10%, especially by less than 2.5%. The single-photon avalanche diode is configured to have a dark count rate that is higher than the dark count rate of the further single-photon avalanche diode.

    [0010] The single-photon avalanche diode is in particular provided for adjusting or controlling an excess bias voltage, while the further single-photon avalanche diode is provided for a detection of radiation. The single-photon avalanche diode and the further single-photon avalanche diode are configured for alternative operation.

    [0011] In embodiments of the SPAD device, the single-photon avalanche diode has a dark count rate, the further single-photon avalanche diode has a further dark count rate, and the dark count rate is at least a factor 100 higher than the further dark count rate at least at one temperature below 25°C.

    [0012] In further embodiments of the SPAD device, a p-n junction of the single-photon avalanche diode forms a base-collector junction of a structure of a bipolar transistor including an emitter region, a base region and a collector region. The bipolar transistor is configured for operation at a reverse collector-to-base voltage above the breakdown voltage.

    [0013] In particular, the bipolar transistor is a vertical bipolar transistor. During operation of a vertical bipolar transistor, electric current across the base region flows in the direction normal to the main surface of the semiconductor substrate or wafer of the device. The current flow may additionally have a lateral component parallel to the main surface.

    [0014] In further embodiments a quenching component is electrically connected with the base or the collector, and a switching circuitry is configured to apply a forward bias to the base-emitter junction.

    [0015] A further embodiment comprises a substrate of semiconductor material, a shallow well of a first type of conductivity in a deep well of an opposite second type of conductivity in the substrate, the deep well and the shallow well forming a p-n junction of the single-photon avalanche photodiode. A junction-forming region of the second type of conductivity is arranged in the deep well under the shallow well. At the p-n junction the doping concentration of the junction-forming region is higher than a doping concentration of the deep well outside the junction-forming region. The further single-photon avalanche diode comprises a further shallow well of the first type of conductivity in the deep well or in a further deep well of the opposite second type of conductivity in the substrate, the further shallow well forming a further p-n junction with the deep well or further deep well. A further junction-forming region is arranged under the further shallow well, the further junction-forming region having a doping concentration for the second type of conductivity, at the further p-n junction said doping concentration being higher than a doping concentration of the deep well or further deep well outside the further junction-forming region. The single-photon avalanche diode and the further single-photon avalanche diode can be arranged in the same deep well. The areas of the p-n junction and the further p-n junction may be the same or differ at most by a factor of 2. An optional cover layer of dielectric material may be arranged on the shallow well above the junction-forming region.

    [0016] In this embodiment a shallow well region is arranged in the shallow well, the shallow well region having a doping concentration that is higher than a doping concentration of the shallow well outside the shallow well region. The shallow well and the shallow well region occupy areas of the substrate surface of different sizes. A further shallow well region is arranged in the further shallow well, the further shallow well region having a doping concentration that is higher than a doping concentration of the further shallow well outside the further shallow well region.

    [0017] A further embodiment comprises a peripheral region of the shallow well, the peripheral region reaching laterally beyond the junction-forming region. In particular, the peripheral region may not be covered by the shallow well region.

    [0018] A further embodiment comprises an opening in the shallow well region, the opening being arranged above the junction-forming region. The opening may comprise separate portions.

    [0019] A further embodiment comprises a polysilicon layer arranged above the shallow well and above the junction-forming region, in particular above an opening in the shallow well region. The cover layer is recessed under the polysilicon layer.

    [0020] A further embodiment comprises a highly doped region of the second type of conductivity in the shallow well above the junction-forming region at a distance from the p-n junction. The highly doped region, the shallow well and the junction-forming region respectively form an emitter region, a base region and a collector region of the structure of a bipolar transistor.

    [0021] A further embodiment comprises a deep well contact region in the deep well, the deep well contact region having a doping concentration that is higher than a doping concentration of the deep well.

    [0022] A further embodiment comprises separate contact layers arranged on the deep well contact region and on the shallow well region.

    [0023] In a further embodiment the contact layer arranged on the shallow well region covers at least 80% of the junction-forming region.

    [0024] In a further embodiment the shallow well region does not cover the entire junction-forming region, and the further shallow well region is arranged above the entire further junction-forming region.

    [0025] The following is a detailed description of examples of the SPAD device in conjunction with the appended figures.
    Figure 1
    is a partial cross section of a single-photon avalanche diode with high dark count rate.
    Figure 2
    is a partial cross section of a further singlephoton avalanche diode with high dark count rate.
    Figure 3
    is a partial cross section of a single-photon avalanche diode according to Figure 1 with an opening in a shallow well region.
    Figure 4
    is a partial cross section of a single-photon avalanche diode according to Figure 2 with openings in a reduced shallow well region.
    Figure 5
    is a partial cross section of a single-photon avalanche diode according to Figure 3 with a polysilicon layer.
    Figure 6
    is a partial cross section of a single-photon avalanche diode according to Figure 3 with an extended silicide layer on the shallow well region.
    Figure 7
    is a partial cross section of a single-photon avalanche diode with an oppositely doped region in the shallow well.
    Figure 8
    is a partial cross section according to Figure 7 with an oppositely doped region in an opening of the shallow well region.
    Figure 9
    is a circuit diagram for the single-photon avalanche diode according to Figure 7 or 8.
    Figure 10
    is an alternative circuit diagram for the singlephoton avalanche diode according to Figure 7 or 8.
    Figure 11
    is a partial cross section of a single-photon avalanche diode with low dark count rate.
    Figure 12
    is a partial cross section of a device including single-photon avalanche diodes with low and high dark count rates arranged in the same deep well.


    [0026] Figure 1 is a partial cross section of a single-photon avalanche diode AD1 with relatively high dark count rate. The single-photon avalanche diode AD1 need not be symmetrical, but it may comprise a symmetry. A rotational symmetry is indicated in the figures by the symmetry axis S as an example. The other appended figures show the same portion of the single-photon avalanche diode, so that the differences between the embodiments are evident.

    [0027] The single-photon avalanche diode AD1 comprises a substrate 1 of semiconductor material, which may be silicon, for instance. Doped regions in the substrate 1 have a first type of conductivity or an opposite second type of conductivity. The first type of conductivity may be p-type conductivity, so that the second type of conductivity is n-type conductivity, as indicated in the figures by way of example. The types of conductivity may be reversed. Doping concentrations for either type of conductivity that are sufficiently high for the formation of ohmic contacts on the semiconductor material are respectively indicated by p+ and n+.

    [0028] The substrate 1 may be intrinsically doped or have a low doping concentration for the first type of conductivity. At a main surface 10 of the substrate 1, a shallow well 3 of the first type of conductivity is located in a deep well 2 of the second type of conductivity. A p-n junction 30 is formed between the deep well 2 and the shallow well 3.

    [0029] An isolation region 4, which may be a shallow trench isolation, for instance, can be present where a lateral boundary of the deep well 2 reaches the substrate surface 10. A cover layer 5 of a dielectric material, which locally prevents silicidation of the semiconductor material, may be present on the substrate surface 10. The cover layer 5 can be an oxide of the semiconductor material, in particular silicon nitride, silicon dioxide or a combination of silicon nitride and silicon oxide, for instance.

    [0030] A substrate contact region 6, which has a high doping concentration for the first type of conductivity, may be provided if an electric connection of the substrate 1 is desired. The substrate contact region 6 is formed at the substrate surface 10 and may be arranged in a substrate region 11, which has a doping concentration for the first type of conductivity yielding an electric conductivity that is higher than the basic conductivity of the substrate 1.

    [0031] A deep well contact region 7, which has a high doping concentration for the second type of conductivity, is provided for an electric connection of the deep well 2. The deep well contact region 7 is formed at the substrate surface 10 and may be arranged in a well region 12, which has a doping concentration for the second type of conductivity yielding an electric conductivity that is higher than the basic conductivity of the deep well 2.

    [0032] A shallow well region 8, which has a high doping concentration for the first type of conductivity, is provided for an electric connection of the shallow well 3. The shallow well region 8 is arranged at the substrate surface 10 in the shallow well 3.

    [0033] The high doping concentrations of the regions 6, 7, 8 enable to form ohmic contacts between the semiconductor material and electrically conductive contact layers. In the described examples, the contact layers are provided by optional silicide layers 16, 17, 18. If a cover layer 5 preventing silicidation is provided, the silicide layers 16, 17, 18 are formed in openings of the cover layer 5. Contact plugs 20, 21, 22 may be arranged in a dielectric layer, in particular an intermetal dielectric of a wiring, for instance. Such a dielectric layer is known per se in semiconductor technology, in particular standard CMOS technology, and not shown in the figures. The contact plugs 20, 21, 22 electrically connect the contact layers 16, 17, 18 to respective conductor layers 24, 25, 26, which may be conductor tracks in a structured metallization level of a wiring, for instance. If the silicide layers 16, 17, 18 are not provided, the contact plugs 20, 21, 22 can be applied directly on the regions 6, 7, 8.

    [0034] In the example shown in Figure 1, the contact plug 22 and the corresponding conductor layer 26, which are provided on the shallow well region 8, are rotationally symmetrically arranged on the symmetry axis S. The contact plug 22, the optional contact layer 18 and the corresponding conductor layer 26 can instead be arranged at any suitable position above the shallow well region 8. They may be symmetrical or not symmetrical.

    [0035] A special region, which will be referred to as junction-forming region 13, is present in the deep well 2 under the shallow well 3 at the p-n junction 30 between the deep well 2 and the shallow well 3. The junction-forming region 13 has an elevated doping concentration for the second type of conductivity at least at the p-n junction 30 and thus provides an avalanche region where an avalanche multiplication of charge carriers takes place. A possible location of the avalanche region 33, which is essentially provided by the space-charge region at the p-n junction 30, is schematically indicated by a hatching. The avalanche region 33 may have a different extension and may even reach below the junction-forming region 13.

    [0036] As shown in Figure 1, the junction-forming region 13 may be confined to an area of the p-n junction 30 outside a lateral peripheral region 31 of the shallow well 3. The shallow well region 8 does not essentially extend laterally beyond the junction-forming region 13. In the example shown in Figure 1, the shallow well region 8 is shorter than the junction-forming region 13. Therefore the peripheral region 31 is essentially free from the contact region 8.

    [0037] Irregular occurrences of charge carriers at the interface 32 between the semiconductor material of the substrate 1 and the cover layer 5 may be the reason for an increased dark count rate. For normal operation of a single-photon avalanche diode, a low dark count rate is desired. This can be achieved by a higher doping concentration of the shallow well 3 at the interface 32 between the semiconductor material of the substrate 1 and the cover layer 5 at least above the junction-forming region 13.

    [0038] Figure 11 is a partial cross section of a single-photon avalanche diode AD9 with low dark count rate. Elements of the single-photon avalanche diode AD9 according to Figure 11 corresponding to elements of the single-photon avalanche diode AD1 according to Figure 1 are designated with the same reference numerals primed. In the single-photon avalanche diode AD9 according to Figure 11, the shallow well region 8' extends above the junction-forming region 13' and substantially into the peripheral region 31' of the shallow well 3'. Hence the doping concentration of the shallow well 3' at the interface 32' between the semiconductor material of the substrate 1 and the cover layer 5' is higher than the doping concentration in the rest of the shallow well 3'. The shallow well region 8' is thus appropriate to remove charge carriers that might cause an increase of the dark count rate.

    [0039] In the SPAD device according to embodiments of the invention, at least one single-photon avalanche diode having a low dark count rate, which may be the single-photon avalanche diode AD9 according to Figure 11, is combined with at least one single-photon avalanche diode having a high dark count rate, which may be the single-photon avalanche diode AD1 according to Figure 1. One single-photon avalanche diode of low dark count rate or a plurality of single-photon avalanche diodes of low dark count rate arranged in an array is employed for normal operation of the SPAD device in order to detect or measure according to the intended application. For the purpose of determining the breakdown voltage and adjusting the excess bias voltage, one single-photon avalanche diode of high dark count rate may be sufficient to achieve fast triggering.

    [0040] The single-photon avalanche diodes according to Figures 1 and 11 differ in the dark count rate, but match in the other relevant parameters, in particular the varying levels of the breakthrough voltage at different temperatures. The breakdown voltage of the single-photon avalanche diode having a high dark count rate may be equal to the breakdown voltage of the single-photon avalanche diode having a low dark count rate. It will suffice if the breakdown voltage of the single-photon avalanche diode having a high dark count rate differs from the breakdown voltage of the single-photon avalanche diode having a low dark count rate by less than 10%, especially by less than 2.5%, at 25°C, for instance. The high dark count rate may be at least a factor of 100 higher than the low dark count rate. Practically, the high dark count rate may be several orders of magnitude higher than the low dark count rate.

    [0041] Figure 2 is a partial cross section of a further single-photon avalanche diode AD2 with high dark count rate. Elements of the single-photon avalanche diode AD2 according to Figure 2 corresponding to elements of the single-photon avalanche diode AD1 according to Figure 1 are designated with the same reference numerals. In the single-photon avalanche diode AD2 according to Figure 2, the well region 12 and the junction-forming region 13 have the same depth. In this embodiment, the well region 12 and the junction-forming region 13 can be formed by the same implantation of dopant for the second type of conductivity. Figure 2 also shows a different arrangement of the contact layer 18, the contact plug 22 and the corresponding conductor layer 26, which are provided for the electric connection of the shallow well region 8 and, in the embodiment according to Figure 2, are not arranged on an optional symmetry axis S.

    [0042] Figure 3 is a partial cross section of a further single-photon avalanche diode AD3 with high dark count rate. Elements of the single-photon avalanche diode AD3 according to Figure 3 corresponding to elements of the single-photon avalanche diode AD1 according to Figure 1 are designated with the same reference numerals. In the single-photon avalanche diode AD3 according to Figure 3, the shallow well region 8 extends into the peripheral region 31, as shown in Figure 3, but it is provided with an opening 28 above the junction-forming region 13. The opening 28 may comprise any geometrical shape. It may be symmetrical or symmetrically arranged with respect to an optional symmetry axis S, but a symmetry is not necessary.

    [0043] The arrangement of the highly doped shallow well region 8 in the shallow well 3 according to Figure 3 has the advantage that the device structure in the peripheral region 31 is similar to the single-photon avalanche diode AD9 of low dark count rate according to Figure 11. Thus an excellent match is obtained between the single-photon avalanche diodes of low and high dark count rates, especially with respect to the breakdown voltage at the lateral p-n junction. As the p+ surface layer is missing in the opening 28 above the junction-forming region 13, a high dark count rate is obtained in a manner similar to the single-photon avalanche diode AD1 according to Figure 1.

    [0044] In the single-photon avalanche diode AD3 according to Figure 3, the junction-forming region 13 may be deeper than shown, in particular as deep as in the single-photon avalanche diode AD2 according to Figure 2. The arrangements of all contacts may differ from the arrangements shown in Figure 3, and in particular the contact layer 18, the contact plug 22 and the corresponding conductor layer 26, which are provided for the electric connection of the shallow well region 8, may be symmetrical with respect to an optional symmetry axis S, but a symmetry is not necessary.

    [0045] Figure 4 is a partial cross section of a further single-photon avalanche diode AD4 with high dark count rate. Elements of the single-photon avalanche diode AD4 according to Figure 4 corresponding to elements of the single-photon avalanche diode AD3 according to Figure 3 are designated with the same reference numerals. In the single-photon avalanche diode AD4 according to Figure 4, the shallow well region 8 does not laterally extend all over the peripheral region 31, but its extension is reduced, compared to the shallow well region 8' of the single-photon avalanche diode AD9 according to Figure 11.

    [0046] The shallow well region 8 of the single-photon avalanche diode AD4 according to Figure 4 comprises an opening 28 above the junction-forming region 13. The opening 28 may comprise two or more separate openings, or the areas of the opening 28 that are shown in Figure 4 may be cross sections of connected portions of the opening 28.

    [0047] Figure 5 is a partial cross section of a further single-photon avalanche diode AD5 with high dark count rate. Elements of the single-photon avalanche diode AD5 according to Figure 5 corresponding to elements of the single-photon avalanche diode AD3 according to Figure 3 are designated with the same reference numerals. In the single-photon avalanche diode AD5 according to Figure 5, the cover layer 5 is interrupted above the junction-forming region 13 by a layer sequence that is similar to a gate electrode. The layer sequence comprises a gate oxide 14 on the substrate surface 10 and a polysilicon layer 15 on the gate oxide 14.

    [0048] A further silicide layer 29 may be arranged on the polysilicon layer 15 for an electric connection to a further conductor layer 27 by a further contact plug 23. The conductor layer 26 that is connected to the shallow well region 8 and the further conductor layer 27 may especially be connected to one another or formed by a continuous conductor track, so that the shallow well region 8 and the polysilicon layer 15 are permanently on the same electric potential.

    [0049] The layer sequence including the polysilicon layer 15 locally prevents the formation of a p+ doping within the shallow well 3, so that an opening 28 of the shallow well region 8 is formed under the polysilicon layer 15. The polysilicon layer 15 can be either n-type or p-type polysilicon. The polysilicon layer 15 can be doped together with the implantation of the shallow well region 8. In this case the polysilicon layer 15 comprises the first type of conductivity, which is p-type conductivity in the example shown in Figure 5.

    [0050] Figure 6 is a partial cross section of a further single-photon avalanche diode AD6 with high dark count rate. Elements of the single-photon avalanche diode AD6 according to Figure 6 corresponding to elements of the single-photon avalanche diode AD3 according to Figure 3 are designated with the same reference numerals. In the single-photon avalanche diode AD6 according to Figure 6, the contact layer 18 on the shallow well region 8 has a larger extension compared to the corresponding contact layer 18 of the single-photon avalanche diode AD3 according to Figure 3. The contact layer 18 covers a portion of the junction-forming region 13 and an opening 28 of the shallow well region 8.

    [0051] In the single-photon avalanche diode AD6 according to Figure 6, the contact layer 18 may extend to the peripheral region 31. The contact layer 18 may instead cover a smaller area and may especially not reach to the peripheral region 31, as shown in Figure 6 by way of example. The contact layer 18 may be silicide, which renders a poor quality of the interface 32 between the semiconductor material and the contact layer 18 and thus yields a particularly high dark count rate.

    [0052] When the single-photon avalanche diode AD9 according to Figure 11 is operated in the dark at a temperature below approximately 50°C, it triggers at a very low count rate, which can typically be less than 10 cps (counts per second) at 10°C. The dark count rate of the single-photon avalanche diodes AD1, AD2, AD3, AD4, AD5, AD6 according to Figures 1 to 6 is substantially higher at temperatures below 50°C by orders of magnitude.

    [0053] The single-photon avalanche diodes with high dark count rate AD1, AD2, AD3, AD4, AD5, AD6 according to Figures 1 to 6 match the single-photon avalanche diode AD9 according to Figure 11 with respect to the breakdown voltage. Hence one of the described single-photon avalanche diodes AD1, AD2, AD3, AD4, AD5, AD6 with high dark count rate can ideally be combined with one or more single-photon avalanche diodes AD9 with low count rate on the same semiconductor chip to render a SPAD device that allows excess bias monitoring without use of a light source to accelerate triggering.

    [0054] At least one single-photon avalanche diode with high dark count rate, according to Figures 1 to 6, and one or more single-photon avalanche diodes with low dark count rate, as the one shown in Figure 11, can be arranged in the same SPAD device and in particular in the same deep well 2.

    [0055] Figure 7 is a partial cross section of a further single-photon avalanche diode AD7. Elements of the single-photon avalanche diode AD7 according to Figure 7 corresponding to elements of the single-photon avalanche diode AD1 according to Figure 1 are designated with the same reference numerals. In the single-photon avalanche diode AD7 according to Figure 7, a highly doped region 9 of the second type of conductivity is arranged at the substrate surface 10 in the shallow well 3 at a small distance from the shallow well region 8, which may be confined to a relatively small region.

    [0056] An electric contact on the highly doped region 9 of the second type of conductivity can be formed by a further contact layer 19, which may be a silicide layer, for instance. A further contact plug 23 can be applied to connect the contact layer 19 with a further conductor layer 27. Instead, the further contact plug 23 can directly be applied on the highly doped region 9. The highly doped region 9 enables a precise control of the number of charge carriers injected into the p-n junction 30 by means of the current through the further p-n junction between the highly doped region 9 and the shallow well 3.

    [0057] The arrangement of the highly doped region 9, the shallow well 3 and the junction-forming region 13 forms the structure of a bipolar transistor. The highly doped region 9 corresponds to the emitter, the shallow well 3 to the base, and the junction-forming region 13 to the collector. When an operating voltage for reverse bias above the breakdown voltage is applied to the p-n junction 30, which is the base-collector junction, the triggering of the single-photon avalanche photodiode can be controlled by the emitter current or the base-emitter voltage.

    [0058] In particular, the bipolar transistor is a vertical bipolar transistor. The deep well 2, which provides the collector, has a region that reaches deeper into the substrate 1 than the shallow well 3, which provides the base. The junction-forming region 13 especially is a region of the deep well 2 that is arranged below the shallow well 3. Thus the distance of the junction-forming region 13 from the substrate surface 10 is larger than the distance of the shallow well 3 from the substrate surface 10. Hence the movement of charge carriers of an electric current through the shallow well 3 and the p-n junction 30 has a component in the direction normal to the substrate surface 10.

    [0059] In the SPAD device according to further embodiments of the invention, at least one single-photon avalanche diode having a low dark count rate, which may be the single-photon avalanche diode AD9 according to Figure 11, is combined with at least one single-photon avalanche diode comprising a structure of a bipolar transistor configured for triggering, which may be the single-photon avalanche diode AD7 according to Figure 7. One single-photon avalanche diode of low dark count rate or a plurality of single-photon avalanche diodes of low dark count rate arranged in an array is employed for normal operation of the SPAD device in order to detect or measure according to the intended application. For the purpose of adjusting the excess bias voltage, one single-photon avalanche diode comprising a structure of a bipolar transistor may be sufficient for the purpose of fast triggering.

    [0060] Figure 8 is a partial cross section of a further single-photon avalanche diode AD8 comprising a structure of a bipolar transistor. Elements of the single-photon avalanche diode AD8 according to Figure 8 corresponding to elements of the single-photon avalanche diode AD7 according to Figure 7 are designated with the same reference numerals. In the single-photon avalanche diode AD8 according to Figure 8, the shallow well region 8 extends into the peripheral region 31. The highly doped region 9 of the second type of conductivity is arranged at the substrate surface 10 in the shallow well 3 in an opening 28 of the shallow well region 8. In particular, the bipolar transistor is a vertical bipolar transistor, as described above in conjunction with Figure 7.

    [0061] Figure 9 is a circuit diagram showing the application of a single-photon avalanche diode according to Figure 7 or 8 for the triggering. The components of the circuit can be integrated in the same semiconductor chip. The circuit comprises a bipolar transistor T that is configured to be operated at a reverse collector-to-base voltage VCB exceeding the breakdown voltage BV of the base-collector junction. The bipolar transistor of a single-photon avalanche diode according to Figure 7 or 8 is suitable for an application in the circuit according to Figure 9.

    [0062] A quenching component Q is provided and can be connected between the collector C and a high voltage VHV, as shown in Figure 9. The quenching component Q may comprise a resistor or a transistor, for instance, or an active quenching circuit, which is known per se.

    [0063] In the circuit according to Figure 9, the emitter E of the bipolar transistor T is connected to a capacitor (cap). A first switch S1, a second switch S2 and a third switch S3 allow to connect the capacitor between the ground potential and a dedicated capacitor voltage Vcap or between the ground potential and the emitter E. A typical switching sequence during operation of the device is: 1.) S1 and S3 are closed to charge the capacitor to Vcap; 2.) S1 and S3 are opened; 3.) S2 is closed, so that the capacitor is discharged through the emitter E to trigger the avalanche breakdown.

    [0064] Figure 10 is a further circuit diagram showing the application of a single-photon avalanche diode according to Figure 7 or 8 for the triggering. The components of the circuit can be integrated in the same semiconductor chip. The circuit shown in Figure 10 differs from the circuit shown in Figure 9 in that the quenching component Q is connected to the base B.

    [0065] Figure 12 is a partial cross section of a device including a single-photon avalanche diode with low dark count rate and a single-photon avalanche diode according to one of the Figures 1 to 8, which are arranged in the same deep well. On the left side of Figure 12, the device structure is similar to the single-photon avalanche diode according to Figure 11, and on the right side of Figure 12, the device structure is similar to the embodiment according to Figure 7, by way of example. Each of these single-photon avalanche diodes AD9, AD7 comprises a shallow well 3, 3', a junction-forming region 13, 13' and a shallow well region 8, 8'.

    [0066] In the example shown in Figure 12, the single-photon avalanche diode AD7 comprises a highly doped region 9 of the second type of conductivity, which yields the structure of a bipolar transistor. It can be used to control the triggering of the SPAD device by the applied emitter current or base-emitter voltage.

    [0067] The well region 12/12' and the deep well contact region 7/7' may be arranged between the single-photon avalanche diodes AD9, AD7. A substrate contact may be laterally disposed and is not shown in the cross section of Figure 12. Contacts and optional contact layers can be provided for the doped regions and wells according to the embodiments previously described. Any number of single-photon avalanche diodes with high or low dark count rate or comprising the structure of a bipolar transistor may thus be arranged in the same deep well of the same semiconductor chip. This has the advantage that the integrated single-photon avalanche diodes are relatively close to one another and are therefore exposed to the same ambient conditions, in particular temperature. Furthermore, a close arrangement of the single-photon avalanche diodes enhances the matching of the breakdown voltages.

    List of reference numerals



    [0068] 
    1
    substrate
    2
    deep well
    2'
    deep well
    3
    shallow well
    3'
    shallow well
    4
    isolation region
    4'
    isolation region
    5
    cover layer
    5'
    cover layer
    6
    substrate contact region
    6'
    substrate contact region
    7
    deep well contact region
    7'
    deep well contact region
    8
    shallow well region
    8'
    shallow well region
    9
    highly doped region of the second type of conductivity
    10
    substrate surface
    11
    substrate region
    11'
    substrate region
    12
    well region
    12'
    well region
    13
    junction-forming region
    13'
    junction-forming region
    14
    gate oxide
    15
    polysilicon layer
    16
    contact layer
    16'
    contact layer
    17
    contact layer
    17'
    contact layer
    18
    contact layer
    18'
    contact layer
    19
    contact layer
    20
    contact plug
    20'
    contact plug
    21
    contact plug
    21'
    contact plug
    22
    contact plug
    22'
    contact plug
    23
    contact plug
    24
    conductor layer
    24'
    conductor layer
    25
    conductor layer
    25'
    conductor layer
    26
    conductor layer
    26'
    conductor layer
    27
    conductor layer
    28
    opening
    29
    further silicide layer
    30
    p-n junction
    30'
    p-n junction
    31
    peripheral region
    31'
    peripheral region
    32
    interface
    32'
    interface
    33
    avalanche region
    ADn
    single-photon avalanche diode
    B
    base
    BV
    breakdown voltage
    C
    collector
    cap
    capacitor
    E
    emitter
    Q
    quenching component
    S
    symmetry axis
    S1
    first switch
    S2
    second switch
    S3
    third switch
    T
    bipolar transistor
    Vcap
    capacitor voltage
    VCB
    collector-to-base voltage
    VHV
    high voltage



    Claims

    1. A SPAD device, comprising:

    a single-photon avalanche diode (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) having a breakdown voltage and a dark count rate,

    a further single-photon avalanche diode (AD9) having a further breakdown voltage and a further dark count rate, the dark count rate being at least a factor 100 higher than the further dark count rate at least at one temperature below 25°C, the further single-photon avalanche diode (AD9) being integrated with the single-photon avalanche diode (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8),

    the breakdown voltage being equal to the further breakdown voltage or differing from the further breakdown voltage by less than 10%,

    the single-photon avalanche diode (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) being provided for adjusting or controlling an excess bias voltage, and

    the further single-photon avalanche diode (AD9) being provided for a detection of radiation.


     
    2. The SPAD device according to claim 1, further comprising: a p-n junction (30) of the single-photon avalanche diode (AD7, AD8) forming a base-collector junction of a structure of a bipolar transistor including an emitter region, a base region and a collector region, the bipolar transistor being configured for operation at a reverse collector-to-base voltage (VCB) above a breakdown voltage (BV) .
     
    3. The SPAD device according to claim 2, further comprising:

    a quenching component (Q) electrically connected with the base (B) or the collector (C), and

    a switching circuitry (S1, S2, S3) configured to apply a forward bias to the base-emitter junction.


     
    4. The SPAD device according to one of claims 1 to 3, wherein the breakdown voltage differs from the further breakdown voltage by less than 2.5% at the temperature of 25°C.
     
    5. The SPAD device according to one of claims 1 to 4, further comprising:

    a substrate (1) of semiconductor material,

    the single-photon avalanche diode (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) comprising

    a shallow well (3) of a first type of conductivity in a deep well (2) of an opposite second type of conductivity in the substrate (1), the deep well (2) and the shallow well (3) forming a p-n junction (30),

    a junction-forming region (13) arranged in the deep well (2) under the shallow well (3), the junction-forming region (13) having a doping concentration for the second type of conductivity, at the p-n junction (30) said doping concentration being higher than a doping concentration of the deep well (2) outside the junction-forming region (13), and

    a shallow well region (8) in the shallow well (3), the shallow well region (8) having a doping concentration that is higher than a doping concentration of the shallow well (3) outside the shallow well region (8),

    the further single-photon avalanche diode (AD9) comprising

    a further shallow well (3') of the first type of conductivity in the deep well (2) or in a further deep well (2') of the opposite second type of conductivity in the substrate (1), the further shallow well (3') forming a further p-n junction (30') with the deep well (2) or further deep well (2'),

    a further junction-forming region (13') arranged under the further shallow well (3'), the further junction-forming region (13') having a doping concentration for the second type of conductivity, at the further p-n junction (30') said doping concentration being higher than a doping concentration of the deep well (2) or further deep well (2') outside the further junction-forming region (13'), and a further shallow well region (8') in the further shallow well (3'), the further shallow well region (8') having a doping concentration that is higher than a doping concentration of the further shallow well (3') outside the further shallow well region (8').


     
    6. The SPAD device according to claim 5, further comprising: a peripheral region (31) of the shallow well (3), the peripheral region (31) reaching laterally beyond the junction-forming region (13).
     
    7. The SPAD device according to claim 6, wherein
    the peripheral region (31) of the shallow well (3) is not covered by the shallow well region (8).
     
    8. The SPAD device according to one of claims 5 to 7, further comprising:
    an opening (28) in the shallow well region (8), the opening (28) being arranged above the junction-forming region (13).
     
    9. The SPAD device according to claim 8, further comprising: a polysilicon layer (15) arranged above the opening (28).
     
    10. The SPAD device according to one of claims 5 to 9, further comprising:
    a highly doped region (9) of the second type of conductivity in the shallow well (3) above the junction-forming region (13) at a distance from the p-n junction (30), the highly doped region (9), the shallow well (3) and the junction-forming region (13) respectively forming an emitter region, a base region and a collector region of a structure of a bipolar transistor.
     
    11. The SPAD device according to one of claims 5 to 10, further comprising:
    a deep well contact region (7) in the deep well (2), the deep well contact region (7) having a doping concentration that is higher than a doping concentration of the deep well (2).
     
    12. The SPAD device according to one of claims 5 to 11, wherein
    the shallow well region (8) does not cover the entire junction-forming region (13), and
    the further shallow well region (8') is arranged above the entire further junction-forming region (13').
     


    Ansprüche

    1. SPAD-Vorrichtung, umfassend:

    eine Einzelphoton-Lawinendiode (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) mit einer Durchbruchspannung und einer Dunkelzählrate,

    eine weitere Einzelphoton-Lawinendiode (AD9) mit einer weiteren Durchbruchspannung und einer weiteren Dunkelzählrate, wobei die Dunkelzählrate mindestens bei einer Temperatur unter 25° C um mindestens einen Faktor 100 höher ist als die weitere Dunkelzählrate, wobei die weitere Einzelphoton-Lawinendiode (AD9) in die Einzelphoton-Lawinendiode (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) integriert ist,

    wobei die Durchbruchspannung gleich der weiteren Durchbruchspannung ist oder sich von der weiteren Durchbruchspannung um weniger als 10 % unterscheidet,

    wobei die Einzelphoton-Lawinendiode (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) dazu vorgesehen ist, eine überschüssige Vorspannung einzustellen oder zu steuern, und

    die weitere Einzelphoton-Lawinendiode (AD9) zu einer Strahlungsdetektion vorgesehen ist.


     
    2. SPAD-Vorrichtung nach Anspruch 1, darüber hinaus umfassend:
    einen p-n-Übergang (30) der Einzelphoton-Lawinendiode (AD7, AD8), der einen Basis-Kollektor-Übergang einer Struktur eines Bipolartransistors bildet, der eine Emitter-Zone, eine Basis-Zone und eine Kollektor-Zone aufweist, wobei der Bipolartransistor zum Betrieb bei einer Sperr-Kollektor-Basis-Spannung (VCB) über einer Durchbruchspannung (BV) ausgelegt ist.
     
    3. SPAD-Vorrichtung nach Anspruch 2, darüber hinaus umfassend:

    eine Löschkomponente (Q), die elektrisch mit der Basis (B) oder dem Kollektor (C) verbunden ist, und

    einen Schaltkreis (S1, S2, S3), der dazu ausgelegt ist, eine Vorwärtsspannung an den Basis-Emitter-Übergang anzulegen.


     
    4. SPAD-Vorrichtung nach einem der Ansprüche 1 bis 3, wobei sich die Durchbruchspannung bei der Temperatur von 25° C um weniger als 2,5 % von der weiteren Durchbruchspannung unterscheidet.
     
    5. SPAD-Vorrichtung nach einem der Ansprüche 1 bis 4, darüber hinaus umfassend:

    ein Substrat (1) aus Halbleitermaterial,

    wobei die Einzelphoton-Lawinendiode (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) umfasst

    eine flache Wanne (3) eines ersten Leitfähigkeitstyps in einer tiefen Wanne (2) eines entgegengesetzten, zweiten Leitfähigkeitstyps in dem Substrat (1), wobei die tiefe Wanne (2) und die flache Wanne (3) einen p-n-Übergang (30) bilden,

    eine übergangsbildende Zone (13), die in der tiefen Wanne (2) unter der flachen Wanne (3) angeordnet ist, wobei die übergangsbildende Zone (13) eine Dotierkonzentration für den zweiten Leitfähigkeitstyp hat, wobei am p-n-Übergang (30) die Dotierkonzentration höher ist als eine Dotierkonzentration der tiefen Wanne (2) außerhalb der übergangsbildenden Zone (13), und

    eine Flachwannenzone (8) in der flachen Wanne (3), wobei die Flachwannenzone (8) eine Dotierkonzentration hat, die höher ist als eine Dotierkonzentration der flachen Wanne (3) außerhalb der Flachwannenzone (8),

    wobei die weitere Einzelphoton-Lawinendiode (AD9) umfasst

    eine weitere flache Wanne (3') des ersten Leitfähigkeitstyps in der tiefen Wanne (2) oder in einer weiteren tiefen Wanne (2') des entgegengesetzten, zweiten Leitfähigkeitstyps in dem Substrat (1), wobei die weitere flache Wanne (3') einen weiteren p-n-Übergang (30') mit der tiefen Wanne (2) oder der weiteren tiefen Wanne (2') bildet,

    eine weitere übergangsbildende Zone (13'), die unter der weiteren flachen Wanne (3') angeordnet ist, wobei die weitere übergangsbildende Zone (13') eine Dotierkonzentration für den zweiten Leitfähigkeitstyp hat, wobei an dem weiteren p-n-Übergang (30') die Dotierkonzentration höher ist als eine Dotierkonzentration der tiefen Wanne (2) oder der weiteren tiefen Wanne (2') außerhalb der weiteren übergangsbildenden Zone (13'), und eine weitere Flachwannenzone (8') in der weiteren flachen Wanne (3'), wobei die weitere Flachwannenzone (8') eine Dotierkonzentration hat, die höher ist als eine Dotierkonzentration der weiteren flachen Wanne (3') außerhalb der weiteren Flachwannenzone (8').


     
    6. SPAD-Vorrichtung nach Anspruch 5, darüber hinaus umfassend:
    eine periphere Zone (31) der flachen Wanne (3), wobei die periphere Zone (31) seitlich über die übergangsbildende Zone (13) hinaus reicht.
     
    7. SPAD-Vorrichtung nach Anspruch 6, wobei die periphere Zone (31) der flachen Wanne (3) nicht von der Flachwannenzone (8) bedeckt ist.
     
    8. SPAD-Vorrichtung nach einem der Ansprüche 5 bis 7, darüber hinaus umfassend:
    eine Öffnung (28) in der Flachwannenzone (8), wobei die Öffnung (28) über der übergangsbildenden Zone (13) angeordnet ist.
     
    9. SPAD-Vorrichtung nach Anspruch 8, darüber hinaus umfassend:
    eine Polysiliziumschicht (15), die über der Öffnung (28) angeordnet ist.
     
    10. SPAD-Vorrichtung nach einem der Ansprüche 5 bis 9, darüber hinaus umfassend:
    eine hochdotierte Zone (9) des zweiten Leitfähigkeitstyps in der flachen Wanne (3) über der übergangsbildenden Zone (13) in einem Abstand von dem p-n-Übergang (30), wobei die hochdotierte Zone (9), die flache Wanne (3) und die übergangsbildende Zone (13) jeweils eine Emitter-Zone, eine Basis-Zone und eine Kollektor-Zone einer Struktur eines Bipolartransistors bilden.
     
    11. SPAD-Vorrichtung nach einem der Ansprüche 5 bis 10, darüber hinaus umfassend:
    eine Tiefwannenkontaktzone (7) in der tiefen Wanne (2), wobei die Tiefwannenkontaktzone (7) eine Dotierkonzentration hat, die höher ist als eine Dotierkonzentration der tiefen Wanne (2) .
     
    12. SPAD-Vorrichtung nach einem der Ansprüche 5 bis 11, wobei die Flachwannenzone (8) nicht die gesamte übergangsbildende Zone (13) bedeckt, und
    die weitere Flachwannenzone (8') über der gesamten weiteren übergangsbildenden Zone (13') angeordnet ist.
     


    Revendications

    1. Dispositif SPAD, comprenant:

    une diode à avalanche à photon unique (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) ayant une tension de claquage et un taux de comptage en obscurité,

    une diode à avalanche à photon unique supplémentaire (AD9) ayant une tension de claquage supplémentaire et un taux de comptage en obscurité supplémentaire, le taux de comptage en obscurité étant au moins d'un facteur 100 plus élevé que le taux de comptage en obscurité supplémentaire au moins à une température sous 25 °C, la diode à avalanche à photon unique supplémentaire (AD9) étant intégrée à la diode à avalanche à photon unique (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8),

    la tension de claquage étant égale à la tension de claquage supplémentaire ou différant de moins de 10 % de la tension de claquage supplémentaire,

    la diode à avalanche à photon unique (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) étant prévue pour régler ou commander une tension de polarisation en excès, et

    la diode à avalanche à photon unique supplémentaire (AD9) étant prévue pour une détection de rayonnement.


     
    2. Le dispositif SPAD selon la revendication 1, comprenant en outre:
    une jonction p-n (30) de la diode à avalanche à photon unique (AD7, AD8) formant une jonction base-collecteur d'une structure d'un transistor bipolaire incluant une région d'émetteur, une région de base et une région de collecteur, le transistor bipolaire étant configuré pour fonctionner à une tension collecteur-base (VCB) inverse au-dessus d'une tension de claquage (BV).
     
    3. Le dispositif SPAD selon la revendication 2, comprenant en outre:

    un composant de coupure (Q) électriquement connecté à la base (B) ou au collecteur (C), et

    un circuit de commutation (S1, S2, S3) configuré pour appliquer une polarisation directe à la jonction base-émetteur.


     
    4. Le dispositif SPAD selon l'une des revendications 1 à 3, sachant que la tension de claquage diffère de moins de 2,5 % de la tension de claquage supplémentaire à la température de 25 °C.
     
    5. Le dispositif SPAD selon l'une des revendications 1 à 4, comprenant en outre :

    un substrat (1) de matériau semiconducteur,

    la diode à avalanche à photon unique (AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8) comprenant

    un puits peu profond (3) d'un premier type de conductivité dans un puits profond (2) d'un deuxième type de conductivité opposé dans le substrat (1), le puits profond (2) et le puits peu profond (3) formant une jonction p-n (30),

    une région formant jonction (13) agencée dans le puits profond (2) sous le puits peu profond (3), la région formant jonction (13) ayant une concentration en dopant pour le deuxième type de conductivité, à la jonction p-n (30) ladite concentration en dopant étant plus élevée qu'une concentration en dopant du puits profond (2) à l'extérieur de la région formant jonction (13), et

    une région de puits peu profond (8) dans le puits peu profond (3), la région de puits peu profond (8) ayant une concentration en dopant qui est plus élevée qu'une concentration en dopant du puits peu profond (3) à l'extérieur de la région de puits peu profond (8),

    la diode à avalanche à photon unique supplémentaire (AD9) comprenant

    un puits peu profond supplémentaire (3') du premier type de conductivité dans le puits profond (2) ou dans un puits profond supplémentaire (2') du deuxième type de conductivité opposé dans le substrat (1), le puits peu profond supplémentaire (3') formant une jonction p-n supplémentaire (30') avec le puits profond (2) ou le puits profond supplémentaire (2'),

    une région formant jonction supplémentaire (13') agencée sous le puits peu profond supplémentaire (3'), la région formant jonction supplémentaire (13') ayant une concentration en dopant pour le deuxième type de conductivité, à la jonction p-n supplémentaire (30') ladite concentration en dopant étant plus élevée qu'une concentration en dopant du puits profond (2) ou du puits profond supplémentaire (2') à l'extérieur de la région formant jonction supplémentaire (13'), et

    une région de puits peu profond supplémentaire (8') dans le puits peu profond supplémentaire (3'), la région de puits peu profond supplémentaire (8') ayant une concentration en dopant qui est plus élevée qu'une concentration en dopant du puits peu profond supplémentaire (3') à l'extérieur de la région de puits peu profond supplémentaire (8').


     
    6. Le dispositif SPAD selon la revendication 5, comprenant en outre:
    une région périphérique (31) du puits peu profond (3), la région périphérique (31) s'étendant latéralement au-delà de la région formant jonction (13).
     
    7. Le dispositif SPAD selon la revendication 6, sachant que la région périphérique (31) du puits peu profond (3) n'est pas couverte par la région de puits peu profond (8).
     
    8. Le dispositif SPAD selon l'une des revendications 5 à 7, comprenant en outre:
    une ouverture (28) dans la région de puits peu profond (8), l'ouverture (28) étant agencée au-dessus de la région formant jonction (13).
     
    9. Le dispositif SPAD selon la revendication 8, comprenant en outre:
    une couche de polysilicium (15) agencée au-dessus de l'ouverture (28).
     
    10. Le dispositif SPAD selon l'une des revendications 5 à 9, comprenant en outre:
    une région hautement dopée (9) du deuxième type de conductivité dans le puits peu profond (3) au-dessus de la région formant jonction (13) à une distance de la jonction p-n (30), la région hautement dopée (9), le puits peu profond (3) et la région formant jonction (13) formant respectivement une région d'émetteur, une région de base et une région de collecteur d'une structure d'un transistor bipolaire.
     
    11. Le dispositif SPAD selon l'une des revendications 5 à 10, comprenant en outre:
    une région de contact de puits profond (7) dans le puits profond (2), la région de contact de puits profond (7) ayant une concentration en dopant qui est plus élevée qu'une concentration en dopant du puits profond (2).
     
    12. Le dispositif SPAD selon l'une des revendications 5 à 11, sachant que
    la région de puits peu profond (8) ne couvre pas toute la région formant jonction (13), et
    la région de puits peu profond supplémentaire (8') est agencée au-dessus de toute la région formant jonction supplémentaire (13').
     




    Drawing





















    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description