(19)
(11)EP 3 474 134 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
13.09.2023 Bulletin 2023/37

(21)Application number: 18200110.7

(22)Date of filing:  12.10.2018
(51)International Patent Classification (IPC): 
G06F 7/58(2006.01)
G06N 3/084(2023.01)
(52)Cooperative Patent Classification (CPC):
G06N 3/084; G06F 7/582

(54)

GENERATING RANDOMNESS IN NEURAL NETWORKS

ERZEUGUNG VON ZUFÄLLIGKEIT IN NEURONALEN NETZWERKEN

GÉNÉRATION DE CARACTÈRE ALÉATOIRE DANS DES RÉSEAUX NEURONAUX


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 20.10.2017 GB 201717309

(43)Date of publication of application:
24.04.2019 Bulletin 2019/17

(73)Proprietor: Graphcore Limited
Bristol BS1 2PH (GB)

(72)Inventors:
  • FELIX, Stephen
    Bristol, BS6 5BN (GB)
  • DA COSTA, Godfrey
    Bristol, BS6 6LX (GB)

(74)Representative: Page White Farrer 
Bedford House 21a John Street
London WC1N 2BF
London WC1N 2BF (GB)


(56)References cited: : 
GB-A- 2 076 570
US-A- 4 218 749
US-A- 3 984 668
US-A1- 2012 303 691
  
  • Anonymous: "Add d3.random.bates; fix d3.random.irwinHall. by mbostock . Pull Request #1656 . d3/d3 . GitHub", , 14 December 2013 (2013-12-14), pages 1-2, XP055742849, Retrieved from the Internet: URL:https://github.com/d3/d3/pull/1656/com mits/c5e2d3d843e2a5f294fb3dc86051364b305e0 ea8 [retrieved on 2020-10-22]
  • ANONYMOUS ED - ANONYMOUS: "Linear feedback shift register", INTERNET CITATION, 4 June 2010 (2010-06-04), pages 1-8, XP002657807, Retrieved from the Internet: URL:http://en.wikipedia.org/w/index.php?ti tle=Linear_feedback_shift_register&oldid=3 65970839 [retrieved on 2011-08-26]
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Technical Field



[0001] The present disclosure relates to generating randomness in neural networks.

Background



[0002] Neural networks are used in the field of machine learning and artificial intelligence. Neural networks comprise arrangements of sets of nodes which are interconnected by links and which interact with each other. The principles of neural networks in computing are based on information about how electrical stimuli convey information in the human brain. For this reason the nodes are often referred to as neurons. They may also be referred to as vertices. The links are sometimes referred to as edges. The network can take input data and certain nodes perform operations on the data. The result of these operations is passed to other nodes. The output of each node is referred to as its activation or node value. Each link is associated with a weight. A weight defines the connectivity between nodes of the neural network. Many different techniques are known by which neural networks are capable of learning, which takes place by altering values of the weights.

[0003] Figure 1 shows an extremely simplified version of one arrangement of nodes in a neural network. This type of arrangement is often used in learning or training and comprises an input layer of nodes, a hidden layer of nodes and an output layer of nodes. In reality, there will be many nodes in each layer, and nowadays there may be more than one layer per section. Each node of the input layer Ni is capable of producing at its output an activation or node value which is generated by carrying out a function on data provided to that node. A vector of node values from the input layer is scaled by a vector of respective weights at the input of each node in the hidden layer, each weight defining the connectivity of that particular node with its connected node in the hidden layer. In practice, networks may have millions of nodes and be connected multi-dimensionally, so the vector is more often a tensor. The weights applied at the inputs of the node Nh are labelled w0....w2. Each node in the input layer is connected at least initially to each node in the hidden layer. Each node in the hidden layer can perform an activation function on the data which is provided to them and can generate similarly an output vector which is supplied to each of the nodes N0 in the output layer 0. Each node weights its incoming data, for example by carrying out the dot product of the input activations of the node and its unique weights for the respective incoming links. It then performs an activation function on the weighted data. The activation function can be for example a sigmoid. See Figure 1A. The network learns by operating on data input at the input layer, assigning weights to the activations from each node and acting on the data input to each node in the hidden layer (by weighing it and performing the activation function). Thus, the nodes in the hidden layer operate on the weighted data and supply outputs to the nodes in the output layer. Nodes of the output layer may also assign weights. Each weight is characterised by a respective error value. Moreover, each node may be associated with an error condition. The error condition at each node gives a measure of whether the error in the weight of the node falls below a certain level or degree of acceptability. There are different learning approaches, but in each case there is a forward propagation through the network from left to right in Figure 1, a calculation of overall error, and a backward propagation from right to left in Figure 1 through the network of the error. In the next cycle, each node takes into account the back propagated error and produces a revised set of weights. In this way, the network can be trained to perform its desired operation.

[0004] One problem which can arise with a neural network is "overfitting". Large networks with millions or billions of parameters (weights) can easily overfit. Overfitting causes a network to remember each training sample that has been provided to it (a training sample providing data to the input nodes), rather than be trained to extract relevant features so that the neural net is appropriate, after it has been trained, for application to more generally extract features from samples. A wide range of techniques has been developed to solve this problem by regularising neural networks to avoid overfitting/memorising.

[0005] When processing large datasets using neural nets, there are techniques involving the use of random numbers which can improve their performance. One technique is so-called Monte Carlo sampling which is a term used for a broad class of computational algorithms that rely on repeated random sampling to obtain numerical results. The underlying idea of Monte Carlo sampling is that randomness may be able to solve problems that might be deterministic in principle. When using Monte Carlo sampling, a prescribed probability distribution of the random numbers is desirable. Monte Carlo sampling can be used for example in generative models.

[0006] Techniques have recently been devised for improving the performance of neural nets by adding random noise to weights or activations. Gaussian noise has been explored as a possibility in this respect.

[0007] Implementing neural networks using known computer technology has various challenges. Implementing randomising techniques, for example using a CPU or GPU is non-trivial and may impact the full benefits that could be achieved with efficient implementation.

[0008] US Patent number 3984668 describes a method is obtained for generating pseudo-random bit sequence words which is characterized in that the bit contents of a given number of elements of the main register are used as an address for reading out from a memory of a corresponding superposition bit sequence of a length equal to the length of the main register and the bit sequence of a number of given elements of the main register are selected as a first word of the series.

[0009] US Patent number 4218749 describes a method of generating a random distributed noise signal. The pseudo-random bit generator receives clock pulses from a clock and simultaneously generates, at each clock pulse, a plurality of n parallel pseudo-random bits. A summing circuit is operative, at each clock pulse, to sum the value of the pseudo random bits output by the pseudo random bit generator to produce a noise signal allegedly exhibiting a substantially Gaussian distribution with time.

[0010] GB Patent Application Publication no 2076570 A describes a random number generator allegedly providing substantially-random numbers with a substantially-Gaussian probability distribution. The generator comprises a 24-bit shift register forming a chain code generator, the numbers defined by each of four groups of six bits, being added in an adder. The generator is applied to an airbrush simulator for an electronic graphic system, in which it constitutes a dedicated- hardware peripheral to supply random numbers to a computer controller, these random numbers being used to modify which storage locations are addressed in response to the output of a two-dimension graphics tablet.

[0011] US 2012/303691 A1 discloses a random number generator based on Perlin noise functions.

Summary



[0012] The present inventors have developed an execution unit for a processor which can efficiently provide, responsive to execution of a program instruction, random values from a predetermined, almost Gaussian, distribution.

[0013] According to one aspect of the invention there is provided an execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution, the execution unit comprising:

a hardware pseudorandom number generator configured to generate at least one randomised bit string on execution of the instruction;

adding circuitry configured to receive a number of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result.



[0014] The execution unit can include normalising circuitry configured to receive the result and to generate a normalised result to centre the predetermined probability distribution at a selected known value and/or to adjust the variance of the distribution to a selected known value.

[0015] The hardware pseudorandom number generator may be configured to generate two or more randomised bit strings on execution of the instruction, and the adding circuitry may be configured to produce two or more results from two or more respective summations.

[0016] In one embodiment, the normalising circuitry comprises a lookup table configured to receive each result and to provide the normalised result. However, any implementation may be utilised. The normalising circuitry can carry out the functions of subtracting a predetermined number from the result, the predetermined number being calculated as half the total possible number range of results produced by the adding circuitry, converting to a floating point format and dividing by a divisor. The divisor can be the number of any possible values of uniformly distributed random variables having the predetermined bit length.

[0017] In one embodiment, the number of bit sequences is twelve. The number twelve has been found to be a good compromise for the number of bit sequences taking into account the required distribution, and hardware optimisation for certain applications. The distribution can be an Irwin-Hall distribution. Each sequence may have any suitable number of bits. It is five in the described embodiment, but this by way of non limiting example only.

[0018] The normalising circuitry may be configured to subtract 186 from the result (where the number range of results is 372).

[0019] The execution unit can comprise summing circuitry which sums together results from a plurality of the computer program instructions to more accurately fit the predetermined probability distribution. It may further comprise circuits for combining the outputs from the pseudorandom number generator with the results from the computer program instruction.

[0020] A corresponding method and computer program are also provided.

[0021] One aspect provides a method of executing a computer program instruction to generate random numbers based on a predetermined probability distribution, the method comprising:

generating at least one randomised bit string on execution of the instruction;

selecting a number of bit sequences of a predetermined bit length from the randomised bit string and summing them to produce a result. Another aspect provides a computer program product comprising a computer program which comprises a computer program instruction recorded on a non transmissible medium which when executed carries out the aforementioned method.



[0022] The invention is defined by the appended claims.

[0023] For a better understanding of the present invention and to show the same may be carried into effect, reference will now be made by way of example only to the following drawings.

Brief Description of the Drawings



[0024] 

Figure 1 is a highly simplified schematic view of a neural net;

Figure 1A is a highly simplified schematic view of a neuron;

Figure 2 is a schematic diagram of a processing unit in accordance with an embodiment of the invention;

Figure 3 shows on a log and normal plot the difference between a normal Gaussian distribution and an Irwin-Hall distribution.

Figure 4 is a block diagram of an execution unit for implementing the masking instruction;

Figure 5 shows the performance improvement by summing results of multiple grand instructions;

Figure 6 illustrates conversion from an f16 value to an f32 value;

Figures 7 and 8 are graphs comparing distributions.


Detailed Description



[0025] Figure 2 shows a schematic block diagram of an execution unit arranged to execute a single instruction for generating random values from a predetermined probability distribution. The instruction is referred to herein as the grand instruction. The execution unit 2 forms part of a pipeline 4 in a processing unit. The processing unit comprises an instruction fetch unit 6 which fetches instruction from an instruction memory 10. The processing unit also comprises a memory access stage 8 which is responsible for accessing a data memory 12 for loading data from the memory or storing data into the memory. A set of registers 14 is provided for holding source and destination operands for the instructions being executed at any instance by the pipeline 4. It will readily be understood that the pipeline 4 may contain many different types of execution unit for executing a variety of different instructions, for example for performing mathematical operations. One type of processing unit which may be useful with the present invention is a processing unit using barrel-threaded time slots, in which a supervisor thread may allocate different worker threads to different time slots for their execution. The grand instruction described herein may be used with any suitable processing unit architecture.

[0026] The execution unit 2 comprises a hardware pseudo random number generator 22 which generates pseudo random numbers when requested by the instruction. The numbers each take the form of a randomised sequence of 64 bits. The execution unit 2 also comprises a grand instruction execution module 23 and an output buffer 27 for holding the result of execution of the instruction.

[0027] There are two versions of the instruction. The first, f16v2grand$aDST returns two random 16-bit values from a predetermined probability distribution of random values into a register or memory location DST. A second version of the instruction f32v2grand$aDST returns two 32-bit values from the same distribution into a register or memory location DST. The technique implemented by the grand instruction module 23 provides a distribution which is close to an Irwin-Hall distribution. As explained herein, the Irwin-Hall distribution is very similar to a Gaussian in distribution. The Irwin Hall Distribution is a probability distribution for a random variable defined as the sum of a number of independent random variables each having a uniform distribution. It is sometimes referred to as the uniform sum distribution, although it has Gaussian characteristics. Figure 3 illustrates a quantized Irwin-Hall distribution where the number of independent random variables which are summed is 12 compared to a quantized normal distribution. This compares closely to a curve of Gaussian distribution shown with a variance of one and a mean of zero. The top graph in Figure 3 is on a log scale, and the lower graph is on an ordinary scale. The probability density function (PDF) is within 20% of Gaussian up to 3 sigma. The cumulative distribution function (CDF) probability differs from Gaussian by less than +/- 0.0024 (about 1%). To all intents and purposes it is a distribution of random numbers which serves the purposes described above for improving the performance of neural nets in a very satisfactory manner.

[0028] In the described embodiment, when the grand instruction is executed by the execution unit the PRNG 22 produces two 64-bit wide outputs res 0, res 1. It will be understood that it would be possible to utilise the principle of the present invention with only a single output being produced, but it is more efficient for two outputs to be produced so as to generate two random numbers responsive to a single instruction. The intermediate 64-bit wide PRNG outputs res 0, res 1 are compressed to nine bits by summing twelve constituent 5 bit fields as indicated below. Figure 4 illustrates schematically the addition function represented below as being implemented by two adders 40a, 40a, each adder receiving input sequences from a respective randomised bit string. Each adder has twelve inputs, and each input is 5 bits wide. The top 4 bits of each input string is discarded. assign rsum0[8:0] = res0[4:0] + res0[9:5] + res0[14:10] + res0[19:15] + res0[24:20] + res0[29:25] + res0[34:30] + resD[39:35] + res0[44:40] + res0[49:45] + res0[54:50] + res0[59:55] + assign rsum1[8:0] = res1[4:0] + res1[9:5] + res1[14:10] + resl[19:15] + resl[24:20] + resl[29:25] + res1[34:30] + res1[39:35] + res1[44:40] + res1[49:45] + res1[54:50] + res1[59:55] +

[0029] The resulting unsigned 9 bit sums (RESULT 1, RESULT 2) are in the range 0 to 372 inclusive. It will be understood that different number ranges could be produced by selecting a different number of bit sequences from the randomised bit strings, and also by changing the number of bits within each bit sequence. For any particular number of sequences/length of sequence, the adders will produce a set of results in a defined number range.

[0030] Two twelve input adders are shown for convenience, although it will be appreciated that other adding circuitry configurations may be utilised. The choice of summing 12 uniformly distributed random variables is an optimisation based on:
  1. 1) a reasonable trade-off between closeness to a normal (Gaussian) distribution and hardware cost; and
  2. 2) doing so happens to produce a distribution with a standard deviation of 1 rather than an awkward fraction, which simplifies the hardware needed to scale the integer to a floating point value with standard deviation of 1.


[0031] The summation results RESULT 1, RESULT 2 are then processed in normalising circuitry 42 so as to provide a normalised curve. Without this normalisation, the number range of the results would extend from 0 to 372 and would not be centred around 0. The normalising circuitry performs a subtract function which subtracts 186 from the result to recentre to the range on 0. This number 186 is a half of 372. It will be appreciated that if there was a different number range, there would be a different subtraction value (half the number range).

[0032] The results should be in floating point format to correspond to the required precision, as shown in the convert to f16 block in the normalising circuitry 42?

[0033] A divide stage divides the floating point numbers by 32 to produce a distribution with very similar attributes to a standard normal distribution (in particular to approximate the standard deviation as close as possibly to 1). Division by 32 is simple to achieve in binary arithmetic since, being a power of 2, it requires a fixed shift or exponent adjustment. 32 is the number of possible values of a single, 5-bit uniformly distributed random variable. Note that if the number of n of selected sequences was not 12, it would need to scaled by 32n/12.

[0034] In the described embodiment, the normalising circuitry is implemented by lookup table 42. However, it will be appreciated that it could be implemented in any suitable form. In one arrangement, the lookup table can be synthesised into logic gates.

[0035] As mentioned above, there are two versions of the instruction. The version which has been described above is f16v2grand. In the alternate version f32v2grand, the output is two f32 values instead of two f16 values. There is no need for another lookup table or similar, because the bits of the required f32 output values can be derived from the respective fl6 results V1, V2 according to the following manipulations, carried out by conversion logic 44. assign f32result0[31:0] = {fpresult0[15:14],4'(fpresult0[13]},fpresult0[12:3],16'b0}; assign f32result1[31:0] = {fpresult1[15:14],4'{fpresult1[13]},fpresult1[12:3],16'b0}; assign aDst[63:0] - {f32result1,f32result0};

[0036] That is, a 32 bit sequence is derived by taking bits 14 and 15 of the VI (f16) result, replicating bit 13 4 times, taking bits 3 to 12 and completing with 16 zeroes. This is shown in Figure 6.

[0037] Reverting to Figure 3, each point on the graph represents one of the 384 possible values generated by summing twelve 5-bit values. The probability distribution function remains Gaussian up to approximately 3.5 sigma beyond which the tails of the distribution fade faster than would be the case in a normal distribution. The most extreme outputs are +/- 5.8125 sigma, but with an extremely low probability. The closest known distribution is a continuous non-quantized 12th order Irwin-Hall distribution, but it will be understood that the particular distribution below is unique based on the manner by which it is generated.

[0038] It is possible to more closely approximate to a normal distribution by summing pseudo Gaussian scalars from multiple grand instructions. As already mentioned, the tail of the Irwin-Hall probability distribution function diminish magnitude more rapidly than those of an ideal normal distribution. This can be remedied by summing multiple scalar outputs from multiple grand instructions. The curves in Figure 5 show how many scalars need to be summed in order to achieve a probability distribution function (or cumulative distribution function) with tails that are within 1%, 10% or 2 x an ideal normal distribution up to a maximum number of standard deviations (sigma). For example, each scalar output from an f16v2 grand instruction is a sum of 12 uniformly distributed pseudo random values and the tails are within 10% of an ideal normal distribution up to 2.8 sigma.

[0039] To sum 12 grand instruction scalar outputs (a 144th order Irwin-Hall distribution); the grand instruction should be executed 6 times and all 12 of the resulting scalar values summed. The final sum is the divided by sqrt (12) to retain a standard deviation of 1.

[0040] The output of the grand instruction can be used in combination with a sum of other uniformly distributed random variables to generate a 2-sigma or 3-sigma truncated normal distribution, An algorithm to generate a 2-sigma resp (3-sigma) can operate to generate two (resp.three) 'uniforms', each uniform being a random number from uniformly distributed random variables in the range -1 to +1 (from the PRNG), and sum them. Then for a 2-sigma distribution two normally distributed values N1, N2 are generated using the grand instruction described earlier. (For a 3-sigma distribution, a single normally distributed value N1 is generated). Note that N1, N2 correspond to outputs V1, V2 discussed earlier.

[0041] For the 2-sigma distribution, where |N1| or |N2| are greater than 2, the sum of uniforms is used as the output.

[0042] For the 3-sigma distribution, where |N1| is greater than 3, the sum of the uniforms is used instead.

[0043] The sum of two uniform random variables has the PDF (probability distribution function) represented by curve (a) in Figure 6: only very roughly Gaussian, but definitely limited to +- 2 sigma. The truncated Gaussian distribution that the algorithm is trying to match is illustrated by curve (b).

[0044] If both of the Gaussian variables are out of range (beyond 2 sigma) then the sum of two uniforms is used instead.

[0045] Since it is unlikely that both Gaussians are out of range; the sum of two uniforms is used only rarely (about 1/500 times) and its effect on the average distribution is therefore very slight.

[0046] The algorithm for generating 3-sigma truncated Gaussian values is slightly different. This time only one Gaussian variable is needed because the likelihood of a single value exceeding 3-sigma range is already slight (about 1/500).

[0047] The sum of three uniform random variables has the PDF represented by the curve (a) in Figure 7. It is roughly Gaussian and definitely limited to +-3 sigma. The truncated Gaussian distribution that the algorithm is trying to match is illustrated by curve (b). If the Gaussian variable is out of range (beyond 3 sigma) then the sum of three uniforms is used instead.

[0048] The error of the resulting distribution is very small since the sum of 3 uniforms is already a fairly good approximation of a 3-sigma truncated Gaussian distribution and it is used only ~1/1500 times.

[0049] The term `random` used herein can mean' truly random 'or 'pseudorandom '. The grand instruction could use either a pseudorandom or a true random bit sequence generator.

[0050] Pseudorandom numbers are generated by a `pseudorandom number generator' or 'PRNG'. PRNG's can be implemented in software or hardware. True random numbers are generated by a 'true random number generator' or 'TRNG'. An example of a TRNG is a "Transition Effect Ring Oscillator". An advantage of PRNGs over TRNGs is determinism (running the same program twice with the same starting conditions always has the same result).

[0051] An advantage of TRNGs over PRNGs is that the output is truly random (while the output of a PRNG satisfies a finite set of arbitrarily chosen mathematical properties; the state and output of a PRNG is always predictable from the current state and therefore not truly random).

[0052] While particular embodiments have been described, other applications and variance of the disclosed techniques may become apparent to a person skilled in the art once given the disclosure hearing. The scope of the present disclosure is not limited by the described embodiments but only by the accompanying claims.


Claims

1. An execution unit (2) in a processor, the execution unit being configured to execute a computer program instruction fetched from instruction memory (10) of the processor to generate random numbers based on a predetermined probability distribution, the execution unit (2) comprising:

a hardware pseudorandom number generator (22) configured to generate at least randomised bit string on execution of the instruction by the execution unit (2); and

adding circuitry (40a, 40b) configured to receive a plurality of bit sequences of a predetermined bit length selected from the randomised bit string and to sum them to produce a result,

wherein the plurality of bit sequences are uniformly distributed random variables.


 
2. An execution unit (2) according to claim 1, wherein the hardware pseudorandom number generator (22) is configured to generate two or more randomised bit strings on execution of the instruction, and wherein the adding circuitry (40a, 40b) is configured to produce two or more results from two or more respective summations.
 
3. An execution unit (2) according to claim 1 or claim 2, comprising normalising circuitry (42) configured to receive the result and to generate a normalised result to at least one of:

centre the predetermined probability distribution at a selected known value; and

adjust the variance of the distribution to a selected known value.


 
4. An execution unit (2) according to claim 3, wherein the normalising circuitry (42) comprises a lookup table configured to receive each result and to provide the normalised result.
 
5. An execution unit (2) according to claim 3 or claim 4, wherein the normalising circuitry (42) subtracts a predetermined number from the result, the predetermined number being calculated as half the total possible number range of results produced by the adding circuitry (40a, 40b).
 
6. An execution unit (2) according to any preceding claim, wherein the plurality of bit sequences consists of 12 bit sequences.
 
7. An execution unit (2) according to claim 6 when dependent upon claim 3, wherein the normalising circuitry (42) is configured to subtract 186 from the result.
 
8. An execution unit (2) according to any of claims 3 to 5 or claim 7, wherein the normalising circuitry (42) is configured to divide by a number which is the number of possible values of uniformly distributed random variables having the predetermined bit length.
 
9. An execution unit (2) according to any preceding claim wherein the bit length of each sequence is 5.
 
10. An execution unit (2) according to claim 8, wherein the normalising circuitry (42) is configured to divide by 32.
 
11. An execution unit (2) according to any preceding claim, wherein the predetermined probability distribution approximates a scaled, offset, quantized Irwin-Hall distribution.
 
12. An execution unit (2) according to any preceding claim, comprising summing circuitry which sums together results from a plurality of the computer program instructions to more accurately fit the predetermined probability distribution.
 
13. An execution unit (2) according to any preceding claim, configured to combine one or more bit sequences from the randomised bit string with one or more normalised results.
 
14. An execution unit according to any preceding claim, comprising conversion logic (44) operable to convert a result of length 16 bits to a result of length 32 bits.
 
15. A method of executing a computer program instruction to generate random numbers based on a predetermined probability distribution, the method implemented in an execution unit (2) of a processor and comprising:

generating, when the computer program instruction is executed by the execution unit (2), at least one randomised bit string on execution of the instruction;

selecting a plurality of bit sequences of a predetermined bit length from the

randomised bit string and summing them to produce a result,

wherein the plurality of bit sequences are uniformly distributed random variables.
 
16. A computer program product comprising a computer program which comprises a computer program instruction recorded on non transmissible media which when executed carries out a method of generating random numbers based on a predetermined probability distribution, the method implemented in an execution unit (2) of a processor comprising:

generating at least one randomised bit string on execution of the instruction by the execution unit (2);

selecting a plurality of bit sequences of a predetermined bit length from the

randomised bit string and summing them to produce a result,

wherein the plurality of bit sequences are uniformly distributed random variables.
 


Ansprüche

1. Ausführungseinheit (2) in einem Prozessor, wobei die Ausführungseinheit konfiguriert ist, um einen Computerprogrammbefehl auszuführen, der aus dem Befehlsspeicher (10) des Prozessors abgerufen wird, um Zufallszahlen basierend auf einer vorbestimmten Wahrscheinlichkeitsverteilung zu erzeugen, wobei die Ausführungseinheit (2) aufweist:

einen Hardware-Pseudozufallszahlengenerator (22), der konfiguriert ist, um bei Ausführung des Befehls durch die Ausführungseinheit (2) mindestens eine zufällige Bitfolge zu erzeugen; und

eine Additionsschaltung (40a, 40b), die konfiguriert ist, um mehrere Bitsequenzen einer vorbestimmten Bitlänge zu empfangen, die aus der zufälligen Bitfolge ausgewählt sind, und um sie zu summieren, um ein Ergebnis zu erzeugen,

wobei die mehreren Bitsequenzen gleichmäßig verteilte Zufallsvariablen sind.


 
2. Ausführungseinheit (2) nach Anspruch 1, wobei der Hardware-Pseudozufallszahlengenerator (22) konfiguriert ist, um bei Ausführung des Befehls zwei oder mehr zufällige Bitfolgen zu erzeugen, und wobei die Additionsschaltung (40a, 40b) konfiguriert ist, um zwei oder mehr Ergebnisse aus zwei oder mehr jeweiligen Summierungen zu erzeugen.
 
3. Ausführungseinheit (2) nach Anspruch 1 oder Anspruch 2, aufweisend eine Normalisierungsschaltung (42), die konfiguriert ist, um das Ergebnis zu empfangen und ein normalisiertes Ergebnis zu erzeugen, um wenigstens eines zu erreichen von:

Zentrieren der vorbestimmten Wahrscheinlichkeitsverteilung auf einen ausgewählten bekannten Wert; und

Anpassen der Varianz der Verteilung an einen ausgewählten bekannten Wert.


 
4. Ausführungseinheit (2) nach Anspruch 3, wobei die Normalisierungsschaltung (42) eine Nachschlagetabelle aufweist, die konfiguriert ist, um jedes Ergebnis zu empfangen und das normalisierte Ergebnis bereitzustellen.
 
5. Ausführungseinheit (2) nach Anspruch 3 oder Anspruch 4, wobei die Normalisierungsschaltung (42) eine vorbestimmte Zahl vom Ergebnis subtrahiert, wobei die vorbestimmte Zahl als die Hälfte des gesamten möglichen Zahlenbereichs der von der Additionsschaltung (40a, 40b) erzeugten Ergebnisse berechnet wird.
 
6. Ausführungseinheit (2) nach einem der vorhergehenden Ansprüche, wobei die Anzahl der Bitfolgen aus 12 Bitfolgen besteht.
 
7. Ausführungseinheit (2) nach Anspruch 6, wenn abhängig von Anspruch 3, wobei die Normalisierungsschaltung (42) konfiguriert ist, um 186 vom Ergebnis zu subtrahieren.
 
8. Ausführungseinheit (2) nach einem der Ansprüche 3 bis 5 oder Anspruch 7, wobei die Normalisierungsschaltung (42) konfiguriert ist, um durch eine Zahl zu dividieren, welche die Anzahl möglicher Werte von gleichmäßig verteilten Zufallsvariablen mit der vorgegebenen Bitlänge ist.
 
9. Ausführungseinheit (2) nach einem der vorhergehenden Ansprüche, wobei die Bitlänge jeder Sequenz 5 ist.
 
10. Ausführungseinheit (2) nach Anspruch 8, wobei die Normalisierungsschaltung (42) konfiguriert ist, um durch 32 zu teilen.
 
11. Ausführungseinheit (2) nach einem der vorhergehenden Ansprüche, wobei die vorgegebene Wahrscheinlichkeitsverteilung eine skalierte, versetzte, quantisierte Irwin-Hall-Verteilung approximiert.
 
12. Ausführungseinheit (2) nach einem der vorhergehenden Ansprüche, aufweisend eine Summierschaltung, die Ergebnisse aus mehreren Computerprogrammbefehlen summiert, um die vorgegebene Wahrscheinlichkeitsverteilung genauer anzupassen.
 
13. Ausführungseinheit (2) nach einem der vorhergehenden Ansprüche, die konfiguriert ist, um ein oder mehr Bitsequenzen aus der randomisierten Bitfolge mit ein oder mehr normalisierten Ergebnissen zu kombinieren.
 
14. Ausführungseinheit nach einem der vorhergehenden Ansprüche, aufweisend eine Konvertierungslogik (44), die betreibbar ist, um ein Ergebnis der Länge von 16 Bits in ein Ergebnis der Länge von 32 Bits umzuwandeln.
 
15. Verfahren zum Ausführen eines Computerprogrammbefehls zum Erzeugen von Zufallszahlen basierend auf einer vorbestimmten Wahrscheinlichkeitsverteilung, wobei das Verfahren in einer Ausführungseinheit (2) eines Prozessors implementiert ist und aufweist:

Erzeugen, wenn der Computerprogrammbefehl von der Ausführungseinheit (2) ausgeführt wird, wenigstens einer zufälligen Bitfolge bei Ausführung des Befehls;

Auswählen mehrerer Bitsequenzen einer vorbestimmten Bitlänge aus der zufälligen Bitfolge und Summieren derselben, um ein Ergebnis zu erzeugen,

wobei die mehreren Bitsequenzen gleichmäßig verteilte Zufallsvariablen sind.


 
16. Computerprogrammprodukt mit einem Computerprogramm, das einen auf nicht übertragbaren Medien aufgezeichneten Computerprogrammbefehl aufweist, der, wenn er ausgeführt wird, ein Verfahren des Erzeugens von Zufallszahlen basierend auf einer vorbestimmten Wahrscheinlichkeitsverteilung ausführt, wobei das in einer Ausführungseinheit (2) eines Prozessors implementierte Verfahren aufweist:

Erzeugen wenigstens einer zufälligen Bitfolge bei Ausführung des Befehls durch die Ausführungseinheit (2);

Auswählen mehrerer Bitsequenzen einer vorbestimmten Bitlänge aus der zufälligen Bitfolge und Summieren derselben, um ein Ergebnis zu erzeugen,

wobei die mehreren Bitsequenzen gleichmäßig verteilte Zufallsvariablen sind.


 


Revendications

1. Unité d'exécution (2) dans un processeur, l'unité d'exécution étant configurée pour exécuter une instruction de programme informatique extraite d'une mémoire d'instruction (10) du processeur pour générer des nombres aléatoires sur la base d'une distribution de probabilité prédéterminée, l'unité d'exécution (2) comprenant :

un générateur de nombres pseudo-aléatoires de matériel (22) qui est configuré pour générer au moins une chaîne aléatoire de bits lors de l'exécution de l'instruction par l'unité d'exécution (2) ; et

un ensemble de circuits additionneurs (40a, 40b) qui est configuré pour recevoir une pluralité de séquences de bits d'une longueur en bits prédéterminée qui est sélectionnée à partir de la chaîne aléatoire de bits, et pour les additionner afin de produire un résultat,

dans laquelle la pluralité de séquences de bits sont des variables aléatoires uniformément distribuées.


 
2. Unité d'exécution (2) selon la revendication 1, dans laquelle le générateur de nombres pseudo-aléatoires de matériel (22) est configuré pour générer au moins deux chaînes aléatoires de bits lors de l'exécution de l'instruction, et dans laquelle l'ensemble de circuits additionneurs (40a, 40b) est configuré pour produire au moins deux résultats à partir d'au moins deux additions respectives.
 
3. Unité d'exécution (2) selon la revendication 1 ou 2, comprenant un ensemble de circuits de normalisation (42) qui est configuré pour recevoir le résultat et pour générer un résultat normalisé pour effectuer au moins l'une de ces étapes :

centrer la distribution de probabilité prédéterminée sur une valeur connue sélectionnée ; et

ajuster la variance de la distribution à une valeur connue sélectionnée.


 
4. Unité d'exécution (2) selon la revendication 3, dans laquelle l'ensemble de circuits de normalisation (42) comprend une table de correspondance qui est configurée pour recevoir chaque résultat et pour fournir le résultat normalisé.
 
5. Unité d'exécution (2) selon la revendication 3 ou 4, dans laquelle l'ensemble de circuits de normalisation (42) soustrait un nombre prédéterminé au résultat, le nombre prédéterminé étant calculé comme étant la moitié du total de la plage de nombres possibles de résultats produits par l'ensemble de circuits additionneurs (40a, 40b).
 
6. Unité d'exécution (2) selon l'une quelconque des revendications précédentes, dans laquelle la pluralité de séquences de bits comprend 12 séquences de bits.
 
7. Unité d'exécution (2) selon la revendication 6 lorsqu'elle est dépendante de la revendication 3, dans laquelle l'ensemble de circuits de normalisation (42) est configuré pour soustraire 186 au résultat.
 
8. Unité d'exécution (2) selon l'une quelconque des revendications 3, 4, 5 ou 7, dans laquelle l'ensemble de circuits de normalisation (42) est configuré pour diviser par un nombre qui est le nombre de valeurs possibles de variables aléatoires uniformément distribuées ayant la longueur en bits prédéterminée.
 
9. Unité d'exécution (2) selon l'une quelconque des revendications précédentes, dans laquelle la longueur en bits de chaque séquence est de 5.
 
10. Unité d'exécution (2) selon la revendication 8, dans laquelle l'ensemble de circuits de normalisation (42) est configuré pour diviser par 32.
 
11. Unité d'exécution (2) selon l'une quelconque des revendications précédentes, dans laquelle la distribution de probabilité prédéterminée se rapproche d'une distribution d'Irwin-Hall mise à l'échelle, compensée et quantifiée.
 
12. Unité d'exécution (2) selon l'une quelconque des revendications précédentes, comprenant un ensemble de circuits de sommation qui additionne ensemble des résultats d'une pluralité d'instructions de programme informatique, afin d'ajuster plus précisément la distribution de probabilité prédéterminée.
 
13. Unité d'exécution (2) selon l'une quelconque des revendications précédentes, laquelle est configurée pour combiner une ou plusieurs séquences de bits de la chaîne aléatoire de bits avec un ou plusieurs résultats normalisés.
 
14. Unité d'exécution selon l'une quelconque des revendications précédentes, comprenant une logique de conversion (44) pouvant fonctionner pour convertir un résultat de longueur 16 bits en un résultat de longueur 32 bits.
 
15. Procédé d'exécution d'une instruction de programme informatique pour générer des nombres aléatoires sur la base d'une distribution de probabilité prédéterminée, le procédé étant implémenté dans une unité d'exécution (2) d'un processeur et consistant à :

générer, lorsque l'instruction de programme informatique est exécutée par l'unité d'exécution (2), au moins une chaîne aléatoire de bits lors de l'exécution de l'instruction ;

sélectionner une pluralité de séquences de bits d'une longueur en bits prédéterminée à partir de la chaîne aléatoire de bits et les additionner afin de produire un résultat,

dans lequel la pluralité de séquences de bits sont des variables aléatoires uniformément distribuées.


 
16. Produit de programme informatique comprenant un programme informatique qui comprend une instruction de programme informatique enregistrée sur un support non transmissible qui, lorsqu'elle est exécutée, effectue un procédé de génération de nombres aléatoires sur la base d'une distribution de probabilité prédéterminée, le procédé implémenté dans une unité d'exécution (2) d'un processeur consistant à :

générer au moins une chaîne aléatoire de bits lors de l'exécution de l'instruction par l'unité d'exécution (2) ;

sélectionner une pluralité de séquences de bits d'une longueur en bits prédéterminée à partir de la chaîne aléatoire de bits et les additionner afin de produire un résultat,

dans lequel la pluralité de séquences de bits sont des variables aléatoires uniformément distribuées.


 




Drawing


























Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description