(19)
(11)EP 3 496 104 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
14.08.2019 Bulletin 2019/33

(43)Date of publication A2:
12.06.2019 Bulletin 2019/24

(21)Application number: 18204766.2

(22)Date of filing:  06.11.2018
(51)International Patent Classification (IPC): 
G11C 16/16(2006.01)
G11C 16/34(2006.01)
G11C 16/28(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 08.12.2017 US 201715836124

(71)Applicant: INTEL Corporation
Santa Clara, CA 95054 (US)

(72)Inventors:
  • FASTOW, Richard
    Cupertino, CA California 95014 (US)
  • SUN, Xin
    Fremont, CA California 94539 (US)
  • CHANDRASEKHAR, Uday
    Santa Clara, CA California 95051 (US)
  • PARAT, Krishna K.
    Palo Alto, CA California 94306 (US)
  • JARAMILLO, Camila
    San Jose, CA California 95134 (US)
  • SULE, Purval S.
    Folsom, CA California 95630 (US)
  • MADRASWALA, Aliasgar S.
    Folsom, CA California 95630 (US)

(74)Representative: Wright, Nicholas Matthew 
Maucher Jenkins 26 Caxton Street
London SW1H 0RJ
London SW1H 0RJ (GB)

  


(54)BLOCK BY DECK OPERATIONS FOR NAND MEMORY


(57) A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.







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