(19)
(11)EP 3 496 270 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.11.2020 Bulletin 2020/45

(21)Application number: 17205536.0

(22)Date of filing:  05.12.2017
(51)International Patent Classification (IPC): 
H03F 1/30(2006.01)
H03F 3/19(2006.01)

(54)

BIAS CIRCUIT

BIAS-STEUERUNG

CIRCUIT DE POLARISATION


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
12.06.2019 Bulletin 2019/24

(73)Proprietor: NXP B.V.
5656 AG Eindhoven (NL)

(72)Inventors:
  • van der Heijden, Mark Pieter
    Redhill, Surrey RH1 1QZ (GB)
  • De Jong, Gerben Willem
    Redhill, Surrey RH1 1QZ (GB)
  • Yang, Xin
    Redhill, Surrey RH1 1QZ (GB)

(74)Representative: Miles, John Richard 
NXP SEMICONDUCTORS Intellectual Property Group Abbey House 25 Clarendon Road
Redhill, Surrey RH1 1QZ
Redhill, Surrey RH1 1QZ (GB)


(56)References cited: : 
US-A1- 2009 108 939
US-B1- 7 023 281
US-A1- 2016 197 586
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD



    [0001] This disclosure relates to a bias circuit for an RF bipolar amplifier.

    BACKGROUND



    [0002] Bipolar Power amplifiers operating at very high frequencies for example mm-wave frequencies usually include bipolar transistors with very low breakdown voltages. To operate at Watt-level, power combining techniques are employed in combination with stacking transistors to increase the voltage-handling capability and to increase the load-line. In one example, a power amplifier may have a cascode configuration including a stack of a low-voltage common-emitter (CE) stage and a low- or high-voltage common-base (CB) stage. The common-emitter stage includes one or more bipolar transistors in a common-emitter configuration which may be referred to as common-emitter transistors. The common-base stage typically includes one or more transistors in a common-base configuration which may also be referred to as common-base transistors. Alternatively, a power amplifier may have a common-emitter stage which includes one or more bipolar transistors in a common-emitter configuration which may be referred to as common-emitter transistors

    [0003] US patent US 7 023 281 B1 discloses different bias structures for cascode amplifiers. US patent application US2016/197586 A1 discloses a cascode amplifier with peak detection for breakdown protection.

    SUMMARY



    [0004] Various aspects of the disclosure are defined in the accompanying claims. In a first aspect, there is provided a bias circuit for an RF bipolar amplifier according to claim 1.

    [0005] In one or more embodiments, the bias circuit may further comprise a first bias resistor arranged between the third bias transistor base and the second bias circuit terminal.

    [0006] In one or more embodiments, the buffer amplifier may further comprise a current sourcing transistor having a base coupled to the buffer amplifier input and an emitter coupled to the buffer amplifier output, a current sink arranged between the buffer amplifier output and common supply rail.

    [0007] In one or more embodiments, the buffer amplifier may further comprise a level shifter having a first terminal coupled to the current sourcing transistor collector and wherein the current sink comprises a current sinking transistor having a base coupled to a second terminal of the level shifter, a collector coupled to the first bias transistor base and an emitter coupled to the common supply rail.

    [0008] In one or more embodiments, the level shifter comprises a series arrangement of at least two diodes and a resistor coupled between current sourcing transistor collector and the common supply rail, and wherein the current sinking transistor base is coupled to a common node of one of the at least two diodes and the resistor.

    [0009] In one or more embodiments, the buffer amplifier may further comprise a current source element arranged between the bias supply voltage rail and the current sourcing transistor collector.

    [0010] In one or more embodiments, the current source element may comprise a resistor.

    [0011] In one or more embodiments, the buffer amplifier may further comprise a clamp transistor arranged in parallel with the current source element.

    [0012] In one or more embodiments, the buffer amplifier may further comprise a class AB amplifier.

    [0013] In one or more embodiments, the buffer amplifier may further comprise an output stage including a series arrangement of a current sourcing transistor and a current sinking transistor between the bias supply voltage rail and the common supply rail; a series arrangement of an input transistor and a level-shift diode between the bias supply voltage rail and the current sink transistor; wherein the first bias transistor base is coupled to the current sourcing transistor emitter and the current sinking transistor emitter, and the first bias transistor collector is coupled to the current sourcing transistor base and the input transistor base.

    [0014] Embodiments of the bias circuit may be included in a bipolar RF amplifier including an amplifier circuit coupled to the bias circuit.

    [0015] The amplifier circuit may comprise a cascode arrangement of a common base stage, and a common emitter stage; an input coupled to the common emitter stage; an output coupled to the common base stage.

    [0016] In the figures and description like reference numerals refer to like features. Embodiments of are now described in detail, by way of example only, illustrated by the accompanying drawings in which:

    Figure 1A shows an RF bipolar amplifier including a bias circuit according to an embodiment.

    Figure 1B shows a bias circuit for an RF bipolar amplifier according to an embodiment.

    Figure 2 illustrates a buffer amplifier for an RF bipolar amplifier bias circuit according to an embodiment.

    Figure 3 shows a buffer amplifier for an RF bipolar amplifier bias circuit according to an embodiment.

    Figure 4 illustrates a buffer amplifier for an RF bipolar amplifier bias circuit according to an embodiment.

    Figure 5 shows a buffer amplifier for an RF bipolar amplifier bias circuit according to an embodiment.

    Figure 6 shows a buffer amplifier for an RF bipolar amplifier bias circuit according to an embodiment.

    Figure 7 shows an RF bipolar amplifier including a bias circuit according to an embodiment.

    Figure 8 shows an RF bipolar amplifier including a bias circuit according to an embodiment.

    Figure 9 illustrates a buffer amplifier for an RF bipolar amplifier bias circuit according to an embodiment.

    Figure 10 shows an RF bipolar amplifier including a bias circuit according to an embodiment.


    DESCRIPTION



    [0017] Figure 1 shows an RF bipolar power amplifier 100 including a bias circuit 130 and an amplifier circuit 140 according to an embodiment. The transistors illustrated in figure 1 are NPN bipolar transistors. Other examples may use PNP transistors or a mix of PNP and NPN bipolar transistors.

    [0018] The bias circuit 130 may include a bias current source 102, a buffer amplifier 110, a first bias transistor QB1, a second bias transistor QB2, a third bias transistor QB3. The bias circuit 130 may include a first bias capacitor CB1, a second bias capacitor CB2. The bias circuit 130 may include a first bias circuit resistor RB1, a second bias circuit resistor RB2 and a third bias circuit resistor RB3.

    [0019] The bias current source 102 may be connected between a bias supply voltage rail 106 and the collector of a first bias transistor QB1. The buffer amplifier 110 may have a buffer amplifier input 108 connected to the collector of the first bias transistor QB1. The buffer amplifier 110 may have a buffer amplifier output 112 connected to the base of the first bias transistor QB1. The buffer amplifier output 112 may be connected to the base of a second bias transistor QB2. The buffer amplifier output 112 may be connected to a first bias circuit terminal or node 114.

    [0020] The first bias resistor RB1 may have a first terminal connected to a second bias circuit terminal or node 116. The first bias resistor RB1 may have a second terminal connected to the base of a third bias transistor QB3.

    [0021] The second bias transistor QB2 may have a collector connected to the bias supply voltage rail 106 and an emitter connected to a first terminal of second bias resistor RB2. A second terminal of the second bias resistor RB2 may be connected to a second bias circuit terminal or node 116. A first terminal of third bias resistor RB3 may be connected to the second bias circuit terminal 116. A second terminal of the third bias resistor RB3 may be connected to a common supply rail 104 which may be a ground.

    [0022] The first bias capacitor CB1 may be connected between the base of the first bias transistor QB1 and the base of the third bias transistor QB3. The collector of the third bias transistor QB3 may be connected to the emitter of first bias transistor QB1. The second bias capacitor CB2 may be connected between the collector of the first bias transistor QB1 and the common supply rail 104.

    [0023] The amplifier circuit 140 may include a common-emitter (CE) transistor Q0, a common-base (CB) transistor Q1, an input AC coupling capacitor C1, an AC-coupling capacitor C2, an output AC coupling capacitor C3, first impedance element Z1, a second impedance element Z2, and an inductance L1. The ac-coupling capacitors C1, C2, C3 may also be referred to as DC-blocking capacitors.

    [0024] The first impedance element Z1 may be connected between the second bias output terminal 116 and the base of the CE transistor Q0. Input AC coupling capacitor C1 may be connected between the base of the CE transistor Q0 and the RF amplifier input 126. The emitter of CE transistor Q0 may be connected to the common supply rail 104. The collector of CE transistor Q0 may be connected to the emitter of the CB transistor Q1.

    [0025] The second impedance element Z2 may be connected between the first bias output terminal 114 and the base of the CB transistor Q1. AC coupling capacitor C2 may be connected between the base of the CB transistor Q1 and common supply rail 104. The inductance L1 may be connected between an amplifier supply rail 118 and the collector of common base transistor Q1. The amplifier supply rail 118 may supply a voltage Vcc. The output capacitor C3 may be connected between a collector of common base transistor Q1 and the RF amplifier output 124. First impedance element Z1 and second impedance element Z2 are connecting impedance elements with inductive and/or resistive elements and may have complex impedance values of Z1(=R1+jX1) and Z2(=R2+jX2) where R1 and R2 are the values of the DC resistance and X1 and X2 are the reactance values of the respective impedance element.

    [0026] The amplifier circuit 140 has a cascode configuration of a low-breakdown-voltage common-emitter transistor Q0 and a low or high break-down voltage common-base transistor Q1. A low voltage may for example be a voltage in the range of 1 to 2.5 volts and a high voltage may for example be a voltage in the range of 2.5 and 5 volts or greater than 5 volts. The common-base transistor Q1 may be operated typically at 3.5 volts. In other examples, the amplifier circuit 140 may have multiple stages of common-emitter transistors and/or common-base transistors dependent on the required power output. Input capacitor C1 is used to feed the RF signal to the base of Q0. The AC decoupling capacitor C2 may be used to ground the base of Q1 at RF to mm Wave frequencies which may be in the range of 100 MHz to greater than 300 GHz. The inductance L1 and output capacitor C3 may provide the required impedance matching for an output load connected to the RF amplifier output 124.

    [0027] In operation, the bias supply rail 106 may supply a bias voltage VCC,Bias. The bias current source 102 which may be for example a resistor coupled to the bias supply rail 106 determines the value of the reference current Iref. First bias transistor QB1, second bias transistor QB2, third bias transistor QB3, second bias resistor RB2, and third bias resistor RB3 form a self-biased cascode bias network to bias common-base transistor Q1 of the cascode of the amplifier circuit 140. The collector current of first bias transistor QB1 may provide the base current for both the first bias transistor QB1 and the third bias transistor QB3. Consequently, by using a cascode arrangement of first bias transistor QB1 and third bias transistor QB3 in the bias circuit, the power consumption of the RF power amplifier 100 may be reduced. In some examples, the bias supply rail 106 and the amplifier supply rail 118 may be connected to the same voltage source so that VCC,Bias is equal to VCC. In other examples, the supply voltages may be different.

    [0028] The transistor QB3, first bias resistor RB1, and first impedance element Z1, forms a current mirror together with common-emitter transistor Q0. The resistor RB1 may be chosen to have a fixed ratio N with respect to the resistance value R1 of the first impedance element Z1. The value of current copied by the current mirror from QB3 to Q0 is Iref*N, where Iref is the reference current from the current source 102.

    [0029] The first bias capacitor CB1 may improve circuit stability by pole splitting of the bias circuit. The second bias capacitor CB2 may help stabilize the circuit operation, by storing excess charge so that Iref remains constant. Capacitor CB2 may also filter noise from the incoming reference current Iref. In some examples, CB2 may be omitted. It will be understood that, in other examples, the capacitors may be positioned at different nodes in the circuit than illustrated in RF amplifier 100 to stabilize the circuit operation.

    [0030] The buffer amplifier 110 may include a level shifter 122 and a unity voltage-gain buffer 120. The buffer amplifier 110 may provide additional current sourcing Isrc, and current sinking Isnk for the base current supplied to or generated from CB transistor Q1. The buffer amplifier 110 may be considered as a beta helper for CB transistor Q1, first bias transistor QB1 and second bias transistor QB2.

    [0031] During operation of the RF amplifier 100, in order to maximize the available voltage headroom of the cascode configuration of transistors Q0 and Q1, the collector-emitter voltage (Vce) of the CB transistor Q1 may be operated beyond the collector breakdown voltage with open base (BVCEO). This means that Q1 may be biased at, or just above BVCEO under nominal power amplifier operating conditions and under extreme loading conditions.

    [0032] When CB transistor Q1 is biased beyond BVCEO, the avalanche current Iavl, illustrated as current source 128, that flows from the collector to the base of CB transistor Q1 is equal or bigger than the forward base current of CB transistor Q1. Consequently, the net base current of CB transistor Q1 reverses sign and flows back into the cascode bias circuit 130. This increase in base current increases the base voltage of CB transistor Q1. The emitter of CB transistor Q1 follows the increase in base voltage. As the base of the second bias transistor QB2 is coupled to the base of the CB transistor Q1, the emitter of the second bias transistor QB2 also follows the increase in base voltage of the CB transistor Q1. Consequently, via the second bias resistor RB2 and the first impedance element Z1, the base-emitter voltage of CE transistor Q0 increases and hence the collector current Ic in the cascode increases. This increase in collector current results in further avalanche multiplication, leading eventually to failure of the device.

    [0033] The inventors of the present disclosure have appreciated that by including the buffer amplifier 110 in the bias circuit with both current sourcing and current sinking capability, a low-impedance voltage output at the base of first bias transistor QB1 and the second bias transistor QB2 may be provided under all operating conditions. Furthermore, since any avalanche current generated by CB transistor Q1 may flow to the common supply rail 104 via the buffer amplifier 110, the risk of failure of the device may be reduced.

    [0034] Figure 1B shows a bias circuit 130' that may be used as an alternative to bias circuit 130 in figure 1A.

    [0035] The bias circuit 130' may include a bias current source 102', a buffer amplifier 110', a first bias transistor QB1', a second bias transistor QB2', a third bias transistor QB3'. The bias circuit 130' may include a first bias circuit resistor RB1', a second bias circuit resistor RB2' and a third bias circuit resistor RB3'.

    [0036] The bias current source 102' may be connected between a bias supply voltage rail 106' and the collector of a first bias transistor QB1'. A voltage reference 122 may be connected between a buffer amplifier input 108' and a common supply rail 104'. The buffer amplifier 110' may have a buffer amplifier output 112' connected to the base of the first bias transistor QB1'. The buffer amplifier output 112' may be connected to a first bias circuit terminal 114'.

    [0037] A first bias resistor RB1' may have a first terminal connected to the second bias circuit terminal 116'. The first bias resistor RB1' may have a second terminal connected to the base of a third bias transistor QB3'.

    [0038] The second bias transistor QB2' may have a collector connected to the bias supply voltage rail 106' and an emitter connected to a first terminal of second bias resistor RB2'. The second bias transistor QB2' may have a base connected to the collector of the first bias transistor QB1'. A second terminal of the second bias resistor RB2' may be connected to the second bias circuit terminal 116'. A first terminal of third bias resistor RB3' may be connected to the second bias circuit terminal 116'. A second terminal of the third bias resistor RB3' may be connected to a common supply rail 104' which may be a ground.

    [0039] In operation, the bias circuit 130' may be connected to a cascode amplifier circuit 140 illustrated in figure 1A. The bias supply rail 106 may supply a bias voltage VCC,Bias the bias current source 102' which may be for example a resistor coupled to the bias supply rail 106 determines the value of the reference current Iref. First bias transistor QB1', second bias transistor QB2', third bias transistor QB3', second bias resistor RB2', and third bias resistor RB3' form a self-biased cascode bias network to bias common-emitter transistor Q0' of the cascode of the amplifier circuit. The bias voltage at the base of common-base transistor QB1' and common-base transistor Q1 may be determined by the value of the voltage Vcasc of the voltage source 122 via the buffer amplifier 110'.

    [0040] The transistor QB3', first bias resistor RB1', and first impedance element Z1, forms a current mirror together with common-emitter transistor Q0. The resistor RB1' may be chosen to have a fixed ratio N with respect to the resistance value R1 of the first impedance element Z1. The value of current copied by the current mirror from QB3' to Q0' is Iref N, where Iref is the reference current from the current source 102'.

    [0041] The buffer amplifier 110' may include a level shifter 122' and a unity voltage-gain buffer 120'. The buffer amplifier 110' may provide additional current sourcing Isrc, and current sinking Isnk for the base current supplied to or generated from CB transistor Q1 in the cascode amplifier 140. The buffer amplifier 110 may be considered as a beta helper for CB transistor Q1.

    [0042] Figure 2 shows a buffer amplifier 200 for a bias circuit according to an embodiment. The buffer amplifier 200 may for example be used instead of buffer amplifier 110 in bias circuit 130. The transistors illustrated in figure 2 are NPN bipolar transistors. Other examples may use PNP transistors or a mix of PNP and NPN bipolar transistors.

    [0043] The buffer amplifier 200 includes a current sourcing transistor QB4 configured as an emitter-follower and a current sink 202. The current sourcing transistor QB4 may have a collector connected to the bias supply rail 106. The current sourcing transistor QB4 may have an emitter connected to the buffer amplifier output 112. The current sourcing transistor QB4 may have a base connected to the buffer amplifier input 108. The current sink 202 may have a first terminal connected to the emitter of the current source transistor QB4. The current sink 202 may have a second terminal connected to the emitter of the current source transistor QB4.

    [0044] In operation, the current sourcing transistor QB4 operates as class-AB voltage buffer which may act as a beta-helper to source base current to the CB transistor Q1. For avalanche current, the fixed current sink 202, which may be a resistor, may sink avalanche current Iavl generated by the CB transistor Q1 via the second impedance element Z2. The current sink 202 is passive and therefore fixed to the maximum negative base current that is expected from CB transistor Q1 which may result in increased power dissipation.

    [0045] Figure 3 shows an example buffer amplifier 250 which may be used instead of buffer amplifier 110 in the bias circuit 130. The transistors illustrated in figure 3 are NPN bipolar transistors. Other examples may use PNP transistors or a mix of PNP and NPN bipolar transistors.

    [0046] The buffer amplifier 250 may include a current sourcing transistor QB5, a current sinking transistor QB6, a level shifter 254, and a current source 252 which may be for example a resistor. The current sourcing transistor QB5 may have a collector connected to a first terminal of the current source 252. A second terminal of the current source may be connected to the bias supply rail 106. The current sourcing transistor QB5 may have an emitter connected to the buffer amplifier output 112. The current sourcing transistor QB5 may have a base connected to the buffer amplifier input 108. A current sinking transistor QB6 may have a collector connected to the buffer amplifier output 112. The current sinking transistor QB6 may have an emitter connected to the common supply rail 104. A level shifter 254 may be connected between the collector of the current sourcing transistor QB5 and the base of the current sinking transistor QB6.

    [0047] In operation, the current source 252 may supply a current Isrc. If avalanche current Iavl is generated by CB transistor Q1, this may flow into the bias network (not shown) and buffer amplifier 250 from CB transistor Q1 and into the buffer amplifier 250 via buffer amplifier output 112. The avalanche current Iavl may decrease the collector current in current sourcing transistor QB5 by an amount Isrc - Iavl. The decrease in collector current results in an increase of the collector voltage of current sourcing transistor QB5. Via level shift 254, the base-emitter voltage of current sinking transistor QB6 increases and sinks the net base current of CB transistor Q1 to the common supply rail 104 which may be a ground. By sinking the net base current, the base bias voltage of CB transistor Q1 may be stabilized. The forward base-current of common base transistor Q1 is now limited by current Isrc from the current source 252. However, this is usually a much lower current than that is required in the avalanche protection mode.

    [0048] Figure 4 shows an example buffer amplifier 300 which may be used instead of buffer amplifier 110 in the bias circuit 130. The transistors illustrated in figure 4 are NPN bipolar transistors. Other examples may use PNP transistors or a mix of PNP and NPN bipolar transistors.

    [0049] The buffer amplifier 300 may include a current sourcing transistor QB7, a current sinking transistor QB8, a level shifter 302, and a current source resistor RB4. The current sourcing transistor QB7 may have a collector connected to a first terminal of the current source resistor RB4. A second terminal of the current source resistor RB4 may be connected to the bias supply rail 106. The current sourcing transistor QB7 may have an emitter connected to the buffer amplifier output 112. The current sourcing transistor QB7 may have a base connected to the buffer amplifier input 108. The current sinking transistor QB8 may have a collector connected to the buffer amplifier output 112. The current sinking transistor QB8 may have an emitter connected to the common supply rail 104.The level shifter 302 may include a series arrangement of diode D1, diode D2 and level shifter resistor RB5 connected between the collector of the current sourcing transistor QB7 and the common supply rail 104. The common node between diode D2 and the level shifter resistor RB5 may be connected to the base of the current sinking transistor QB8.

    [0050] In operation, the bias supply rail may supply a voltage denoted VCC, Bias. The current source resistor RB4 may supply a current Isrc. If avalanche current Iavl is generated by CB transistor Q1, this may flow into the bias network (not shown) from CB transistor Q1 and into the buffer amplifier 300 via buffer amplifier output 112. The avalanche current Iavl may decrease the collector current in current sourcing transistor QB7 by an amount Isrc - Iavl. The decrease in collector current results in an increase of the collector voltage of current sourcing transistor QB7. Via level shift 302, the base-emitter voltage of current sinking transistor QB8 increases and sinks the net base current of CB transistor Q1 to the common supply rail 104 which may be ground. By sinking the net base current, the base bias voltage of CB transistor Q1 may be stabilized. The forward base-current of common base transistor Q1 is now limited by current Isrc from the current source resistor RB4. However, this is usually a much lower current than that is required in the avalanche protection mode.

    [0051] Figure 5 shows an example buffer amplifier 350 which may be used instead of buffer amplifier 110 in the bias circuit 130. The transistors illustrated in figure 4 are NPN bipolar transistors. Other examples may use PNP transistors or a mix of PNP and NPN bipolar transistors.

    [0052] The buffer amplifier 350 may include a current sourcing transistor QB9, a current sinking transistor QB10, a level shifter 352, a current source resistor RB6, A clamp transistor QB11, and a voltage reference 354. The current sourcing transistor QB9 may have a collector connected to a first terminal of the current source resistor RB6. A second terminal of the current source resistor RB6 may be connected to the bias supply rail 106. The current sourcing transistor QB9 may have an emitter connected to the buffer amplifier output 112. The current sourcing transistor QB9 may have a base connected to the buffer amplifier input 108. The current sinking transistor QB10 may have a collector connected to the buffer amplifier output 112. The current sinking transistor QB10 may have an emitter connected to the common supply rail 104. The level shifter 352 may include a series arrangement of diode D3, diode D4 and level shifter resistor RB7 connected between the collector of the current sourcing transistor QB9 and the common supply rail 104. The common node between diode D4 and the level shifter resistor RB7 may be connected to the base of the current sinking transistor QB10.

    [0053] In operation, the bias supply rail may supply a voltage denoted VCC, Bias. The current source resistor RB6 may supply a current Isrc. If avalanche current Iavl is generated by CB transistor Q1, this may flow into the bias network (not shown) from CB transistor Q1 and into the buffer amplifier 350 via buffer amplifier output 112. The avalanche current Iavl may decrease the collector current in current sourcing transistor QB9 by an amount Isrc - Iavl. The decrease in collector current results in an increase of the collector voltage of current sourcing transistor QB9. Via level shift 352, the base-emitter voltage of current sinking transistor QB10 increases and sinks the net base current of common-base transistor Q1 to the common supply rail 104 which may be ground. By sinking the net base current, the base bias voltage of CB transistor Q1 may be stabilized. The clamp transistor QB11 across the current source resistor may protect current source QB9 from saturation under extreme operating conditions. Extreme operating conditions may be caused for example by a high voltage standing wave ratio (VSWR) condition on an antenna connected to the RF amplifier output. This VSWR condition may cause a load mismatch for the CB transistor Q1 resulting in a large increase in base current. The voltage reference 354 may have a reference voltage of 4-diode drop voltages or slightly higher so that the base emitter junction of clamp transistor QB11 is always forward biased. The voltage clamp formed by clamp transistor QB11 and voltage reference 354 may limit the voltage drop across current source resistor RB6 and prevent the current sourcing transistor QB9 going into saturation when forward current exceeding the quiescent current of the current sourcing transistor QB9 is required to be sourced to the base of the common-base transistor Q1. Preventing the current sourcing transistor QB9 going into saturation in this way may result in less variation in the bias voltage supplied due to differences in processing of the transistor during manufacturing, supply voltage differences and temperature variations. In buffer amplifier 350, the forward base-current required by common base transistor Q1 is no longer limited by current Isrc from the current source resistor RB6. In some examples, the single current sourcing transistor QB9 may be replaced by a Darlington pair configuration of two transistors which effectively acts as a single transistor with a higher current gain or beta value.

    [0054] Figure 6 shows an example buffer amplifier 400 which may be used instead of buffer amplifier 110 in the bias circuit 130. The buffer amplifier 400 may include a complementary class-AB output stage including current sourcing transistor QB14 and a current sinking transistor QB12. The buffer amplifier 400 may further include an input transistor QB13, level-shift diode D5 and current source 402. The current sourcing transistor QB14 and input transistor QB13 are NPN bipolar transistors. The current sinking transistor QB12 is a PNP transistor.

    [0055] The current sourcing transistor QB14 may have a collector connected to the bias supply rail 106. The current sourcing transistor QB14 may have an emitter connected to the buffer amplifier output 112. The current sourcing transistor QB14 may have a base connected to the buffer amplifier input 108. The collector of the input transistor QB13 may be connected to the bias supply rail 106. The base of the input transistor QB13 may be connected to the buffer amplifier input 108.

    [0056] The current sinking transistor QB12 may have an emitter connected to the buffer amplifier output 112. A series arrangement of level-shift diode D5 and current source 402 may be connected between the emitter of the input transistor QB13 and the common supply rail 104. The common node between level-shift diode D5 and the current source 402 may be connected to the base of the current sinking transistor QB12.

    [0057] In operation, the bias supply rail may supply a voltage denoted VCC,Bias. The source current is supplied to the buffer output 112 by the current sourcing transistor QB14 and so supplies base current to CB transistor Q1. If avalanche current Iavl is generated by CB transistor Q1, this may flow into the bias network (not shown) from CB transistor Q1 and into the buffer amplifier 400 via buffer amplifier output 112. The current sinking transistor QB12 acts as a complementary beta-helper for CB transistor Q1 and acts as a current sink for the generated avalanche current from CB transistor Q1. The base of the current sinking transistor QB12 is controlled by the input transistor QB13 and the level-shift diode D5. In some examples, the level-shift diode D5 may be implemented using a transistor with a base connected to the collector. In this case, the quiescent current of the buffer amplifier may be determined by the current source 402 which may be a resistor and the emitter-area ratios QB14/QB13 and QB12/D5. In buffer amplifier 400, the current limits of sourcing and sinking is not fixed by any current source.

    [0058] Figure 7 shows an RF bipolar amplifier 500 according to an embodiment. RF amplifier includes a bias circuit 530 and an RF cascode amplifier circuit 540.

    [0059] The bias circuit 530 includes a cascode bias network 520, a buffer amplifier 510 and a current source 502. The current source 502 may have a connection 504 to the cascode bias network 520. The current source 502 may have a connection 504 to the buffer amplifier input 512. The buffer amplifier output 514 may be connected to a first bias terminal 506. The cascode bias network 520 may be connected to the first bias terminal 506 and a second bias terminal 508.

    [0060] The RF amplifier circuit 540 may include a common-emitter stage 528 including one or more bipolar transistors in a common-emitter configuration. The RF amplifier circuit 540 may include a common-base stage 526 including one or more bipolar transistors in a common-base configuration. The common-base stage 526 may be connected to the RF amplifier output 524. The common-emitter stage 528 may be connected to the RF amplifier input 522. The common-emitter stage 528 may be connected via connection 532 to the common-base stage 526. The common-base stage 526 and the common-emitter stage 528 may be arranged in a cascode configuration.

    [0061] The first bias terminal 506 may be connected to one or more of the bases of the transistors in the common-base stage 526. The second bias terminal 508 may be connected to one or more of the bases of the transistors in the common-emitter stage 528.

    [0062] In operation, the cascode bias network 520 may supply the base current for the transistors in the common-base stage 526 via first bias terminal 506. The cascode bias network 520 may supply the base current for the transistors in the common-emitter stage 528 via second bias terminal 508. The buffer amplifier 510 may provide additional base current to the common-base stage 526. The buffer amplifier 510 may sink avalanche current generated from the common-base stage 526. The buffer amplifier 510 may source and sink base currents to and from the common-base stage 526 in the presence of avalanche currents under nominal and extreme loading conditions. Consequently, the buffer amplifier 510 may stabilize the bias supply to the RF amplifier circuit 540 and prevent the cascode arrangement of the common-base stage 526 and the common-emitter stage 528 from breakdown.

    [0063] It will be appreciated that the buffer amplifier 510 may be implemented by any of the buffer amplifiers 200, 250, 300, 350, 400.

    [0064] Figure 8 shows an RF bipolar power amplifier 600 including a bias circuit 630 and an amplifier circuit 640 according to an embodiment. The transistors illustrated in figure 8 are NPN bipolar transistors. Other examples may use PNP transistors or a mix of PNP and NPN bipolar transistors. It will be appreciated that the transistors may be formed on different semiconductor substrates such as Silicon, GaAs, GaN and other suitable materials

    [0065] The bias circuit 630 may include a bias current source 602, a buffer amplifier 610, and a bias network 620. The bias network 620 may include a bias transistor QB15, a first bias capacitor CB3, a second bias capacitor CB4, a first bias resistor RB8, and a second bias resistor RB9.

    [0066] The bias current source 608 may be connected between a bias supply voltage rail 606 and the collector of a first bias transistor QB15. The buffer amplifier 610 may have a buffer amplifier input 608 connected to the collector of the first bias transistor QB15. The buffer amplifier 610 may have a buffer amplifier output 612 connected to bias circuit terminal 616.

    [0067] The first bias resistor RB8 may have a first terminal connected to the bias circuit terminal 616. The first bias resistor RB8 may have a second terminal connected to the base of the bias transistor QB15. The second bias resistor RB9 may have a first terminal connected to the collector of the bias transistor QB15. The second bias resistor RB8 may have a second terminal connected to the buffer amplifier input 608.

    [0068] The first bias capacitor CB3 may have a first terminal connected to the base of the bias transistor QB15 and a second terminal connected to the collector of the bias transistor QB15. The second bias capacitor CB4 may have a first terminal connected to the base of the bias transistor QB15 and a second terminal connected to the emitter of the bias transistor QB15. The emitter of the bias transistor QB15 may be connected to a common supply rail 604 which may be a ground. In some examples, the second bias resistor RB9 may be omitted. In some examples, if the base-emitter capacitance of bias transistor is sufficient, the second bias capacitor CB4 may be omitted. In some examples, the first bias resistor RB8 may be omitted. In some examples, if the base-collector capacitance of bias transistor is sufficient, the first bias capacitor CB4 may be omitted.

    [0069] The amplifier circuit 640 may include a common-emitter (CE) transistor Q0', an input AC coupling capacitor C1', and an impedance element Z1'.

    [0070] The impedance element Z1' may be connected between the bias output terminal 616 and the base of the CE transistor Q0'. Input AC coupling capacitor C1' may be connected between the base of the CE transistor Q0' and the RF amplifier input 618. The emitter of CE transistor Q0' may be connected to the common supply rail 604. The collector of CE transistor Q0' may be connected to the RF amplifier output 622.

    [0071] The amplifier circuit 640 may have a low or high break-down voltage common-emitter transistor Q0'. A low voltage may for example be a voltage in the range of 1 to 2.5 volts and a high voltage may for example be a voltage in the range of 2.5 and 5 volts or greater than 5 volts. In other examples, the amplifier circuit 640 may have multiple stages of common-emitter transistors dependent on the required power output. Input capacitor C1' is used to feed the RF signal to the base of Q0'.

    [0072] In operation, the bias supply rail 606 may supply a bias voltage VCC,Bias. The bias current source 608 which may be for example a resistor coupled to the bias supply rail 606 determines the value of the reference current Iref.

    [0073] The transistor QB15, first bias resistor RB8, and first impedance element Z1', forms a current mirror together with common-emitter transistor Q0'. The resistor RB8 may be chosen to have a fixed ratio N with respect to the resistance value R1' of the first impedance element Z1'. The value of current copied by the current mirror from QB3 to Q0 is Iref N, where Iref is the reference current from the current source 608.

    [0074] The first bias capacitor CB3 and CB4 may improve circuit stability of the bias circuit 630. In some examples, the capacitors CB3 and CB4 may be omitted. It will be understood that, in other examples, the capacitors may be positioned at different nodes in the circuit than illustrated in RF amplifier 600 to stabilize the circuit operation.

    [0075] The buffer amplifier 610 may provide additional current sourcing Isrc, and current sinking Isnk for the base current supplied to or generated from common emitter transistor Q0'. The buffer amplifier 610 may be considered as a beta helper for common-emitter transistor Q0'.

    [0076] The inventors of the present disclosure have appreciated that by including the buffer amplifier 610 with both current sourcing and current sinking capability in the bias circuit 630, a low-impedance voltage output at the base of first bias transistor QB15 may be provided under all operating conditions. Furthermore, since any avalanche current generated by CE transistor Q0' may flow to the common supply rail 604 via the buffer amplifier 610, the risk of failure of the device may be reduced.

    [0077] Figure 9 shows an example buffer amplifier 650 which may be used instead of buffer amplifier 610 in the bias circuit 630. The transistors illustrated in figure 9 are NPN bipolar transistors. Other examples may use PNP transistors or a mix of PNP and NPN bipolar transistors.

    [0078] The buffer amplifier 650 may include a current sourcing transistor QB17, a current sinking transistor QB18, a level shifter 652, an input transistor QB16 and a current source resistor RB10.

    [0079] The input transistor QB16 may have a collector connected to a first terminal of the current source resistor RB10. A second terminal of the current source resistor RB10 may be connected to the bias supply rail 606. The input transistor QB16 may have an emitter connected to the buffer amplifier output 612. The input transistor QB17 may have a base connected to the buffer amplifier input 608.

    [0080] The current sourcing transistor QB17 may have a collector connected to the bias supply rail 606. The current sourcing transistor QB17 may have an emitter connected to the buffer amplifier output 612. The current sourcing transistor QB17 may have a base connected to the buffer amplifier input 608.

    [0081] The current sinking transistor QB18 may have a collector connected to the buffer amplifier output 612. The current sinking transistor QB18 may have an emitter connected to the common supply rail 604.

    [0082] The level shifter 652 may include a series arrangement of diode D6, diode D7 and level shifter resistor RB11 connected between the collector of the input transistor QB17 and the common supply rail 604. The common node between diode D7 and the level shifter resistor RB11 may be connected to the base of the current sinking transistor QB18.

    [0083] In operation, the bias supply rail may supply a voltage denoted VCC,Bias. The current source resistor RB10 may supply a current Isrc. If avalanche current Iavl illustrated as current source 628 is generated by CE transistor Q0', this may flow into the bias network from CE transistor Q0' and impedance element Z1' into the buffer amplifier 650 via buffer amplifier output 612. The avalanche current Iavl may decrease the collector current in input transistor QB16 by an amount Isrc - Iavl. The decrease in collector current results in an increase of the collector voltage of input transistor QB16. Via level shift 652, the base-emitter voltage of current sinking transistor QB18 may increases and sinks the net base current of CE transistor Q0' to the common supply rail 604 which may be ground. By sinking the net base current, the base bias voltage of CE transistor Q0' may be stabilized.

    [0084] The forward base-current of common emitter transistor Q0' may be provided by input transistor QB16 and current sourcing transistor QB17. The forward base current provided may by higher than Isrc since current sourcing transistor QB17 is not limited by the current source resistor RB10.

    [0085] In other examples, it will be appreciated that any of the buffer amplifiers 200,250,300, 350 may be used to replace buffer amplifier 610 in the RF amplifier 600.

    [0086] Figure 10 shows an RF bipolar amplifier 700 according to an embodiment. RF amplifier includes a bias circuit 730 and an RF cascode amplifier circuit 740.

    [0087] The bias circuit 730 includes a cascode bias network 720, a buffer amplifier 710 and a current source 702. The current source 702 may have a connection 704 to the cascode bias network 720. The current source 702 may have a connection 704 to the buffer amplifier input 708. The buffer amplifier output 712 may be connected to a first bias terminal 706. The bias network 720 may be connected to the first bias terminal 706

    [0088] The RF amplifier circuit 740 may include a common-emitter stage 726 including one or more bipolar transistors in a common-emitter configuration. The common-emitter stage 726 may be connected to the RF amplifier output 724. The common-emitter stage 726 may be connected to the RF amplifier input 722.

    [0089] The first bias terminal 706 may be connected to one or more of the bases of the transistors in the common-emitter stage 726.

    [0090] In operation, the bias network 720 may supply the base current for the transistors in the common-emitter stage 726 via first bias terminal 706. The buffer amplifier 710 may provide additional base current to the common-emitter stage 726. The buffer amplifier 710 may sink avalanche current generated from the common-emitter stage 726. The buffer amplifier 710 may source and sink base currents to and from the common-emitter stage 726 in the presence of avalanche currents under nominal and extreme loading conditions. Consequently, the buffer amplifier 710 may stabilize the bias supply to the RF amplifier circuit 740 and prevent the common-emitter stage 726 from breakdown.

    [0091] It will be appreciated that the buffer amplifier 710 may be implemented by any of the buffer amplifiers 200, 250, 300, 350, 400, 650.

    [0092] The embodiments herein describe a bias circuit including a buffer amplifier which may act as a beta-helper circuit for a common-base transistor in the cascode of an RF amplifier. The buffer amplifier may allow additional base current sourcing when required by the common-base stage. The buffer amplifier may allow more efficient avalanche current sinking. By improving the avalanche current sinking the possibility of damage occurring to the RF power amplifier during operation due to, for example, a mismatched load impedance based on VSWR requirements, may be reduced. Furthermore, the bias circuit may include a cascode configuration to supply bias currents to a common-base stage and a common-emitter stage.

    [0093] Embodiments herein further describe a bias circuit including a buffer amplifier which may act as a beta-helper circuit for a common-emitter stage of a common-emitter RF amplifier. The buffer amplifier may allow additional base current sourcing when required by the common-emitter stage. The buffer amplifier may allow more efficient avalanche current sinking. By improving the avalanche current sinking the possibility of damage occurring to the RF power amplifier during operation due to, for example, a mismatched load impedance based on VSWR requirements, may be reduced.

    [0094] The term current sourcing transistor as used herein refers to a transistor where current is flowing out of the device. A current sourcing transistor may provide current to the base of the transistors in the amplifier circuits. The term current sinking transistor as used herein refers to a transistor where current is flowing into the device. A current sinking transistor may sink current from the base of the transistors in the amplifier circuits.

    [0095] A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier circuit. The buffer provides additional base current to the amplifier circuit of the bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.

    [0096] Embodiments of the bias circuit described may be included in any amplifier using bipolar transistors. The bias circuit may for example be used for amplifiers required to amplify signals to high-power levels for the transmission of radio signals. High power levels may be in a range from 10mWatts to several Watts of power. For example, the bias circuit may be included in power amplifiers for wireless applications, such as for example 5G mmWave products or cellular mobile products.

    [0097] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

    [0098] The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

    [0099] For the sake of completeness it is also stated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single processor or other unit may fulfil the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.


    Claims

    1. A bias circuit (130) for an RF bipolar amplifier (140), the bias circuit comprising:

    a first bias circuit terminal (114) configured to be coupled to a base of a common-base transistor (Q1) of the RF bipolar amplifier (140);

    a second bias circuit terminal (116) configured to be coupled to a base of a common-emitter transistor (Q0) of the RF bipolar amplifier (140) ;

    a current source (102) coupled between a bias supply voltage rail (106) and a collector of a first bias transistor (QB1);

    a bias network coupled to the current source (102), the first bias circuit terminal (114), and

    the second bias circuit terminal (116) ; and

    a buffer amplifier (110) having an input (108) coupled to the collector of the first bias transistor (QB1) and an output (112) coupled to the first bias circuit terminal (114); wherein the buffer amplifier (110) is configured to at least partially source current provided to the first bias circuit terminal and to sink current from the first bias circuit terminal; and wherein the bias network is configured to provide a current to the first bias circuit terminal (114) and the second bias circuit terminal (116), and wherein the bias network comprises:

    the first bias transistor (QB1), a second bias transistor (QB2), a third bias transistor (QB3), a second bias resistor (RB2), and a third bias resistor (RB3), wherein the

    first bias transistor (QB1) and third bias transistor (QB3) are arranged in a cascode stack between the current source (102)and a common supply rail (104), the first bias transistor (QB1) having a base coupled to the first bias circuit terminal (114) and the third bias transistor (QB3) having a base coupled to the second bias circuit terminal (116); and

    the second bias transistor (QB2) having a base coupled to the first bias transistor base, a collector coupled to the bias supply voltage rail (106), and an emitter coupled to the common supply rail (104) through a series arrangement of the second bias resistor (RB2) and the third bias resistor (RB3), wherein the third bias transistor base is coupled to a common node between the second bias resistor (RB2) and the third bias resistor (RB3).


     
    2. The bias circuit of claim 1 further comprising a first bias resistor (RB1) arranged between the third bias transistor base and the second bias circuit terminal ((116).
     
    3. The bias circuit of any preceding claim wherein the buffer amplifier (200, 250, 300) comprises:

    a current sourcing transistor (QB4, QB5, QB7) having a base coupled to the buffer amplifier input and an emitter coupled to the buffer amplifier output,

    a current sink (202, QB6, QB8) arranged between the buffer amplifier output and common supply rail.


     
    4. The bias circuit of claim 3 wherein the buffer amplifier (250, 300) further comprises a level shifter (254, 302) having a first terminal coupled to the current sourcing transistor collector and wherein the current sink comprises a current sinking transistor (QB8) having a base coupled to a second terminal of the level shifter, a collector coupled to the first bias transistor base and an emitter coupled to the common supply rail.
     
    5. The bias circuit of claim 4 wherein the level shifter (302) comprises a series arrangement of at least two diodes (D1,D2) and a resistor (R5) coupled between current sourcing transistor collector and the common supply rail, and wherein the current sinking transistor base is coupled to a common node of one of the at least two diodes and the resistor.
     
    6. The bias circuit of any of claims 4 or 5 wherein the buffer amplifier (350) further comprises a current source element (RB6) arranged between the bias supply voltage rail (106) and the current sourcing transistor collector.
     
    7. The bias circuit of claim 6 wherein the current source element comprises a resistor (RB6).
     
    8. The bias circuit of claim 6 or 7, wherein the buffer amplifier (350) further comprises a clamp transistor (QB11) arranged in parallel with the current source element.
     
    9. The bias circuit of any preceding claim wherein the buffer amplifier comprises a class AB amplifier.
     
    10. The bias circuit of any preceding claim wherein the buffer amplifier comprises:

    an output stage including a series arrangement of a current sourcing transistor (QB12) and a current sinking transistor (QB12) between the bias supply voltage rail and the common supply rail;

    a series arrangement of an input transistor (QB13) and a level-shift diode (D5) between the bias supply voltage rail and the current sink transistor;

    wherein the first bias transistor base is coupled to the current sourcing transistor emitter and the current sinking transistor emitter, and the first bias transistor collector is coupled to the current sourcing transistor base and the input transistor base.


     
    11. A bipolar RF amplifier (100) comprising the bias circuit (130) of any preceding claim coupled to an amplifier circuit (140).
     
    12. The bipolar RF amplifier of claim 11 wherein the amplifier circuit comprises:

    a cascode arrangement of a common base stage (Q1), and a common emitter stage (Q0);

    an input (126) coupled to the common emitter stage;

    an output (124) coupled to the common base stage.


     


    Ansprüche

    1. Vorspannungsschaltung (130) für einen HF-Bipolarverstärker (140), wobei die Vorspannungsschaltung Folgendes umfasst:

    einen ersten Vorspannungsschaltunganschluss (114), der konfiguriert ist, mit einer Basis eines Transistors mit gemeinsamer Basis (Q1) des HF-Bipolarverstärkers (140) gekoppelt zu sein;

    einen zweiten Vorspannungsschaltunganschluss (116), der konfiguriert ist, mit einer Basis eines Transistors mit gemeinsamem Emitter (Q0) des HF-Bipolarverstärkers (140) gekoppelt zu sein;

    eine Stromquelle (102), die zwischen einer Vorspannungsversorgungsspannungsschiene (106) und einem Kollektor eines ersten Vorspannungstransistors (QB1) gekoppelt ist;

    ein Vorspannungsnetz, das mit der Stromquelle (102), dem ersten Vorspannungsschaltunganschluss (114) und dem zweiten Vorspannungsschaltunganschluss (116) gekoppelt ist; und

    einen Pufferverstärker (110), der einen Eingang (108), der mit dem Kollektor des ersten Vorspannungstransistors (QB1) gekoppelt ist, und einen Ausgang (112), der mit dem ersten Vorspannungsschaltunganschluss (114) gekoppelt ist, aufweist; wobei der Pufferverstärker (110) konfiguriert ist, wenigstens teilweise eine Quelle für Strom, der für den ersten Vorspannungsschaltunganschluss bereitgestellt ist, und eine Senke für Strom aus dem ersten Vorspannungsschaltunganschluss zu sein; und wobei das Vorspannungsnetz konfiguriert ist, einen Strom für den ersten Vorspannungsschaltunganschluss (114) und den zweiten Vorspannungsschaltunganschluss (116) bereitzustellen, und wobei das Vorspannungsnetz Folgendes umfasst:

    den ersten Vorspannungstransistor (QB1), einen zweiten Vorspannungstransistor (QB2), einen dritten Vorspannungstransistor (QB3), einen zweiten Vorspannungswiderstand (RB2) und einen dritten Vorspannungswiderstand (RB3), wobei der erste Vorspannungstransistor (QB1) und der dritte Vorspannungstransistor (QB3) in einem Kaskoden-Stapel zwischen der Stromquelle (102) und einer gemeinsamen Versorgungsschiene (104) angeordnet sind, wobei der erste Vorspannungstransistor (QB1) eine Basis aufweist, die mit dem ersten Vorspannungsschaltunganschluss (114) gekoppelt ist, und der dritte Vorspannungstransistor (QB3) eine Basis aufweist, die mit dem zweiten Vorspannungsschaltunganschluss (116) gekoppelt ist; und

    der zweite Vorspannungstransistor (QB2) eine Basis, die mit der ersten Vorspannungstransistor-Basis gekoppelt ist, einen Kollektor, der mit der Vorspannungsversorgungsspannungsschiene (106) gekoppelt ist, und einen Emitter, der mit der gemeinsamen Versorgungsschiene (104) über eine Reihenanordnung aus dem zweiten Vorspannungswiderstand (RB2) und dem dritten Vorspannungswiderstand (RB3) gekoppelt ist, aufweist, wobei die dritte Vorspannungstransistor-Basis mit einem gemeinsamen Knoten zwischen dem zweiten Vorspannungswiderstand (RB2) und dem dritten Vorspannungswiderstand (RB3) gekoppelt ist.


     
    2. Vorspannungsschaltung nach Anspruch 1, die ferner einen ersten Vorspannungswiderstand (RB1) umfasst, der zwischen der dritten Vorspannungstransistor-Basis und dem zweiten Vorspannungsschaltunganschluss (116) angeordnet ist.
     
    3. Vorspannungsschaltung nach einem der vorhergehenden Ansprüche, wobei der Pufferverstärker (200, 250, 300) Folgendes umfasst:

    einen Stromquellentransistor (QB4, QB5, QB7), der eine Basis, die mit dem Pufferverstärkereingang gekoppelt ist, und einen Emitter, der mit dem Pufferverstärkerausgang gekoppelt ist, aufweist,

    eine Stromsenke (202, QB6, QB8), die zwischen dem Pufferverstärkerausgang und der gemeinsamen Stromschiene angeordnet ist.


     
    4. Vorspannungsschaltung nach Anspruch 3, wobei der Pufferverstärker (250, 300) ferner einen Pegelumsetzer (254, 302) umfasst, der einen ersten Anschluss aufweist, der mit dem Stromquellentransistor-Kollektor gekoppelt ist, und wobei die Stromsenke einen Stromsenkentransistor (QB8) umfasst, der eine Basis, die mit einem zweiten Anschluss des Pegelumsetzers gekoppelt ist, einen Kollektor, der mit der ersten Vorspannungstransistor-Basis gekoppelt ist, und einen Emitter, der mit der gemeinsamen Stromschiene gekoppelt ist, aufweist.
     
    5. Vorspannungsschaltung nach Anspruch 4, wobei der Pegelumsetzer (302) eine Reihenanordnung aus wenigstens zwei Dioden (D1, D2) und einem Widerstand (R5) umfasst, die zwischen dem Stromquellentransistor-Kollektor und der gemeinsamen Stromschiene gekoppelt ist, und wobei die Stromsenkentransistor-Basis mit einem gemeinsamen Knoten einer aus den wenigstens zwei Dioden und des Widerstands gekoppelt ist.
     
    6. Vorspannungsschaltung nach einem der Ansprüche 4 oder 5, wobei der Pufferverstärker (350) ferner ein Stromquellenelement (RB6) umfasst, das zwischen der Vorspannungsversorgungsspannungsschiene (106) und dem Stromquellentransistor-Kollektor angeordnet ist.
     
    7. Vorspannungsschaltung nach Anspruch 6, wobei das Stromquellenelement einen Widerstand (RB6) umfasst.
     
    8. Vorspannungsschaltung nach Anspruch 6 oder 7, wobei der Pufferverstärker (350) ferner einen Klemmen-Transistor (QB11) umfasst, der parallel zu dem Stromquellenelement angeordnet ist.
     
    9. Vorspannungsschaltung nach einem der vorhergehenden Ansprüche, wobei der Pufferverstärker einen Klasse-AB-Verstärker umfasst.
     
    10. Vorspannungsschaltung nach einem der vorhergehenden Ansprüche, wobei der Pufferverstärker Folgendes umfasst:

    eine Ausgangsstufe, die eine Reihenanordnung aus einem Stromquellentransistor (QB12) und einem Stromsenkentransistor (QB12) zwischen der Vorspannungsversorgungsspannungsschiene und der gemeinsamen Versorgungsschiene enthält,

    eine Reihenanordnung aus einem Eingangstransistor (QB13) und einer Pegelumsetzungsdiode (D5) zwischen der Vorspannungsversorgungsspannungsschiene und dem Stromsenkentransistor;

    wobei die erste Vorspannungstransistor-Basis mit dem Stromquellentransistor-Emitter und dem Stromsenkentransistor-Emitter gekoppelt ist und der erste Vorspannungstransistor-Kollektor mit der Stromquellentransistor-Basis und der Eingangstransistor-Basis gekoppelt ist.


     
    11. Bipolar-HF-Verstärker (100), der die Vorspannungsschaltung (130) eines der vorhergehenden Ansprüche gekoppelt mit einer Verstärkerschaltung (140) umfasst.
     
    12. Bipolar-HF-Verstärker nach Anspruch 11, wobei die Verstärkerschaltung Folgendes umfasst:

    eine Kaskoden-Anordnung einer Stufe mit gemeinsamer Basis (Q1) und einer Stufe mit gemeinsamem Emitter (Q0);

    einen Eingang (126), der mit der Stufe mit gemeinsamem Emitter gekoppelt ist;

    einen Ausgang (124), der mit der Stufe mit gemeinsamer Basis gekoppelt ist.


     


    Revendications

    1. Circuit de polarisation (130) pour amplificateur bipolaire RF (140), le circuit de polarisation comprenant :

    une première borne de circuit de polarisation (114) configurée pour être couplée à une base d'un transistor à base commune (Q1) de l'amplificateur bipolaire RF (140) ;

    une seconde borne de circuit de polarisation (116) configurée pour être couplée à une base d'un transistor à émetteur commun (Q0) de l'amplificateur bipolaire RF (140) ;

    une source de courant (102) couplée à un rail de tension d'alimentation de polarisation (106) et un collecteur d'un premier transistor de polarisation (QB1) ;

    un réseau de polarisation couplé à la source de courant (102), à la première borne de circuit de polarisation (114), et à la seconde borne de circuit de polarisation (116) ; et

    un amplificateur tampon (110) présentant une entrée (108) couplée au collector du premier transistor de polarisation (QB1) et une sortie (112) couplée à la première borne de circuit de polarisation (114) ; dans lequel l'amplificateur tampon (110) est configuré pour au moins produire partiellement le courant fourni à la première borne de circuit de polarisation et collecter un courant à partir de la première borne de circuit de polarisation ; et dans lequel le réseau de polarisation est configuré pour fournir un courant à la première borne de circuit de polarisation (114) et à la seconde borne de circuit de polarisation (116), et le réseau de polarisation comprenant :

    le premier transistor de polarisation (QB1), un deuxième transistor de polarisation (QB2), et un troisième transistor de polarisation (QB3), une deuxième résistance de polarisation (RB2), et une troisième résistance de polarisation (RB3), dans lequel le premier transistor de polarisation (QB1) et le troisième transistor de polarisation (QB3) sont disposés en un empilement cascode entre la source de courant (102) et un rail d'alimentation commun (104), le premier transistor de polarisation (QB1) présentant une base couplée à la première borne de circuit de polarisation (114) et le troisième transistor de polarisation (QB3) présentant une base couplée à la seconde borne de circuit de polarisation (116) ; et

    le deuxième transistor de polarisation (QB2) présentant une base couplée à la base du premier transistor de polarisation, un collecteur couplé au rail de tension d'alimentation de polarisation (106), et un émetteur couplé au rail d'alimentation commun (104) par le biais d'un agencement série de la seconde résistance de polarisation (RB2) et de la troisième résistance de polarisation (RB3), dans lequel la base du troisième transistor de polarisation est couplée à un nœud commun entre la deuxième résistance de polarisation (RB2) et la troisième résistance de polarisation (RB3).


     
    2. Circuit de polarisation selon la revendication 1 comprenant en outre une première résistance de polarisation (RB1) disposée entre la base du troisième transistor de polarisation et la seconde borne de circuit de polarisation (116).
     
    3. Circuit de polarisation selon n'importe quelle revendication précédente dans lequel l'amplificateur tampon (200, 250, 300) comprend :

    un transistor de source de courant (QB4, QB5, QB7) présentant une base couplée à l'entrée de l'amplificateur tampon et un émetteur couplé à la sortie de l'amplificateur tampon,

    un collecteur de courant (202, QB6, QB8) disposé entre la sortie de l'amplificateur tampon et le rail d'alimentation commun.


     
    4. Circuit de polarisation selon la revendication 3 dans lequel l'amplificateur tampon (250, 300) comprend en outre un circuit de décalage de niveau (254, 302) présentant une première borne couplée au collecteur du transistor de source de courant et dans lequel le collecteur de courant comprend un transistor de collecte de courant (QB8) présentant une base couplée à une seconde borne du circuit de décalage de niveau, un collecteur couplé à la base du premier transistor de polarisation et un émetteur couplé au rail d'alimentation commun.
     
    5. Circuit de polarisation selon la revendication 4 dans lequel le circuit de décalage de niveau (302) comprend un agencement série d'au moins deux diodes (D1, D2) et une résistance (R5) couplée entre le collecteur du transistor de source de courant et le rail d'alimentation commun, et dans lequel la base du transistor de collecte de courant est couplée à un nœud commun d'une des au moins deux diodes et de la résistance.
     
    6. Circuit de polarisation selon l'une quelconque des revendications 4 ou 5 dans lequel l'amplificateur tampon (350) comprend en outre un élément de source de courant (RB6) disposé entre le rail de tension d'alimentation de polarisation (106) et le collecteur du transistor de source de courant.
     
    7. Circuit de polarisation selon la revendication 6 dans lequel l'élément de source de courant comprend une résistance (RB6).
     
    8. Circuit de polarisation selon la revendication 6 ou 7, dans lequel l'amplificateur tampon (350) comprend en outre un transistor de fixation du niveau (QB11) disposé en parallèle avec l'élément de source de courant.
     
    9. Circuit de polarisation selon n'importe quelle revendication précédente dans lequel l'amplificateur tampon comprend un amplificateur de classe AB.
     
    10. Circuit de polarisation selon n'importe quelle revendication précédente dans lequel l'amplificateur tampon comprend :

    un étage de sortie comportant un agencement série d'un transistor de source de courant (QB12) et d'un transistor de collecte de courant (QB12) entre le rail de tension d'alimentation de polarisation et le rail d'alimentation commun ;

    un agencement série d'un transistor d'entrée (QB13) et d'une diode de décalage de niveau (D5) entre le rail de tension d'alimentation de polarisation et le transistor de collecte de courant ;

    dans lequel la base du premier transistor de polarisation est couplée à l'émetteur du transistor de source de courant et à l'émetteur du transistor de collecte de courant, et le collecteur du premier transistor de polarisation est couplé à la base du transistor de source de courant et à la base du transistor d'entrée.


     
    11. Amplificateur bipolaire RF (100) comprenant le circuit de polarisation (130) selon n'importe quelle revendication précédente couplé à un circuit amplificateur (140).
     
    12. Amplificateur bipolaire RF selon la revendication 11 dans lequel le circuit amplificateur comprend :

    un agencement cascode d'un étage de base commune (Q1), et d'un étage d'émetteur commun (Q0) ;

    une entrée (126) couplée à l'étage d'émetteur commun ;

    une sortie (124) couplée à l'étage de base commune.


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description