(19)
(11)EP 3 525 252 A1

(12)EUROPEAN PATENT APPLICATION

(43)Date of publication:
14.08.2019 Bulletin 2019/33

(21)Application number: 19156079.6

(22)Date of filing:  07.02.2019
(51)Int. Cl.: 
H01L 43/08  (2006.01)
H01L 43/02  (2006.01)
H01L 43/12  (2006.01)
G11C 11/16  (2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 08.02.2018 US 201815891767

(71)Applicant: Taiwan Semiconductor Manufacturing Company, Ltd
Hsinchu 300-78 (TW)

(72)Inventors:
  • YI, YANG
    Fremont, CA 94539 (US)
  • ZHONGJIAN, TENG
    Santa Clara, CA 95051 (US)
  • YU-JEN, WANG
    San Jose, CA 95118 (US)

(74)Representative: Schuffenecker, Thierry 
120 Chemin de la Maure
06800 Cagnes sur Mer
06800 Cagnes sur Mer (FR)

  


(54)CMP STOP LAYER AND SACRIFICE LAYER FOR HIGH-YIELD SMALL SIZE MRAM DEVICES


(57) An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.




Description

BACKGROUND


1. Technical Field



[0001] This disclosure relates generally to the fabrication of magnetoresistive random access memory (MRAM) devices, specifically to methods of depositing and patterning multi-layered MTJ cells.

2. Description of the Related Art



[0002] Fabrication of magnetoresistive random-access memory (MRAM) devices normally involves a sequence of processing steps during which many layers of metals and dielectrics are deposited to form a stack and then the stack is patterned to form an array of separated magnetoresistive devices, such as MTJ (magnetic tunneling junctions) as well as top and bottom electrodes for making electrical connections to the devices. To define those magnetic tunnel junction (MTJ) cells in each MRAM device and make them non-interacting with each other (until such interconnections may be desired), precise patterning steps including photolithography and plasma etch such as reactive ion etching (RIE), ion beam etching (IBE) or their combination are usually involved. During photolithography, patterns are transferred from a photomask to a light-sensitive photoresist, then subsequently transferred to define arrays of MTJ devices by plasma etches, forming separate and non-interacting MTJ devices. After plasma etching, smaller size devices in the patterned array usually have less top electrode left because the photoresist covering them is consumed more quickly during this etching process. As a result of the disparity in electrode thicknesses which creates a non-planar top surface, it is challenging for the final top metal contact to connect them, resulting in open devices (devices where poor contacts are made). New approaches are needed if one wants to achieve high yield on small sizes (e.g. sub 60nm) of MTJ devices. It must be noted that several prior art patents disclose approaches to address some of the difficulties alluded to above. For example, U.S. Patent 9,070,869 (Jung et al) discloses a variety of layer constructions and U.S. Patent 8,975,088 (Satoh et al) teaches several different masking layers. However, neither of these prior arts teach the methods to be disclosed herein nor do they demonstrate the results that are obtained by application of those methods.

SUMMARY



[0003] An object of the present disclosure is to provide a method of improving the yield of arrays of small-sized layered MTJ devices and of a multiplicity of such devices of various dimensions, by adding additional layers between the hard mask used for patterning such MTJ devices and the electrode that is the top layer of the MTJ stack to be patterned.

[0004] A further object of the present disclosure is to provide such a yield improvement that can be attributed to eliminating electrical opens associated with damage to the very small top electrodes.

[0005] A still further object of the present disclosure is to provide the above stated benefits to a multiplicity of MTJ devices of various sizes adjacently disposed and being simultaneously processed on a common substrate.

[0006] In typical prior art processes, patterns are transferred from photoresist to a dielectric hard mask, then to a top electrode, and then to the MTJ stack beneath the top electrode. After the etch process to complete the pattern transfer, the remaining portion of the top electrode on the smaller portions of the pattern is found to be reduced in size when the pattern feature sizes are 60nm and below, resulting in an electric open (a failure in electrical conductivity) and great yield loss.

[0007] To eliminate these difficulties, the presently disclosed method inserts a CMP (chemical mechanical polishing) stop layer and a sacrifice layer between the photoresist hard mask pattern and the electrode. After plasma etch, any photoresist consumption difference would only result in different thicknesses (heights) of CMP sacrifice layer patterns. The top electrode thickness remains the same for all sizes of devices due to the protection of the CMP stop layer. By choosing proper slurries during the following CMP process, any remaining sacrifice patterns are completely removed, stopping on the CMP stop layer. The CMP stop layer is then removed by plasma etch, exposing the top electrode underneath. Using this method, different size MTJ cells retain the same height of their top electrode, making it easier to connect the later deposited top metal contact. Any yield loss due to electric opens is avoided. This method benefits the future generation of sub 60nm MRAM products as well as other fabrications having small sizes.

BRIEF DESCRIPTION OF THE DRAWINGS



[0008] 

Fig. 1A, 1B, 1C, 1D, 1E and 1F is a series of schematic illustrations showing the process flow of fabricating high yield MRAM devices of various sizes.

Fig. 2 is a table describing two slurries used to create CMP polishes with different polishing rates on different elements of a layered MRAM device.


DETAILED DESCRIPTION



[0009] A schematic set of Illustrations of the process flow is shown in Fig's 1A-1F, where there is shown the application of the method to simultaneously create two adjacent exemplary MTJ devices of different sizes but having top electrodes of substantially the same heights and coplanar upper surfaces so that the devices may be advantageously connected by a common metal contact without the formation of electrical opens (open circuits).

[0010] Referring first to Fig. 1A, there is schematically shown a single stack structure about to be patterned into two adjacent but separated MTJ devices by a first plasma etch. It is understood that two devices are exemplary to simplify the description and an array comprising a multiplicity of such separated devices is contemplated. We note here that the MTJ device is one type of active device element that may be processed using the following methodology, but any type of active multilayered device may be formed into an array including devices of various widths and provided with top electrodes having coplanar upper surfaces on which a single electrically connecting layer may be advantageously formed with no open circuits between array elements.

[0011] From the bottom up, there is shown a substrate layer 10, which may be a common electrical contact such as a layer of Ta, TaN, Ti or TiN or the top of an additional integrated electronic structure, a bottom electrode 20, a multilayered MTJ stack 30, a top electrode 40 of thickness between approx. 200-1000 A, a CMP stop layer 50 of thickness between approx. 20-300 A, a CMP sacrifice layer 60, of thickness between approx. 200-1000 A which is either alone or formed in combination with a hard mask (HM) layer (not separately shown) of thickness between approx. 200-2000 A. The additional hard mask (HM) layer, which is not shown here, may be deposited on the sacrifice layer 60 to improve the subsequent plasma etch selectivity. Note, the addition of a dielectric hard mask (HM) layer to improve the etch selectivity while etching the CMP sacrifice layer can be thought of as producing a "thick hard mask", where the combination works together to improve overall selectivity. For example, one can use plasma gas species such as CHF3, CH2F2 or C4F8 that will readily etch the HD, but which has a very low etch rate on the photoresist. Finally a photoresist layer (PR) is formed to a thickness of between approx. 1000-3000 A on the hard mask (if present) or sacrifice layer 60. The photoresist layer is shown as already having been photolithographically patterned into two portions, 701 and 702 of dimension d1 and d2 respectively, which will ultimately lead to the formation of two MTJ devices of those dimensions. The top electrode 40, deposited freely on top of the MTJ stack 30, is a layer of conducting material such as Ta, Ti, TaN or TiN. The CMP stop layer 50, is a layer of SiO2 or SiON and is deposited on the top electrode. The CMP sacrifice layer 60 is a layer of Ta, Ti, TaN and TiN and it is then deposited onto the CMP stop layer. Alternatively, to improve the subsequent plasma etch selectivity and pattern integrity, a dielectric hard mask, such as layer of SiN, SiO2 or SiON can be deposited on top of the CMP sacrifice layer (not specifically shown). Photoresist patterns 701 and 702 are formed by photolithography as is well known in the art. As also shown in Fig. 1a, two exemplary photoresist pattern sizes of d1 and d2, where d1>d2, are created here to help better understand how this method works. For this example, the width d1 is approx. 60-100nm and d2 is approx. 10-60 nm.

[0012] An important aspect of the exemplary process being shown herein is that one of the MTJ devices is larger (in horizontal dimension) than the other so that the etching process also leads to a different thickness (vertical dimension) which can have negative impact on process yields. A first plasma etch is shown being applied to the opening between 701 and 702 to separate the stack.

[0013] Referring next to Fig. 1B, there is shown the structure of Fig. 1A after a plasma etch (reactive ion RIE, ion-beam IBE or their combination) of the whole stack which leaves a space 80 between two remaining portions each of substantially uniform width d1 and d2 respectively. The portion of the stack having the larger size d1 includes a remaining CMP sacrifice layer portion 601 having a final thickness h1 that is larger than h2, the thickness of the smaller size pattern's CMP sacrifice layer 602. This final thickness difference is because the smaller layer of photoresist (702 in Fig. 1A) over the now smaller size pattern portion 602, is consumed more quickly during the plasma etch process, leading to part of the CMP sacrifice layer 602 being etched away as well. One can imagine that if the top electrode (40 in Fig. 1A) were located directly underneath the photoresist and/or the not-shown dielectric hard mask HM, then it would be the electrode portions 401 and 402 that would be left with different thicknesses instead of 601 and 602.

[0014] As shown in schematic Fig. 1C, after plasma etch, an encapsulation layer 90 is deposited into the patterned MTJ stack filling the space 80 (in Fig. 1B) between them. This layer is typically SiN, SC, or SiCN and is deposited by chemical vapor deposition (CVD). Next as also shown in Fig. 1C, a first CMP is applied, using slurry 1 as listed in Table 1, that provides a high polish rate for the encapsulation materials 80 as well as the alternative additional dielectric hard mask (if one is used). This first CMP process is applied to completely remove an upper portion of the encapsulation layer and additional hard mask portions (if present), stopping at the remaining CMP sacrifice layers 601 and 602.

[0015] As now also shown in Fig. 1C, a CMP process employing slurry 2, as listed in Table 1, is then used to completely polish away the remaining CMP sacrifice layer 601 and 602. This process stops on the CMP stop layers 501 and 502, since slurry 2 has an extremely low polish rate for the material of the CMP stop layers.

[0016] Next as shown schematically in Fig. ID, a second plasma etch is applied again to etch back the CMP stop layer 501 and 502, exposing the upper surfaces of top electrode 401 and 402 underneath. As shown schematically in Fig. IE, the resulting exposed top surfaces of the electrodes 401 and 402 are now coplanar and the two MTJ devices 301 and 302 are now electrically separate and completely defined by both upper 401, 402 and lower 201, 202 electrodes. At this point the devices are both at the same height and any height differences that were created by the first etch process shown in Fig. 1b have been eliminated.

[0017] Finally as shown in Fig. 1F, a common top metal contact 100, such as a layer of Ta, TaN, Ti, Al or Cu is deposited onto the coplanar surfaces of top electrodes 401 and 402 to form an electrical connection to the two exemplary (and otherwise electrically separate) MTJ devices 301 and 302. Large size pattern final width d3 and small size pattern final width d4 each have their own separate top electrodes 401 and 402 with coplanar upper surfaces and the same top electrode thickness h3, preventing any yield loss due to formation of electric opens when the top connection 100 is formed.

[0018] As is finally understood by a person skilled in the art, the detailed description given above is illustrative of the present disclosure rather than limiting of the present disclosure. Revisions and modifications may be made to methods, materials, structures and dimensions employed in forming and providing a multiplicity of small (in the horizontal dimensional range of approx. 60nm) MTJ devices having top electrodes of uniform thickness (vertical dimension) and thereby to improve device yield, while still forming and providing such a structure and its method of formation in accord with the spirit and scope of the present invention as defined by the appended claims.


Claims

1. An array comprising a multiplicity of adjacent, separated multilayered devices of various uniform widths (uniform horizontal dimensions) but all having a common height (vertical dimension), said devices having coplanar upper surfaces and said devices being electrically connected by a common top metal contact, the array comprising:

a common substrate;

a multiplicity of N spatially separated multilayered devices formed on said common substrate, wherein

each said multilayered device has a width dn where n runs from 1 to N and wherein said widths are generally different;

wherein each of said N multilayered devices has common height h and wherein there is a space-filling encapsulation layer of variable width sjk between adjacent multilayered devices where j varies from 1 to N, and k=j+1; wherein

each said multilayered device further comprises:

a lower electrode of substantially identical thickness;

an active device element formed on said lower electrode;

an upper electrode formed on said active device element, wherein said upper electrode has a substantially identical thickness and wherein upper surfaces of all said upper electrodes are coplanar; and

a single top metal contact formed over said upper electrodes, making open-free electrical contact with each said upper electrode.


 
2. The array of claim 1 wherein said top and bottom electrodes are formed of Ta, Ti, TaN or TiN, of thicknesses between approximately 200-1000A.
 
3. The array of claim 1 wherein each said active device element is an MTJ (magnetic tunnel junction) device.
 
4. The array of claim 1 wherein an exemplary device width is approximately 60 nm or less.
 
5. The array of claim 1 wherein said encapsulation layer is a layer of SiN, SC or SiCn.
 
6. A method for forming an array of electrically separated, adjacent, multilayered devices of various widths and separation spacings but of a common height configured for a final common electrical connection to each device, said connection having no electrical open circuits, the method comprising:

providing a substrate;

forming on said substrate, in sequential contiguous order, a multilayered stack comprising:

a bottom electrode contacting said substrate;

a multilayered stack comprising functional device layers;

a top electrode of height h3 covering said multilayered stack;

a CMP (Chemical Mechanical Polishing) stop layer covering said top electrode;

a CMP sacrifice layer or a combined CMP sacrifice layer and hard mask layer, formed over said CMP stop layer;

a patterned photoresist layer defining widths and spacings for said device array, then;

using said photoresist layer, patterning said multilayered stack.


 
7. The method of claim 6 wherein said patterning process comprises:

using a first plasma etch applied through said patterned photoresist layer, separating said multilayered stack into an array of separated adjacent portions, each portion having a width and each portion having a spacing from an adjacent portion predetermined by said patterned photoresist layer and each portion having an undetermined unique height resulting from a final undetermined height of said CMP sacrifice layer or said combined CMP sacrifice layer and hard mask layer resulting from said first plasma etch; then

refilling portions of said multilayered stack removed by said first plasma etch by depositing an encapsulation layer therein; then

using a first slurry and a first CMP process, removing a top portion of said encapsulation layer and said hard mask layer if a combined CMP layer and hard mask layer was used, stopping at said CMP sacrifice layer or, if no hard mask layer was used, removing said top portion of said encapsulation layer stopping at said CMP sacrifice layer; then

using a second slurry and a second CMP process, removing said CMP sacrifice layer, stopping at said CMP stop layer; then

applying a second plasma etch process, removing said CMP stop layer exposed by said second CMP process, thereby exposing said top electrode on each portion of said patterned multilayered stack, wherein top surfaces of each said top electrode and of said encapsulation layer between adjacent portions are coplanar and wherein each said top electrode has the same said height h3; then

forming a top metal contact over said coplanar top surfaces whereby said top metal contact makes electrical contact with each of said top electrodes and wherein said electrical contact is free of any electrical open circuits.


 
8. The method of claim 6 wherein h3 is between approximately 200-1000 A.
 
9. The method of claim 6 wherein a combined hard mask layer and CMP stop layer would allow using a plasma etch comprising CHF3, CH2F2 or C4F8 that will readily etch the dielectric hard mask but which has a very low etch rate on the photoresist layer.
 
10. The method of claim 6 wherein said hard mask layer is a layer of SiN, SiO2 or SiON.
 
11. The method of claim 6 wherein said CMP sacrifice layer is a layer of Ta, Ti, TaN or TiN.
 
12. The method of claim 6 wherein said CMP stop layer is a layer of SiO2 or SiON.
 
13. The method of claim 6 wherein said first slurry is a slurry of Zirconium Oxide particles.
 
14. The method of claim 6 wherein said second slurry is a slurry of Aluminum Oxide particles.
 




Drawing




















REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description