(19)
(11)EP 3 527 126 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
22.07.2020 Bulletin 2020/30

(21)Application number: 17905908.4

(22)Date of filing:  18.12.2017
(51)International Patent Classification (IPC): 
A61B 5/024(2006.01)
G11C 27/02(2006.01)
H03F 3/00(2006.01)
H03G 3/30(2006.01)
G01R 19/00(2006.01)
H03F 1/08(2006.01)
A61B 5/00(2006.01)
H03F 1/26(2006.01)
H03F 3/08(2006.01)
H03G 3/32(2006.01)
G11C 7/02(2006.01)
H04N 5/355(2011.01)
(86)International application number:
PCT/CN2017/116831
(87)International publication number:
WO 2019/119176 (27.06.2019 Gazette  2019/26)

(54)

CURRENT SAMPLING AND HOLDING CIRCUIT FOR AN OPTICAL SENSOR

STROMABTASTUNG UND HALTESCHALTUNG FÜR EINEN OPTISCHEN SENSOR

CIRCUIT D'ÉCHANTILLONNAGE ET DE MAINTIEN DE COURANT POUR UN CAPTEUR OPTIQUE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
21.08.2019 Bulletin 2019/34

(73)Proprietor: Shenzhen Goodix Technology Co., Ltd.
Shenzhen, Guangdong 518045 (CN)

(72)Inventors:
  • LI, Jingshan
    Shenzhen, Guangdong 518045 (CN)
  • ZHANG, Mengwen
    Shenzhen, Guangdong 518045 (CN)

(74)Representative: EIP 
EIP Europe LLP Fairfax House 15 Fulwood Place
London WC1V 6HU
London WC1V 6HU (GB)


(56)References cited: : 
EP-A1- 0 046 396
CN-A- 102 353 395
CN-A- 106 535 753
CN-Y- 201 215 954
US-A1- 2017 031 008
EP-A1- 3 255 789
CN-A- 104 359 455
CN-A- 106 599 754
US-A1- 2009 167 364
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] This disclosure relates to current sample-and-hold technologies, and particularly, to a current sample-and-hold circuit and a sensor.

    BACKGROUND



    [0002] In an existing heart rate detection circuit, a photodiode is generally used for receiving reflected light from human body, and then an integrator is utilized to convert an induced current of the photodiode into a voltage signal for subsequent processing. However, due to presence of ambient light, the integrator is usually saturated, which affects normal operation of the circuit. Therefore, a current sample-and-hold circuit needs to be introduced to offset a background photocurrent (i.e., the induced current generated by the photodiode due to receiving the ambient light) in the photodiode so as to prevent saturation of the integrator.

    [0003] A conventional current sample-and-hold circuit is as shown in Fig. 1. In Fig. 1, a current output circuit in the current sample-and-hold circuit is formed by a P-channel Metal Oxide Semiconductor (PMOS) transistor M of a fixed size. The PMOS transistor M, in a sampling stage, is used for sampling the background photocurrent of the photodiode PD (i.e., the induced current of a photodiode PD, namely, a current of a variable current source IBG in Fig. 1) and converting the sampled current into a voltage of a capacitor CSH. In an integrating stage, the PMOS transistor M is used for conveying the previous sampled current to the photodiode PD so as to offset the background photocurrent of the photodiode.

    [0004] In a case where an area of the photodiode PD remains unchanged, the background photocurrent of the photodiode PD increases as light intensity increases. In a case where the light intensity remains unchanged, the background photocurrent of the photodiode PD is in turn proportional to the area of the photodiode PD. Therefore, when the area of the photodiode PD remains unchanged and the light intensity changes within a large range, or when the light intensity remains unchanged and the area of the photodiode PD changes within a large range, the background photocurrent of the photodiode PD can be changed within a large range. When the background photocurrent of the photodiode PD is very large, a gate-to-source voltage of the PMOS transistor M can also become very large, and the voltage of the capacitor CSH is equal to the gate-to-source voltage of the PMOS transistor M and also becomes larger. When the voltage of the capacitor CSH becomes large, a reversed bias voltage of the photodiode PD becomes small. When the reversed bias voltage decreases to a certain degree, a working efficiency of the photodiode PD is greatly reduced. Therefore, in existing technologies, in order to ensure the working efficiency of the photodiode PD, the voltage of the capacitor CSH is avoided to become very large, that is, the background photocurrent of the photodiode PD is avoided to become very large. That is to say, the conventional current sample-and-hole circuit can only be used for offsetting a relatively small background photocurrent.

    [0005] EP3255789A1 provides a conversion circuit for converting a current signal into a first output voltage signal, where the current signal flows through a sensing component. The conversion circuit includes: a first current eliminating circuit, configured to eliminate a first current in the current signal, the first current eliminating circuit including: a current sample and hold circuit; and a current driving circuit, coupled between the sensing component and the current sample and hold circuit; a second current eliminating circuit, coupled to the sensing component and configured to eliminate a second current in the current signal; and an integrating circuit, coupled to the sensing component and configured to integrating for a third current in the current signal, and output a first input voltage signal between a first integration output terminal and a second integration output terminal. A background photoelectric current and a base current in the current signal may be eliminated, and integration may be carried out for a heartbeat current in the current signal by using the integrating circuit, such that the impacts caused by the background photoelectric current and the base current to the heartbeat current are removed, and the detection efficiency is improved.

    SUMMARY



    [0006] An embodiment of the invention is defined by independent claim 1, preferred embodiments of the invention are further defined by dependent claims 2-8. An
    objective of some exemplary embodiments in this disclosure is to provide a current sample-and-hold circuit and a sensor, which enable the current sample-and-hold circuit to offset a wider range of background photocurrent on the premise of avoiding a change of a voltage of a capacitor within a large range.

    [0007] One exemplary embodiment of this disclosure provides a current sample-and-hold circuit, which is used for offsetting a background photocurrent of a photodiode and includes: a capacitor and a first transconductance amplifier which has adjustable transconductance and is used for outputting a sampled current to the photodiode to offset the background photocurrent of the photodiode; one end of the capacitor is connected with a power supply VDD, and the other end of the capacitor is connected with one end of the first transconductance amplifier; and the other end of the first transconductance amplifier is used for being connected with the photodiode so as to output the sampled current to the photodiode to offset the background photocurrent of the photodiode.

    [0008] An exemplary embodiment of this disclosure further provides a sensor, the sensor is integrated with a photodiode and the above-mentioned current sample-and-hold circuit, and the other end of the first transconductance amplifier of the current sample-and-hold circuit is connected with the photodiode.

    [0009] Compared to existing technologies, according to the exemplary embodiments of this disclosure, the first transconductance amplifier with the adjustable transconductance is arranged in the current sample-and-hold circuit, and according to a formula I=gm1U, it can be known that when the background photocurrent I of the photodiode increases (which is caused by a change of light intensity or caused by a change of an area of the photodiode), a change of a voltage U of the capacitor within a large range can be avoided by increasing the transconductance gm1 of the first transconductance amplifier, so that the current sample-and-hold circuit can offset a larger background photocurrent.

    [0010] In addition, the first transconductance amplifier includes a plurality of first electronic switches and a plurality of control switches for controlling the first electronic switches; the plurality of first electronic switches are connected between the power supply VDD and the photodiode, the plurality of first electronic switches are connected in series, and control ends of the plurality of first electronic switches are all connected with the other end of the capacitor; a junction between any two adjacent first electronic switches corresponds to one control switch, one end of each control switch is connected with the power supply VDD, and the other end of each control switch is connected with the corresponding junction. An implementation of the first transconductance amplifier is provided.

    [0011] In addition, the current sample-and-hold circuit further includes a first sampling switch and a bias circuit for providing a bias voltage to the first transconductance amplifier; one end of the bias circuit is simultaneously connected with one end of the first transconductance amplifier and the other end of the capacitor through the first sampling switch; and the other end of the bias circuit is used for being connected with the photodiode. When the first sampling switch is closed, a closed-loop negative feedback is formed in the current sample-and-hold circuit.

    [0012] In addition, the bias circuit includes a second electronic switch and a second transconductance amplifier; a first end of the second electronic switch is connected with the power supply VDD; a second end of the second electronic switch is connected with one end of the second transconductance amplifier; a control end of the second electronic switch, as one end of the bias circuit, is connected with the first sampling switch and a junction between the second end of the second electronic switch and one end of the second transconductance amplifier; and the other end of the second transconductance amplifier, as the other end of the bias circuit, is used for being connected with the photodiode. A structure of the bias circuit is provided.

    [0013] In addition, the second transconductance amplifier includes a second sampling switch, an amplification circuit, a first current source, a third electronic switch and a fourth electronic switch; a first end of the third electronic switch is connected with the second end of the second electronic switch; a second end of the third electronic switch is grounded; a control end of the third electronic switch is connected with a junction between a second end of the first current source and a first end of the fourth electronic switch, and a control end of the fourth electronic switch; a first end of the first current source is connected with the power supply VDD; the first end of the fourth electronic switch is also connected with one end of the amplification circuit through the second sampling switch; a second end of the fourth electronic switch is grounded; and the other end of the amplification circuit is used for being connected with the photodiode. An implementation of the second transconductance amplifier is provided.

    [0014] In addition, the amplification circuit includes a second current source and a fifth electronic switch; a first end of the fifth electronic switch, as one end of the amplification circuit, is respectively connected with the second current source and the second sampling switch; a second end of the fifth electronic switch is grounded; and a control end of the fifth electronic switch, as the other end of the amplification circuit, is used for being connected with the photodiode. The amplification circuit may be an amplification circuit in an integrator, which is beneficial for implementing multiplexing on the amplification circuit.

    [0015] In addition, the first electronic switch is a PMOS transistor; a plurality of PMOS transistors are sequentially arranged along a direction towards the photodiode; in the plurality of PMOS transistors, a first PMOS transistor is a PMOS transistor the closest to the photodiode, and a last PMOS transistor is a PMOS transistor the furthest away from the photodiode; and a width-to-length ratio of the first PMOS transistor is equal to that of a second PMOS transistor, a width-to-length ratio of an ith PMOS transistor is twice of a width-to-length ratio of a (i-1)th PMOS transistor, and the i is greater than or equal to 3. An implementation of the first electronic switch is provided.

    [0016] In addition, the second electronic switch is a PMOS transistor, and a width-to-length ratio of the second electronic switch is equal to that of the first PMOS transistor. A relationship between the first electronic switch and the second electronic switch is provided.

    [0017] In addition, the current sample-and-hold circuit further includes a third sampling switch; and the third sampling switch is connected in parallel to the capacitor. Before sampling, charges on the capacitor can be released by closing the third sampling switch so as to ensure accuracy of sampling.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0018] The invention is defined by appended claims 1-8. One or more exemplary embodiments are illustrated by figures in corresponding accompanying drawings. Elements with the same reference numeral in the accompanying drawings represent similar elements. Unless specified otherwise, the figures in the accompanying drawings do not constitute a proportional limitation.

    Fig. 1 is a structural schematic diagram of a current sample-and-hold circuit according to existing technologies;

    Fig. 2 is a structural schematic diagram of a current sample-and-hold circuit according to a first exemplary embodiment of this disclosure;

    Fig. 3 is a structural schematic diagram of a current sample-and-hold circuit according to a second exemplary embodiment of this disclosure; and

    Fig. 4 is a structural schematic diagram of a current sample-and-hold circuit according to a third exemplary embodiment of this disclosure.


    DETAILED DESCRIPTION



    [0019] In order to make objectives, technical solutions and advantages of this disclosure more apparent, some exemplary embodiment of this disclosure will be further illustrated in detail in combination with accompanying drawings. It should be understood that specific exemplary embodiments described herein merely are used for explaining this disclosure, and not intended to limit this disclosure. The invention is defined by appended claims 1-8.

    [0020] A first exemplary embodiment of this disclosure relates to a current sample-and-hold circuit. As shown in Fig. 2, the current sample-and-hold circuit is used for offsetting a background photocurrent of a photodiode, and includes a capacitor CSH and a first transconductance amplifier OTA1 which is used for outputting a sampled current to the photodiode to offset the background photocurrent of the photodiode. One end of the capacitor CSH is connected with a power supply VDD, and the other end of the capacitor CSH is connected with one end of the first transconductance amplifier OTA1; and the other end of the first transconductance amplifier OTA1 is connected with the photodiode PD. In Fig. 2, a current of a variable current source IBG is the background photocurrent of the photodiode PD; and a parasitic capacitance CPD is a parasitic capacitance of the photodiode PD.

    [0021] In the exemplary embodiment, a transconductance of the first transconductance amplifier OTA1 is set to be adjustable. A working process of the current sample-and-hold circuit will be specifically illustrated below.

    [0022] Specifically, the working process of the current sample-and-hold circuit includes a sampling stage and an integrating stage. In the sampling stage, a current of the first transconductance amplifier OTA1, which flows into the photodiode PD, is equal to the current of the variable current source IBG (i.e., the background photocurrent of the photodiode PD), and the capacitor CSH equivalently samples the background photocurrent and converts the background photocurrent into a voltage of the capacitor CSH. The capacitor CSH specifically may be a holding capacitor, but in practical applications, is not limited thereto.

    [0023] When the background photocurrent of the photodiode PD is changed (which is caused by a change of light intensity or caused by a change of an area of the photodiode), i.e., when the current of the variable current source IBG is changed, the transconductance of the first transconductance amplifier OTA1 may be adjusted to avoid the change of the voltage U of the capacitor within a large range. According to a formula I=gm1U, it can be known that when the background photocurrent I of the photodiode is increased, a change of the voltage U of the capacitor within the large range can be avoided by increasing the transconductance gm1 of the first transconductance amplifier. Therefore, even though the current sample-and-hold circuit samples a background photocurrent within a larger range, the change of the voltage U of the capacitor within the large range can also be avoided. Particularly, the transconductance gm1 of the first transconductance amplifier and the background photocurrent I of the photodiode can be changed according to a same proportion, so that the voltage U of the capacitor can be kept unchanged.

    [0024] After the sampling stage ends, the integrating stage is processed. At the moment, the voltage of the capacitor CSH is converted into a current (a value of the current is equal to that of the background photocurrent sampled previously), and the current is output to the photodiode PD through the first transconductance amplifier OTA1 so as to offset the background photocurrent of the photodiode PD. The background photocurrent of the photodiode PD is equivalently offset by the previous sampled current.

    [0025] Compared to existing technologies, according to the exemplary embodiment, the first transconductance amplifier with adjustable transconductance is arranged in the current sample-and-hold circuit, and according to the formula I=gm1U, it can be known that when the background photocurrent I of the photodiode is increased (which is caused by the change of the light intensity or caused by the change of the area of the photodiode), the change of the voltage U of the capacitor within the large range can be avoided by increasing the transconductance gm1 of the first transconductance amplifier, and the current sample-and-hold circuit can offset the background photocurrent within the larger range.

    [0026] A second exemplary embodiment of this disclosure relates to a current sample-and-hold circuit. The second exemplary embodiment is further improved based on the first exemplary embodiment, and an improvement is mainly that the second embodiment provides a bias circuit for providing a bias voltage to the first transconductance amplifier OTA1.

    [0027] As shown in Fig. 3, the current sample-and-hold circuit in the exemplary embodiment further includes a first sampling switch SW1 and the bias circuit 31 for providing the bias voltage to the first transconductance amplifier OTA1. A first end of the bias circuit 31 is connected with the first sampling switch SW1, and is further connected with one end of the first transconductance amplifier OTA1 and the other end of the capacitor CSH simultaneously through the first sampling switch SW1. A second end of the bias circuit 31 is connected with the power supply VDD, and a third end of the bias circuit 31 is connected with the photodiode PD.

    [0028] In practical applications, the bias circuit 31 may include a second electronic switch M3 and a second transconductance amplifier OTA2. The second electronic switch M3 may be formed by a field effect transistor or other electronic transistors, and the field effect transistor may be a PMOS transistor or a N-channel metal oxide semiconductor (NMOS) transistor. The second electronic switch in Fig. 3 is the PMOS transistor as an example, but in practical applications, the NMOS transistor may also be selected as the second electronic switch as required, and the exemplary embodiment is not limited thereto. A first end of the second electronic switch M3 (i.e., a source of the PMOS transistor in Fig. 3), as the second end of the bias circuit 31, is connected with the power supply VDD. A second end of the second electronic switch M3 (i.e., a drain of the PMOS transistor in Fig. 3) is connected with one end of the second transconductance amplifier OTA2. A control end of the second electronic switch M3 (i.e., a gate of the PMOS transistor in Fig. 3), as the first end of the bias circuit 31, is connected with the first sampling switch SW1 and a junction between the second end of the second electronic switch M3 and one end of the second transconductance amplifier OTA2. The other end of the second transconductance amplifier OTA2, as the third end of the bias circuit 31, is connected with the photodiode PD.

    [0029] According to the exemplary embodiment, a third sampling switch SW3 may also be connected in parallel to the capacitor CSH, and the third sampling switch SW3 is closed before the sampling stage starts. At the moment, two ends of the capacitor CSH are connected, and the capacitor CSH is in a discharge state. This helps to eliminate charges on the capacitor CSH and ensure accuracy of sampling.

    [0030] In the sampling stage, the third sampling switch SW3 may be off and the first sampling switch SW1 is closed. At the moment, a closed-loop negative feedback is formed in the entire current sample-and-hold circuit. A first end of the second transconductance amplifier OTA2 (i.e., the end for being connected with the photodiode PD) inputs a cathode voltage of the photodiode PD, and a second end of the second transconductance amplifier OTA2 (i.e., the end for being connected with the second electronic switch M3) outputs a current into the second electronic switch M3 (i.e., provides a bias current to the second electronic switch M3). When a current passes through the second electronic switch M3, a voltage may be generated so as to provide the bias voltage to the first transconductance amplifier OTA1 and trigger the first transconductance amplifier OTA1 to be in a working state. At the moment, a current of the first transconductance amplifier OTA1, which flows into the photodiode PD, is equal to a current of the variable current source IBG (i.e., the background photocurrent of the photodiode PD), and the capacitor CSH equivalently samples the background photocurrent and converts the background photocurrent into the voltage of the capacitor CSH.

    [0031] Similarly, when the background photocurrent of the photodiode PD is changed (which is caused by the change of light intensity or caused by the change of the area of the photodiode), the transconductance of the first transconductance amplifier OTA1 may be adjusted to avoid the change of the voltage U of the capacitor within a large range. For example, when the background photocurrent I of the photodiode is increased, the change of the voltage U of the capacitor within a large range with increase of the background photocurrent I can be avoided by increasing the transconductance gm1 of the first transconductance amplifier. Therefore, not only can the current sample-and-hold circuit samples the background photocurrent in a larger range, but also the voltage U of the capacitor can be avoided from changing within a large range.

    [0032] After the sampling stage ends, the first sampling switch SW1 may be off, and at the moment, the circuit enters the integrating stage. As mentioned above, in the sampling stage, the current of the first transconductance amplifier OTA1, which flows into the photodiode PD, is equal to the current of the variable current source IBG (i.e., the background photocurrent of the photodiode PD), and the capacitor CSH equivalently samples the background photocurrent and converts the background photocurrent into the voltage of the capacitor CSH. In the integrating stage, the voltage of the capacitor CSH is converted into a current (a value of the current is equal to a value of the background photocurrent sampled previously), and the current is output to the photodiode PD through the first transconductance amplifier OTA1 so as to offset the background photocurrent of the photodiode PD. The background photocurrent of the photodiode PD is equivalently offset by the previous sampled current.

    [0033] In addition, it is worth mentioning that in the exemplary embodiment, a loop formed by the current sample-and-hold circuit includes two poles, one pole is a dominant pole P1 (corresponding to a node between the first transconductance amplifier OTA1 and the photodiode PD), and the other pole is a non-dominant pole P2 (corresponding to a node among the control end of the second electronic switch M3, the second end of the second electronic switch M3 and the second transconductance amplifier OTA2). A position formula of the non-dominant pole P2 is that: P2=1/(r2C2), where r2 represents an equivalent impedance of the corresponding node, and C2 represents an equivalent capacitance of the corresponding node. It can be seen that a position of the pole P2 is unrelated to the photodiode PD, and thus, when the area of the photodiode PD is changed, the position of the non-dominant pole is kept unchanged. A gain bandwidth product GBW of the loop is gm1gm2r2/CPD, where gm2 represents a transconductance of the second transconductance amplifier OTA2, and CPD represents a parasitic capacitance of the photodiode PD. When the area of the photodiode PD is changed, CPD can also be synchronously changed (for example, when the area of the photodiode PD is increased by A times, CPD may also be increased by A times), and at the moment, gm1 is changed according to an equal proportion (i.e., make gm1 also increased by A times) by adjusting the transconductance gm1 of the first transconductance amplifier OTA1, so that the gain bandwidth product GBW may be kept unchanged. The gain bandwidth product GBW is kept unchanged and the position of the non-dominant pole P2 is also kept unchanged, so that stability of the entire loop is not influenced by the change of the area of the photodiode PD.

    [0034] Compared to the first exemplary embodiment, according to the example, when the background photocurrent I of the photodiode PD is increased (which is caused by the change of the light intensity or caused by the change of the area of the photodiode), the change of the voltage U of the capacitor within the large range with increase of the background photocurrent I can be avoided by increasing the transconductance gm1 of the first transconductance amplifier, and the background photocurrent changing within a larger range can be offset by the current sample-and-hold circuit. Meanwhile, when the area of the photodiode PD is changed, the transconductance gm1 of the first transconductance amplifier is changed in the same proportion as the area of the photodiode PD is changed by adjusting the transconductance gm1 of the first transconductance amplifier, so that stability of the entire circuit is not influenced by the change of the area of the photodiode PD.

    [0035] A third exemplary embodiment of this disclosure relates to a current sample-and-hold circuit. The third exemplary embodiment provides an implementation of the first transconductance amplifier and the second transconductance amplifier based on the second exemplary embodiment.

    [0036] As shown in Fig. 4, the first transconductance amplifier OTA1 may include a plurality of first electronic switches and a plurality of control switches for controlling the first electronic switches. The plurality of first electronic switches are connected between the power supply VDD and the photodiode PD, the plurality of first electronic switches are connected in series, and control ends of the plurality of first electronic switches are all connected with the other end of the capacitor CSH. Moreover, a junction between any two adjacent first electronic switches corresponds to one control switch, one end of each control switch is connected with the power supply VDD, and the other end of each control switch is connected with the corresponding junction.

    [0037] Specifically, the first electronic switch may be formed by a field effect transistor or other electronic transistors, and the field effect transistor may be a PMOS transistor or a NMOS transistor. Fig. 4 illustrates that the first electronic switch is the PMOS transistor and the number of the first electronic switches is equal to 4. Four first electronic switches in Fig. 4 are respectively a PMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6 and a PMOS transistor M7 which are sequentially connected. A source of the PMOS transistor M4, as one end of the first transconductance amplifier OTA1, is connected to the capacitor CSH; and a drain of the PMOS transistor M4 is connected with a source of the PMOS transistor M5, a drain of the PMOS transistor M5 is connected with a source of the PMOS transistor M6, a drain of the PMOS transistor M6 is connected with a source of the PMOS transistor M7, and a drain electrode of the PMOS transistor M7, as the other end of the first transconductance amplifier OTA1, is connected with the photodiode PD. Gates of the PMOS transistor M4, PMOS transistor M5, PMOS transistor M6 and PMOS transistor M7 are all connected with the other end of the capacitor CSH.

    [0038] The control switch may be an electronic switch or a common mechanical switch, and the electronic switch may be a field effect transistor, e.g., a PMOS transistor or a NMOS transistor. Fig. 4 illustrates that the control switch is the PMOS transistor and the number of the control switches is equal to 3. Three control switches in Fig. 4 are respectively a M8 (i.e., CN1), a M9 (i.e., CN2) and a M10 (i.e., CN3). A junction corresponding to the control switch M8 is a junction between the PMOS transistor M6 and the PMOS transistor M7, a junction corresponding to the control switch M9 is a junction between the PMOS transistor M5 and the PMOS transistor M6, and a junction corresponding to the control switch M10 is a junction between the PMOS transistor M4 and the PMOS transistor M5. It is worth mentioning that when the PMOS transistor or the NMOS transistor is selected as the control switch, a gate of the PMOS transistor or the NMOS transistor may be float, and a source and a drain thereof are used as two connecting terminals of the control switch. In the exemplary embodiment, the PMOS transistor is preferably selected as the control switch as compared with the NMOS transistor, because a substrate of the PMOS transistor is short connected with the source, thus the PMOS transistor has no substrate bias effect and has a better conduction characteristic.

    [0039] It should be noted that the exemplary embodiment merely illustrates that the number of the first electronic switches is 4 and the number of the control switches is 3. In practical applications, the number of the first electronic switches may also be flexibly selected according to the actual situation, the number of the control switches is adaptively adjusted according to the number of the first electronic switches, and the exemplary embodiment is not limited thereto.

    [0040] The second transconductance amplifier OTA2 may include a second sampling switch SW2, an amplification circuit 41, a first current source IB 1, a third electronic switch M2 and a fourth electronic switch M1. The third electronic switch M2 and the fourth electronic switch M1 may be formed by field effect transistors or other electronic transistors, and the field effect transistors may be PMOS transistors or NMOS transistors. Fig. 4 illustrates that both the third electronic switch M2 and the fourth electronic switch M1 are NMOS transistors. A first end of the third electronic switch M2 (i.e., a drain of the NMOS transistor M2 in Fig. 4) is connected with a second end of the second electronic switch M3. A second end of the third electronic switch M2 (i.e., a source of the NMOS transistor M2 in Fig. 4) is grounded. A control end of the third electronic switch M2 (i.e., a gate of the NMOS transistor M2 in Fig. 4) is connected with a junction between a second end of the first current source IB1 and a first end of the fourth electronic switch M1 (i.e., a drain of the NMOS transistor M1 in Fig. 4) as well as a control end of the fourth electronic switch M1 (i.e., a gate of the NMOS transistor M1 in Fig. 4). A second end of the fourth electronic switch M1 (i.e., a source electrode of the NMOS transistor M1 in Fig. 4) is grounded. A first end of the first current source IB1 is connected with the power supply VDD. The first end of the fourth electronic switch M1 is also connected with one end of the amplification circuit 41 through the second sampling switch SW2; and the other end of the amplification circuit 41 is connected with the photodiode PD.

    [0041] In the exemplary embodiment, the amplification circuit 41 may be an amplification circuit in the integrator, which is beneficial for implementing multiplexing on the amplification circuit. The amplification circuit 41 may include a second current source IB2 and a fifth electronic switch MA. The fifth electronic switch MA may be formed by a field effect transistor or other electronic transistors, and the field effect transistor may be a PMOS transistor or an NMOS transistor. Fig. 4 illustrates that the fifth electronic switch MA is the NMOS transistor. A first end of the fifth electronic switch MA (i.e., a drain of the NMOS transistor MA in Fig. 4), as one end of the amplification circuit 41, is respectively connected with the second current source IB2 and the second sampling switch SW2; a second end of the fifth electronic switch MA (i.e., a source of the NMOS transistor MA in Fig. 4) is grounded; and a control end of the fifth electronic switch MA (i.e., a gate of the NMOS transistor MA in Fig. 4), as the other end of the amplification circuit 41, is connected with the photodiode PD.

    [0042] When the plurality of first electronic switches in the first transconductance amplifier OTA1 are all field effect transistors, an equivalent width-to-length ratio of conductive field effect transistors and an equivalent output impedance of conductive field effect transistors may be adjusted by controlling the number of conductive field effect transistors, so that an objective to adjust a transconductance of the first transconductance amplifier OTA1 is fulfilled, a larger background photocurrent can be offset by the current sample-and-hold circuit in the premise of avoiding the voltage U of the capacitor from changing within a large range, and stability of the current sample-and-hold circuit is not influenced by the change of the area of the photodiode PD.

    [0043] The following illustrates that the plurality of first electronic switches are all PMOS transistors. Specifically, when the plurality of first electronic switches are all the PMOS transistors, width-to-length ratios of the plurality of PMOS transistors should meet a relationship that: when the plurality of PMOS transistors are sequentially arranged towards the photodiode PD, a first PMOS transistor refers to a PMOS transistor the closest to the photodiode PD, and a last PMOS transistor refers to a PMOS transistor the furthest away from the photodiode PD. A width-to-length ratio of the first PMOS transistor is equal to that of a second PMOS transistor, and a width-to-length ratio of an ith PMOS transistor is twice of a width-to-length ratio of a (i-1)thPMOS transistor, wherein the i is greater than or equal to 3. When the second electronic switch M3 is also a PMOS transistor, a width-to-length ratio of the second electronic switch M3 may be equal to that of the first PMOS transistor. Namely, a width-to-length ratio of the PMOS transistor M7 is equal to that of the PMOS transistor M6, i.e., (W/L)M7=(W/L)M6; a width-to-length ratio of the PMOS transistor M5 is twice of that of the PMOS transistor M6, i.e., (W/L)M5=2(W/L)M6; a width-to-length ratio of the PMOS transistor M4 is twice of that of the PMOS transistor M5, i.e., (W/L)M4=2(W/L)M5; and a width-to-length ratio of the second electronic switch M3 is equal to that of the PMOS transistor M7, i.e., (W/L)M3=(W/L)M7.

    [0044] It is worth mentioning that in the practical application, one or more PMOS transistors may further be connected in series between the PMOS transistor M4 and the power supply VDD (the number of the PMOS transistors connected in series can be determined according to the actual situation), in order to cover a larger range of the background photocurrent (i.e., cover a larger change range of the area of the photodiode). For example, when one PMOS transistor is further connected in series between the PMOS transistor M4 and the power supply VDD, a width-to-length ratio of this PMOS transistor should be twice of that of the PMOS transistor M4.

    [0045] In the sampling stage, the third sampling switch SW3 is off, and the first sampling switch SW1 and the second sampling switch SW2 are closed. At the moment, a closed-loop negative feedback is formed in the current sample-and-hold circuit. The first current source IB1 and the second current source IB2 provide currents to the fourth electronic switch M1, and a voltage is generated on the fourth electronic switch M1, so that a bias voltage is provided to the third electronic switch M2. After receiving the bias voltage, the third electronic switch M2 generates a current so as to provide a bias current to the second electronic switch M3. After receiving the bias current, the second electronic switch M3 generates a voltage so as to provide a bias voltage to the gates of the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 (i.e., provide the bias voltage to the plurality of first electronic switches) and trigger the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 to be in a working state. At the moment, a current flowing into the photodiode PD through the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 is equal to that of a variable current source IBG (i.e., the background photocurrent), and the capacitor CSH equivalently samples the background photocurrent and converts the background photocurrent into a voltage of the capacitor CSH.

    [0046] In a case where light intensity is unchanged, when the area of the photodiode PD is minimum, the background photocurrent is also minimum. At the moment, the control switches M8, M9 and M10 may be off, so that the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 are all conductive. At the moment, the equivalent width-to-length ratio of the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 is W/(8L), and the width-to-length ratio of the second electronic switch M3 is W/L, i.e., the width-to-length ratio of the second electronic switch M3 is eight times of the width-to-length ratio of the conductive PMOS transistor M4, PMOS transistor M5, PMOS transistor M6 and PMOS transistor M7. Therefore, a current IM3 flowing through the second electronic switch M3 is eight times of a current IBG of the variable current source IBG (i.e., the background photocurrent) currently, i.e., IM3=8IBG. When the area of the photodiode PD is doubled, the current of the variable current source IBG is also changed into 2IBG. At the moment, the control switches M8 and M9 may be off, and the control switch M10 is on, so that the PMOS transistor M4 is short-circuited. At the moment, the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 are conductive, the equivalent width-to-length ratio of the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 is W/(4L), the width-to-length ratio of the second electronic switch M3 is four times of the width-to-length ratio of the conductive PMOS transistor M5, PMOS transistor M6 and PMOS transistor M7, and the current IM3 flowing through the second electronic switch M3 is four times of a current of the variable current source IBG 2IBG currently, i.e., IM3=8IBG. Similarly, when the area of the photodiode PD is changed into four times of the original area, the current of the variable current source IBG is also changed into 4IBG, the control switches M8 and M10 may be off and the control switch M9 is on, so that the PMOS transistor M4 and the PMOS transistor M5 are short-circuited. At the moment, the PMOS transistor M6 and the PMOS transistor M7 are conductive, and the equivalent width-to-length ratio of the PMOS transistor M6 and the PMOS transistor M7 is W/(2L). The width-to-length ratio of the second electronic switch M3 is twice of the equivalent width-to-length ratio of the conductive PMOS transistor M6 and PMOS transistor M7, and the current flowing through the second electronic switch M3 IM3 is twice of a current of the variable current source IBG 4IBG currently, i.e., IM3=8IBG. Thus, it can be seen that no matter how the area of the photodiode PD is changed, the current IM3 flowing through the second electronic switch M3 may be always unchanged, by changing the number of the conductive PMOS transistors by controlling on and off of the plurality of control switches and adjusting the equivalent width-to-length ratio of the conductive PMOS transistors.

    [0047] In one aspect, a formula is that 1=(1/2)ucox(W/L)(VGS-VTH), wherein I represents the background photocurrent of the photodiode PD, i.e., the current of the variable current source IBG IBG; ucox is a constant parameter; (W/L) herein represents the equivalent width-to-length ratio of the conductive PMOS transistors; VGS represents a gate-to-source voltage of the plurality of PMOS transistors, and is equal to the voltage U of the capacitor CSH; and VTH represents a threshold voltage of the plurality of PMOS transistors, and is not influenced by the change of the area of the photodiode PD. It can be known from the above formula that: when the area of the photodiode PD is changed, I can be changed with accordingly. In this case, the equivalent width-to-length ratio (W/L) of the conductive PMOS transistors is also changed by changing the number of the conductive PMOS transistors, so that the change of the voltage of the capacitor CSH within a large range can be avoided. Specially, if the equivalent width-to-length ratio (W/L) is changed in the same proportion as the current I is changed, the VGS may be kept unchanged, i.e., the voltage of the capacitor CSH is kept unchanged.

    [0048] In another aspect, when the area of the photodiode is changed, the current IM3 flowing through the second electronic switch M3 is always unchanged by adjusting the equivalent width-to-length ratio of the conductive PMOS transistors, so that the position of the non-dominant pole P2 in the circuit may be kept unchanged. A current in the circuit, which flows through the fourth electronic switch M1, is provided by the first current source IB1 and the second current source IB2; due to that both the first current source IB1 and the second current source IB2 are constant current sources, the current IM1 flowing through the fourth electronic switch M1 also may not be changed. Since IM1 is unchanged, a position of a non-dominant pole P3 (corresponding to a node among the second end of the first current source IB 1 and the first end of the fourth electronic switch M1 and the control end of the fourth electronic switch M1) in the circuit also is changed. In other words, the positions of both the non-dominant poles P2 and P3 in the circuit are not changed. A formula about a gain bandwidth product of the circuit is that GBW=gmAK/CPD, wherein CPD represents a parasitic capacitance of the photodiode, and K represents a ratio of the equivalent width-to-length ratio of the conductive PMOS transistors to the width-to-length ratio of the second electronic switch M3; and gmA represents a transconductance of the amplification circuit 41, and is not influenced by the change of the photodiode PD. As mentioned above, when the area of the photodiode PD is doubled, CPD may also be doubled. In this case, the PMOS transistor M4 is short-circuited, the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 are conductive, and an equivalent channel length of the PMOS transistor M5, the PMOS transistor M6 and the PMOS transistor M7 is reduced by 50%, so that the ratio K of the equivalent width-to-length ratio of the conductive PMOS transistors to the width-to-length ratio of the second electronic switch M3 is also changed to be twice of the original ratio, and GBW is kept unchanged. Similarly, when the area of the photodiode PD is increased by four times, CPD may also be increased by four times. In this case, the PMOS transistor M4 and the PMOS transistor M are short-circuited, the PMOS transistor M6 and the PMOS transistor M7 are conductive. The ratio K of the equivalent width-to-length ratio of the conductive PMOS transistors to the width-to-length ratio of the second electronic switch M3 is also changed to be four times of the original ratio, and GBW is still kept unchanged. Thus it can be seen that when the area of the photodiode PD is changed, the equivalent channel length of the conductive PMOS transistors can be changed in a reversed proportion to the change of the area of the photodiode PD by changing the number of the conductive PMOS transistors (i.e., the equivalent output impedance is in a direct proportion to the equivalent channel length, and thus herein, the equivalent output impedance of the conductive PMOS transistors may also be changed in the reversed proportion to the change of the area of the photodiode), so that the gain bandwidth product of the loop is constant. The positions of the two non-dominant poles P2 and P3 in the loop are kept unchanged, and the gain bandwidth product of the loop is also constant, so that stability of the loop may be not influenced by the change of the area of the photodiode PD.

    [0049] It should be noted that in actual designs, the minimum width-to-length ratio (e.g., the width-to-length ratio of the PMOS transistor M7) may be designed according to the minimum area of the photodiode PD. Moreover, at design time, a certain margin is reserved. For example, a gear with 1 time of area (i.e., the area of the photodiode PD is doubled) is enough for supporting the case where the area of the photodiode PD is changed in a range between 0.5 time and 1.5 times; a gear with 2 times of area (i.e., the area of the photodiode PD is increased by twice) is enough for supporting the case where the area of the photodiode PD is changed in a range between 1.5 times and 2.5 times.

    [0050] When the sampling stage ends, the first sampling switch SW1 and the second sampling switch SW2 may be off, and at the moment, the circuit enters into the integrating stage. The voltage of the capacitor CSH is converted into the current (the value of the current is equal to the value of the background photocurrent sampled previously), and the current is output to the photodiode PD through the conductive PMOS transistors so as to offset the background photocurrent of the photodiode PD.

    [0051] It is worth mentioning that the exemplary embodiment provides the implementation of the first transconductance amplifier OTA1 and the second transconductance amplifier OTA2. But in the practical application, conventional operational transconductance amplifiers may also be directly selected as the first transconductance amplifier OTA1 and the second transconductance amplifier OTA2, and the exemplary embodiment is limited thereto.

    [0052] A fourth exemplary embodiment of this disclosure relates to a sensor. The sensor may be a sensor for detecting a heart rate, and specifically, the sensor may be integrated with the current sample-and-hold circuit as provided by the first exemplary embodiment, the second or the third exemplary embodiments, together with a photodiode. The other end of the first transconductance amplifier OTA1 of the current sample-and-hold circuit may be connected with a cathode of the photodiode, and an anode of the photodiode may be grounded.

    [0053] In addition, alternatively, the sensor may also be integrated with an integrator, and an amplification circuit of the integrator is used as the amplification circuit of the bias circuit in the second exemplary embodiment. Therefore, in a sampling stage, the first sampling switch SW1 is closed, and the amplification circuit of the integrator, as one part of the current sample-and-hold circuit, forms a loop with other parts of the current sample-and-hold circuit. In an integrating stage, after the first sampling switch SW1 is off, the amplification circuit works as one part of the integrator. It is beneficial for implementing multiplexing on the amplification circuit of the integrator.

    [0054] The invention is defined by appended claims 1-8.


    Claims

    1. A current sample-and-hold circuit for offsetting a background photocurrent of a photodiode (PD), applied to sensor comprising a photodiode (PD) and comprising: a capacitor (CSH) and a first transconductance amplifier (OTA1) which is used for outputting a sampled current to the photodiode (PD) to offset the background photocurrent of the photodiode (PD);
    one end of the capacitor (CSH) being connected with a power supply VDD, and the other end of the capacitor (CSH) being connected with one end of the first transconductance amplifier (OTA1); and the other end of the first transconductance amplifier (OTA1) being connected with the photodiode (PD) to output the sampled current to the photodiode (PD); the one end of the first transconductance amplifier (OTA1) refers to an output end, and the other end of the first transconductance amplifier (OTA1) refers to an input end characterized in that: the first transconductance amplifier (OTA1) has adjustable transconductance;
    the
    first transconductance amplifier (OTA1) comprises a plurality of first electronic switches (M4, M5, M6, M7) and a plurality of control switches (M8, M9, M10) for controlling the first electronic switches (M4, M5, M6, M7);
    the plurality of first electronic switches (M4, M5, M6, M7) are connected between the power supply VDD and the photodiode (PD), the plurality of first electronic switches (M4, M5, M6, M7) are connected in series, and control ends of the plurality of first electronic switches (M4, M5, M6, M7) are all connected with the other end of the capacitor (CSH); and
    a junction between any two adjacent first electronic switches (M4, M5, M6, M7) corresponds to one control switch (M8, M9, M10), one end of each control switch (M8, M9, M10) is connected with the power supply VDD, and the other end of each control switch (M8, M9, M10) is connected with a corresponding junction.
     
    2. The current sample-and-hold circuit according to claim 1, characterized by further comprising a first sampling switch (SW1) and a bias circuit (31) for providing a bias voltage to the first transconductance amplifier (OTA1);
    a first end of the bias circuit (31) being simultaneously connected with one end of the first transconductance amplifier (OTA1) and the other end of the capacitor (CSH) through the first sampling switch (SW1); a second end of the bias circuit (31) being connected with the power supply VDD; and a third end of the bias circuit (31) being connected with the photodiode (PD).
     
    3. The current sample-and-hold circuit according to claim 2, characterized in that the bias circuit (31) comprises a second electronic switch (M3) and a second transconductance amplifier (OTA2);
    a first end of the second electronic switch (M3), as the second end of the bias circuit (31), is connected with the power supply VDD; a second end of the second electronic switch (M3) is connected with one end of the second transconductance amplifier (OTA2); a control end of the second electronic switch (M3), as the first end of the bias circuit (31), is connected with the first sampling switch (SW1) as well as a junction between the second end of the second electronic switch (M3) and one end of the second transconductance amplifier (OTA2); and the other end of the second transconductance amplifier (OTA2), as the third end of the bias circuit (31), is connected with the photodiode (PD).
     
    4. The current sample-and-hold circuit according to claim 3, characterized in that the second transconductance amplifier (OTA2) comprises a second sampling switch (SW2), an amplification circuit (41), a first current source (IB1), a third electronic switch (M2) and a fourth electronic switch (M1);
    a first end of the third electronic switch (M2) is connected with the second end of the second electronic switch (M3); a second end of the third electronic switch (M2) is grounded; a control end of the third electronic switch (M2) is connected with a junction between a second end of the first current source (IB1) and a first end of the fourth electronic switch (M1) as well as a control end of the fourth electronic switch (M1); a first end of the first current source (IB1) is connected with the power supply VDD;
    the first end of the fourth electronic switch (M1) is also connected with one end of the amplification circuit (41) through the second sampling switch (SW2); a second end of the fourth electronic switch (M1) is grounded; and the other end of the amplification circuit (41) is connected with the photodiode (PD).
     
    5. The current sample-and-hold circuit according to claim 4, characterized in that the amplification circuit (41) comprises a second current source (IB2) and a fifth electronic switch (MA);
    a first end of the fifth electronic switch (MA), as one end of the amplification circuit (41), is respectively connected with the second current source (IB2) and the second sampling switch (SW2); a second end of the fifth electronic switch (MA) is grounded; and a control end of the fifth electronic switch (MA), as the other end of the amplification circuit (41), is connected with the photodiode (PD).
     
    6. The current sample-and-hold circuit according to claim 5, characterized in that the first electronic switches are PMOS transistors; a plurality of PMOS transistors are sequentially arranged towards the photodiode (PD);
    a first PMOS transistor of the plurality of PMOS transistors refers to a PMOS transistor the closest to the photodiode (PD), and a last PMOS transistor refers to a PMOS transistor the furthest away from the photodiode (PD); a width-to-length ratio of the first PMOS transistor is equal to that of a second PMOS transistor, a width-to-length ratio of an ith PMOS transistor is twice of a width-to-length ratio of a (i-1)th PMOS transistor, and the i is greater than or equal to 3.
     
    7. The current sample-and-hold circuit according to claim 3, characterized in that the second electronic switch (M3) is a PMOS transistor, and a width-to-length ratio of the second electronic switch (M3) is equal to that of the first PMOS transistor.
     
    8. The current sample-and-hold circuit according to claim 1, characterized by further comprising a third sampling switch (SW3); the third sampling switch (SW3) being connected in parallel to the capacitor (CSH).
     


    Ansprüche

    1. Strom-Abtast-Halte-Schaltung zum Ausgleichen eines Hintergrundphotostroms einer Photodiode (PD), der an einen Sensor mit einer Photodiode (PD) angelegt wird, umfassend:

    einen Kondensator (CSH) und einen ersten Transkonduktanzverstärker (OTA1), der zum Ausgeben eines abgetasteten Stroms an die Photodiode (PD) verwendet wird, um den Hintergrundphotostrom der Photodiode (PD) auszugleichen;

    wobei ein Ende des Kondensators (CSH) mit einer Spannungsversorgung VDD verbunden ist und das andere Ende des Kondensators (CSH) mit einem Ende des ersten Transkonduktanzverstärkers (OTA1) verbunden ist; und das andere Ende des ersten Transkonduktanzverstärkers (OTA1) mit der Photodiode (PD) verbunden ist, um den abgetasteten Strom an die Photodiode (PD) auszugeben; wobei sich das eine Ende des ersten Transkonduktanzverstärkers (OTA1) auf ein Ausgangsende bezieht, und sich das andere Ende des ersten Transkonduktanzverstärkers (OTA1) auf ein Eingangsende bezieht,

    dadurch gekennzeichnet, dass:

    der erste Transkonduktanzverstärker (OTA1) eine einstellbare Transkonduktanz aufweist;

    der erste Transkonduktanzverstärker (OTA1) mehrere erste elektronische Schalter (M4, M5, M6, M7) und mehrere Steuerschalter (M8, M9, M10) zum Steuern der ersten elektronischen Schalter (M4, M5, M6, M7) aufweist;

    die mehreren ersten elektronischen Schalter (M4, M5, M6, M7) zwischen die Spannungsversorgung VDD und die Photodiode (PD) geschaltet sind, die mehreren ersten elektronischen Schalter (M4, M5, M6, M7) in Reihe geschaltet sind, und die Steuerenden der mehreren ersten elektronischen Schalter (M4, M5, M6, M7) alle mit dem anderen Ende des Kondensators (CSH) verbunden sind; und

    eine Verbindungsstelle zwischen zwei beliebigen benachbarten ersten elektronischen Schaltern (M4, M5, M6, M7) mit einem Steuerschalter (M8, M9, M10) korrespondiert, wobei ein Ende jedes Steuerschalters (M8, M9, M10) mit der Spannungsversorgung VDD verbunden ist und das andere Ende jedes Steuerschalters (M8, M9, M10) mit einer korrespondierenden Verbindungsstelle verbunden ist.


     
    2. Strom-Abtast-Halte-Schaltung nach Anspruch 1, dadurch gekennzeichnet, dass sie ferner einen ersten Abtastschalter (SW1) und eine Vorspannungsschaltung (31) zur Bereitstellung einer Vorspannung für den ersten Transkonduktanzverstärker (OTA1) umfasst;
    wobei ein erstes Ende der Vorspannungsschaltung (31) über den ersten Abtastschalter (SW1) gleichzeitig mit einem Ende des ersten Transkonduktanzverstärkers (OTA1) und dem anderen Ende des Kondensators (CSH) verbunden ist; ein zweites Ende der Vorspannungsschaltung (31) mit der Spannungsversorgung VDD verbunden ist; und ein drittes Ende der Vorspannungsschaltung (31) mit der Photodiode (PD) verbunden ist.
     
    3. Strom-Abtast-Halte-Schaltung nach Anspruch 2, dadurch gekennzeichnet, dass die Vorspannungsschaltung (31) einen zweiten elektronischen Schalter (M3) und einen zweiten Transkonduktanzverstärker (OTA2) umfasst;
    wobei ein erstes Ende des zweiten elektronischen Schalters (M3) als das zweite Ende der Vorspannungsschaltung (31) mit der Spannungsversorgung VDD verbunden ist; ein zweites Ende des zweiten elektronischen Schalters (M3) mit einem Ende des zweiten Transkonduktanzverstärkers (OTA2) verbunden ist; ein Steuerende des zweiten elektronischen Schalters (M3) als das erste Ende der Vorspannungsschaltung (31) mit dem ersten Abtastschalter (SW1) sowie einer Verbindungsstelle zwischen dem zweiten Ende des zweiten elektronischen Schalters (M3) und einem Ende des zweiten Transkonduktanzverstärkers (OTA2) verbunden ist; und das andere Ende des zweiten Transkonduktanzverstärkers (OTA2) als das dritte Ende der Vorspannungsschaltung (31) mit der Photodiode (PD) verbunden ist.
     
    4. Strom-Abtast-Halte-Schaltung nach Anspruch 3, dadurch gekennzeichnet, dass der zweite Transkonduktanzverstärker (OTA2) einen zweiten Abtastschalter (SW2), eine Verstärkungsschaltung (41), eine erste Stromquelle (IB1), einen dritten elektronischen Schalter (M2) und einen vierten elektronischen Schalter (M1) umfasst;
    wobei ein erstes Ende des dritten elektronischen Schalters (M2) mit dem zweiten Ende des zweiten elektronischen Schalters (M3) verbunden ist; ein zweites Ende des dritten elektronischen Schalters (M2) geerdet ist; ein Steuerende des dritten elektronischen Schalters (M2) mit einer Verbindungsstelle zwischen einem zweiten Ende der ersten Stromquelle (IB1) und einem ersten Ende des vierten elektronischen Schalters (M1) sowie einem Steuerende des vierten elektronischen Schalters (M1) verbunden ist; ein erstes Ende der ersten Stromquelle (IB1) mit der Spannungsversorgung VDD verbunden ist;
    wobei das erste Ende des vierten elektronischen Schalters (M1) über den zweiten Abtastschalter (SW2) auch mit einem Ende der Verstärkungsschaltung (41) verbunden ist; ein zweites Ende des vierten elektronischen Schalters (M1) geerdet ist; und das andere Ende der Verstärkungsschaltung (41) mit der Photodiode (PD) verbunden ist.
     
    5. Strom-Abtast-Halte-Schaltung nach Anspruch 4, dadurch gekennzeichnet, dass die Verstärkungsschaltung (41) eine zweite Stromquelle (IB2) und einen fünften elektronischen Schalter (MA) umfasst;
    wobei ein erstes Ende des fünften elektronischen Schalters (MA) als ein Ende der Verstärkungsschaltung (41) jeweils mit der zweiten Stromquelle (IB2) und dem zweiten Abtastschalter (SW2) verbunden ist; ein zweites Ende des fünften elektronischen Schalters (MA) geerdet ist; und ein Steuerende des fünften elektronischen Schalters (MA) als das andere Ende der Verstärkungsschaltung (41) mit der Photodiode (PD) verbunden ist.
     
    6. Strom-Abtast-Halte-Schaltung nach Anspruch 5, dadurch gekennzeichnet, dass die ersten elektronischen Schalter PMOS-Transistoren sind; wobei mehrere PMOS-Transistoren sequentiell in Richtung zu der Photodiode (PD) angeordnet sind;
    wobei ein erster PMOS-Transistor der mehreren PMOS-Transistoren sich auf einen PMOS-Transistor bezieht, der der Photodiode (PD) am nächsten ist, und ein letzter PMOS-Transistor sich auf einen PMOS-Transistor bezieht, der am weitesten von der Photodiode (PD) entfernt ist; ein Breite-Länge-Verhältnis des ersten PMOS-Transistors gleich demjenigen eines zweiten PMOS-Transistors ist, ein Breite-Länge-Verhältnis eines i-ten PMOS-Transistors zweimal so groß ist wie ein Breite-Länge-Verhältnis eines (i-1)-ten PMOS-Transistors, wobei i größer oder gleich 3 ist.
     
    7. Strom-Abtast-Halte-Schaltung nach Anspruch 3, dadurch gekennzeichnet, dass der zweite elektronische Schalter (M3) ein PMOS-Transistor ist und ein Breite-Länge-Verhältnis des zweiten elektronischen Schalters (M3) gleich demjenigen des ersten PMOS-Transistors ist.
     
    8. Strom-Abtast-Halte-Schaltung nach Anspruch 1, dadurch gekennzeichnet, dass sie ferner einen dritten Abtastschalter (SW3) umfasst; wobei der dritte Abtastschalter (SW3) parallel zu dem Kondensator (CSH) geschaltet ist.
     


    Revendications

    1. Circuit échantillonneur-bloqueur de courant pour compenser un courant photoélectrique de fond d'une photodiode (PD), appliqué à un capteur comprenant une photodiode (PD), et comprenant : un condensateur (CSH) et un premier amplificateur de transconductance (OTA1) qui est utilisé pour fournir en sortie un courant échantillonné à la photodiode (PD) afin de compenser le courant photoélectrique de fond de la photodiode (PD) ;
    une extrémité du condensateur (CSH) étant connectée à une alimentation électrique VDD, et l'autre extrémité du condensateur (CSH) étant connectée à une extrémité du premier amplificateur de transconductance (OTA1) ; et l'autre extrémité du premier amplificateur de transconductance (OTA1) étant connectée à la photodiode (PD) en vue de fournir en sortie le courant échantillonné à la photodiode (PD) ; ladite une extrémité du premier amplificateur de transconductance (OTA1) fait référence à une extrémité de sortie, et l'autre extrémité du premier amplificateur de transconductance (OTA1) fait référence à une extrémité d'entrée ;
    caractérisé en ce que : le premier amplificateur de transconductance (OTA1) présente une transconductance réglable ;
    le premier amplificateur de transconductance (OTA1) comprend une pluralité de premiers commutateurs électroniques (M4, M5, M6, M7) et une pluralité de commutateurs de commande (M8, M9, M10) pour commander les premiers commutateurs électroniques (M4, M5, M6, M7) ;
    les commutateurs de la pluralité de premiers commutateurs électroniques (M4, M5, M6, M7) sont connectés entre l'alimentation électrique VDD et la photodiode (PD), la pluralité de premiers commutateurs électroniques (M4, M5, M6, M7) sont connectés en série, et les extrémités de commande de la pluralité de premiers commutateurs électroniques (M4, M5, M6, M7) sont toutes connectées aux autres extrémités respectives du condensateur (CSH) ; et
    une jonction entre deux quelconques premiers commutateurs électroniques adjacents (M4, M5, M6, M7) correspond à un commutateur de commande (M8, M9, M10), une extrémité de chaque commutateur de commande (M8, M9, M10) est connectée à l'alimentation électrique VDD, et l'autre extrémité de chaque commutateur de commande (M8, M9, M10) est connectée à une jonction correspondante.
     
    2. Circuit échantillonneur-bloqueur de courant selon la revendication 1, caractérisé en ce qu'il comprend en outre un premier commutateur d'échantillonnage (SW1) et un circuit de polarisation (31) pour fournir une tension de polarisation au premier amplificateur de transconductance (OTA1) ;
    une première extrémité du circuit de polarisation (31) étant simultanément connectée à une extrémité du premier amplificateur de transconductance (OTA1) et à l'autre extrémité du condensateur (CSH) par l'intermédiaire du premier commutateur d'échantillonnage (SW1) ; une deuxième extrémité du circuit de polarisation (31) étant connectée à l'alimentation électrique VDD ; et une troisième extrémité du circuit de polarisation (31) étant connectée à la photodiode (PD).
     
    3. Circuit échantillonneur-bloqueur de courant selon la revendication 2, caractérisé en ce que le circuit de polarisation (31) comprend un deuxième commutateur électronique (M3) et un second amplificateur de transconductance (OTA2) ;
    une première extrémité du deuxième commutateur électronique (M3), en tant que la deuxième extrémité du circuit de polarisation (31), est connectée à l'alimentation électrique VDD ; une deuxième extrémité du deuxième commutateur électronique (M3) est connectée à une extrémité du second amplificateur de transconductance (OTA2) ; une extrémité de commande du deuxième commutateur électronique (M3), en tant que la première extrémité du circuit de polarisation (31), est connectée au premier commutateur d'échantillonnage (SW1) ainsi qu'à une jonction entre la deuxième extrémité du deuxième commutateur électronique (M3) et une extrémité du second amplificateur de transconductance (OTA2) ; et l'autre extrémité du second amplificateur de transconductance (OTA2), en tant que la troisième extrémité du circuit de polarisation (31), est connectée à la photodiode (PD).
     
    4. Circuit échantillonneur-bloqueur de courant selon la revendication 3, caractérisé en ce que le second amplificateur de transconductance (OTA2) comprend un deuxième commutateur d'échantillonnage (SW2), un circuit d'amplification (41), une première source de courant (IB1), un troisième commutateur électronique (M2) et un quatrième commutateur électronique (M1) ;
    une première extrémité du troisième commutateur électronique (M2) est connectée à la deuxième extrémité du deuxième commutateur électronique (M3) ; une deuxième extrémité du troisième commutateur électronique (M2) est mise à la masse ; une extrémité de commande du troisième commutateur électronique (M2) est connectée à une jonction entre une deuxième extrémité de la première source de courant (IB1) et une première extrémité du quatrième commutateur électronique (M1), ainsi qu'une extrémité de commande du quatrième commutateur électronique (M1) ; une première extrémité de la première source de courant (IB1) est connectée à l'alimentation électrique VDD ; et
    la première extrémité du quatrième commutateur électronique (M1) est également connectée à une extrémité du circuit d'amplification (41) par l'intermédiaire du deuxième commutateur d'échantillonnage (SW2) ; une deuxième extrémité du quatrième commutateur électronique (M1) est mise à la masse ; et l'autre extrémité du circuit d'amplification (41) est connectée à la photodiode (PD).
     
    5. Circuit échantillonneur-bloqueur de courant selon la revendication 4, caractérisé en ce que le circuit d'amplification (41) comprend une seconde source de courant (IB2) et un cinquième commutateur électronique (MA) ;
    une première extrémité du cinquième commutateur électronique (MA), en tant qu'une extrémité du circuit d'amplification (41), est respectivement connectée à la seconde source de courant (IB2) et au deuxième commutateur d'échantillonnage (SW2) ; une deuxième extrémité du cinquième commutateur électronique (MA) est mise à la masse ; et une extrémité de commande du cinquième commutateur électronique (MA), en tant que l'autre extrémité du circuit d'amplification (41), est connectée à la photodiode (PD).
     
    6. Circuit échantillonneur-bloqueur de courant selon la revendication 5, caractérisé en ce que les premiers commutateurs électroniques sont des transistors PMOS ; une pluralité de transistors PMOS sont agencés séquentiellement vers la photodiode (PD) ;
    un premier transistor PMOS de la pluralité de transistors PMOS fait référence à un transistor PMOS le plus proche de la photodiode (PD), et un dernier transistor PMOS fait référence à un transistor PMOS le plus éloigné de la photodiode (PD) ; un rapport largeur/longueur du premier transistor PMOS est identique à celui d'un second transistor PMOS, un rapport largeur/longueur d'un ième transistor PMOS est égal au double d'un rapport largeur/longueur d'un (i-1)ème transistor PMOS, et dans lequel « i » est supérieur ou égal à 3.
     
    7. Circuit échantillonneur-bloqueur de courant selon la revendication 3, caractérisé en ce que le deuxième commutateur électronique (M3) est un transistor PMOS, et un rapport largeur/longueur du deuxième commutateur électronique (M3) est identique à celui du premier transistor PMOS.
     
    8. Circuit échantillonneur-bloqueur de courant selon la revendication 1, caractérisé en ce qu'il comprend en outre un troisième commutateur d'échantillonnage (SW3) ; le troisième commutateur d'échantillonnage (SW3) étant connecté en parallèle au condensateur (CSH).
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description