 (11)  EP 3 537 675 A1 
(12)  EUROPEAN PATENT APPLICATION 
published in accordance with Art. 153(4) EPC 



 
(54)  METHOD FOR DEMODULATING FREQUENCY MODULATION SIGNAL OF PMA STANDARD WIRELESS CHARGING DEVICE 
(57) The present disclosure relates to a method for demodulating a frequency modulated signal of a PMA standard wireless charging device, including: (1) reading coil signals, sampling the coil signals, and counting cycles; (2) extracting a frequency change according to a change in a cycle count; (3) determining data according to the frequency change and a frequency duration and outputting the data; and (4) splicing the outputted data. With the method, a demodulation part does not require a complex analog circuit, and the highest frequency desired at a digital circuit part is only 4 MHz. Moreover, at this frequency, there is only a simple addition operation, and the main operating frequency is below 236 KHz. Compared with an existing FSK decoding method, the method is more compatible with a PMA standard frequency modulated signal, low in costs, high in demodulation speed, easy to adjust and high in accuracy, has no requirement for a fixed Fop, and can be widely applied. 
CROSSREFERENCE TO RELATED APPLICATIONS
TECHNICAL FIELD
BACKGROUND
SUMMARY
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a schematic diagram of a conventional FSK signal data transmission manner.
FIG. 2 is a schematic diagram of a process of a method for demodulating a frequency modulated signal of a PMA standard wireless charging device according to the present disclosure.
FIG. 3 is a flowchart of a data acquisition process of a method for demodulating a frequency modulated signal of a PMA standard wireless charging device according to the present disclosure.
FIG. 4 is a flowchart of extracting a frequency change of a method for demodulating a frequency modulated signal of a PMA standard wireless charging device according to the present disclosure.
FIG. 5 is a flowchart of data determination of a method for demodulating a frequency modulated signal of a wireless charging device according to the present disclosure.
DESCRIPTION OF EMBODIMENTS
(11) receiving the coil signals and comparing the coil signals with 0 level by a comparator;
(12) reading an outputted value of the comparator at a frequency of 4 MHz;
(13) filtering out a jitter waveform with a higher frequency in the outputted value of the comparator; and
(14) counting the cycles by a cycle counter.
(141) determining whether the filtered outputted value of the comparator changes from 0 to 1 , and if yes, proceeding to step (142); otherwise, proceeding to step (143);
(142) outputting a count value of the cycle counter, clearing the count value, and proceeding to step (11); and
(143) incrementing the count value of the cycle counter by 1, and proceeding to step (11) .
(21) calculating a sum of numbers of sampling points in latest 24 cycles according to a count value of the latest cycle;
(22) filtering the sum of the numbers of the sampling points in the 24 cycles, and eliminating frequency jitter caused by sampling;
(23) counting Fop points;
(24) calculating sum_delta by the following formula:
where sum_delta is a differential result between the filtered outputted value and a currently determined Fop value sum_Fop, out_IIR is the filtered outputted value, and sum_Fop is a count value of the Fop points; and
(25) eliminating the frequency jitter, modifying the waveform and outputting the modified waveform.
(211) determining whether the cycle counter has an outputted value, and if yes, proceeding to step (212);
(212) calculating the sum of the numbers of the sampling points in the 24 cycles according to the following formula:
where SumTbuff is the sum of the numbers of the sampling points, T_counter is the count value of the cycle counter, Tbuffer[23] is a 24th cached value of a buffer Tbuffer, and the buffer Tbuffer is used to store the outputted value of the cycle counter T_counter, the buffer Tbuffer has a depth of 24 and follows a principle of first in first out; and
(212) updating the buffer Tbuffer.
(231) determining whether delta is 0, and if yes, proceeding to step (233), otherwise, proceeding to step (232), wherein delta is the differential result of the filtered outputted value ;
(232) clearing Count_delta, wherein Count_delta is a count value when delta is 0, and proceeding to step (234);
(233) incrementing Count_delta by 1 and proceeding to step (234);
(234) determining whether Count_delta is greater than a first constant, and if yes, proceeding to step (235); and
(235) clearing Count_delta, clearing Count_SumDiv4, taking a value of out_IIR as sum_Fop, and proceeding to step (24), wherein Count_SumDiv4 is a count value of SumDiv4, and SumDiv4 is a value obtained by right shifting the filtered outputted value by two bits.
(23a) determining whether a current SumDiv4 is equal to a previous SumDiv4, and if yes, proceeding to step (23b), otherwise, proceeding to step (23c);
(23b) incrementing Count_SumDiv4 by 1 and proceeding to step (23d);
(23c) clearing Count_SumDiv4 and proceeding to step (23d);
(23d) using the current SumDiv4 to cover the previous SumDiv4;
(23e) determining whether Count_SumDiv4 is greater than or equal to a second constant and whether an absolute value of sum_delta is greater than a third constant, and if yes, proceeding to step (23f); and
(23f) clearing Count_SumDiv4, taking the value of out_IIR as sum_Fop, and proceeding to step (24).
(251) determining whether an absolute value of sum_delta is smaller than or equal to a fourth constant, and if yes, proceeding to step (252), otherwise, proceeding to step (253);
(252) taking clip_sum_delta= 0 as a modified sum_delta, and proceeding to step (254);
(253) modifying sum_delta in a section smaller than the fourth constant, and proceeding to step (254); and
(254) outputting data of the modified sum_delta.
(2531) determining whether the absolute value of sum_delta is greater than 31, and if yes, proceeding to step (2532), otherwise, proceeding to step (2535);
(2532) determining whether sum_delta is greater than 0, and if yes, proceeding to step (2533), otherwise, proceeding to step (2534);
(2533) taking clip_sum_delta=31 as the modified sum_delta, and proceeding to step (254);
(2534) taking clip_sum_delta= 31 as the modified sum_delta, and proceeding to step (254); and
(2535) directly taking the value of sum_delta as clip_sum_delta, and proceeding to step (254).
(31) determining whether clip_sum_delta changes between zero and a nonzero value, and if yes, proceeding to step (32);
(32) adding a value of clk_count to a value of reg_clk_count to obtain a new reg_clk_count, and clearing clk_count, where reg_clk_count is an accumulated value of a 4MHz clock counter, and clk_count is a count value of the 4MHz clock counter;
(33) performing data determination on reg_clk_count to obtain data_bit;
(34) outputting data according to data_bit; and
(35) outputting data, saving a latest bit_salve, and proceeding to step (4), wherein the outputted data is 0 or 1, bit_salve is a saved value of the data determination, and the saved value of the data determination is used to save a condition of a latest determined half cycle.
(331) determining whether reg_clk_count is greater than or equal to a threshold value a, and if yes, proceeding to step (332), otherwise, proceeding to step (333);
(332) clearing reg_clk_count, outputting a data determination result as data_bit = 8, and proceeding to step (4);
(333) determining whether clip_sum_delta changes from a nonzero value to zero, and if yes, proceeding to step (333), otherwise, proceeding to step (338);
(334) determining whether reg_clk_count is greater than the threshold value a, and if yes, proceeding to step (335), otherwise, proceeding to step (336);
(335) skipping the determination and proceeding to step (34);
(336) determining whether bit_salve is equal to 3, and if yes, recording the data determination result as case a, otherwise, recording the data determination result as case b;
(337) subtracting a threshold value b from a value of reg_clk_count to obtain a new reg_clk_count, and proceeding to step (34);
(338) determining whether reg_clk_count is smaller than a threshold value e, and if yes, recording the data determination result as case c and proceeding to step (339), otherwise, proceeding to step (3310);
(339) clearing reg_clk_count, and proceeding to step (34);
(3310) determining whether reg_clk_count is smaller than a threshold value d, and if yes, proceeding to step (3311), otherwise, proceeding to step (3312);
(3311) determining whether bit_salve is equal to 2, and if yes, recording the data determination result as case d, otherwise, recording the data determination result as case e, and proceeding to step (339);
(3312) determining whether reg_clk_count is smaller than a threshold value c, and if yes, proceeding to step (3313), otherwise, proceeding to step (3315);
(3313) determining whether bit_salve is equal to 2, and if yes, recording the data determination result as case f and proceeding to step (339), otherwise, proceeding to step (3314);
(3314) determining whether bit_salve is equal to 3, and if yes, recording the data determination result as case g, otherwise, recording the data determination result as case h, and proceeding to the step (339);
(3315) determining whether reg_clk_count is smaller than the threshold value b, and if yes, proceeding to step (3316), otherwise, recording the data determination result as case j and proceeding to the step (339) ;
(3316) determining whether bit_salve is equal to 2, and if yes, recording the data determination result as case j and proceeding to the step (339), otherwise, proceeding to step (3317); and
(3317) determining whether bit_salve is equal to 3, and if yes, recording the data determination result as case k, otherwise, recording the data determination result as case 1, and proceeding to the step (339).
(341) determining whether data_bit is equal to 8, and if yes, proceeding to step (342), otherwise, proceeding to step (343);
(342) clearing reg_clk_count;
(343) determining a value of data_bit; and
(344) ascertaining the outputted data according to the value of data_bit, saving a latest bit_salve, the outputted data being 0 or 1, and proceeding to step (4).
const1, const2, const3, const4  constants involved in the algorithm;
Tbuffer   a cycle count buffer, which is used for saving an outputted value of T_counter has a depth of 23, first in first out;
SumTbuff   a sum of members of the cycle count buffer, 15bit, having an initial value of 0;
delta   a differential result of outputted values by LPF2;
Count_delta   a counter when a delta value is 0, which accumulates when delta is 0 and clears when there is a change;
sum_delta   a difference between the sum values, indicating a difference between a value currently outputted by the filter and a current Fop value; and
clip_sum_delta   modified sum_delta data.
const_a, const_b, const_c, const_d, const_e   threshold values of a 4MHz clock counter involved in the algorithm;
clip_sum_delta   an output of a cycle point number processing module;
clk_count   a 4MHz clock counter;
reg_clk_count   an output register of a 4MHz counter;
data_bit   0 indicating that 0 is detected, 1 indicating that 1 is detected, 2 indicating that fop + fmod + fop is detected, 3 indicating that fmod + fop + fop is detected, 4 indicating that fop + fmod + fop is detected, 5 indicating that fmod + fop +long fop is detected, 6 indicating that fop+fmod+long fop is detected, 7 indicating that the processing is suspending, and 8 indicating that an error is detected; and
bit_salve   a data determination saving value for saving the latest determined half cycle, 2 indicating fop, 3 indicating fmod, and 0 and 1 indicating that the previous data has been determined.
(1) reading coil signals, sampling the coil signals, and counting cycles;
(2) extracting a frequency change according to a change in a cycle count;
(3) determining data according to the frequency change and a frequency duration and outputting the data; and
(4) splicing the outputted data.
(11) receiving the coil signals and comparing the coil signals with 0 level by a comparator;
(12) reading an outputted value of the comparator at a frequency of 4 MHz;
(13) filtering out a jitter waveform with a higher frequency in the outputted value of the comparator; and
(14) counting the cycles by a cycle counter.
(141) determining whether the filtered outputted value of the comparator changes from 0 to 1, and if yes, proceeding to step (142); otherwise, proceeding to step (143);
(142) outputting a count value of the cycle counter, clearing the count value, and proceeding to step (11); and
(143) incrementing the count value of the cycle counter by 1, and proceeding to step (11).
(21) calculating a sum of numbers of sampling points in latest 24 cycles according to a count value of the latest cycle;
(22) filtering the sum of the numbers of the sampling points in the 24 cycles, and eliminating frequency jitter caused by sampling;
(23) counting Fop points;
(24) calculating sum_delta by the following formula:
where sum_delta is a differential result between the filtered outputted value and a currently determined Fop value sum_Fop, out_IIR is the filtered outputted value, and sum_Fop is a count value of the Fop points; and
(25) eliminating the frequency jitter, modifying the waveform and outputting the modified waveform.
(211) determining whether the cycle counter has an outputted value, and if yes, proceeding to step (212);
(212) calculating the sum of the numbers of the sampling points in the 24 cycles according to the following formula:
where SumTbuff is the sum of the numbers of the sampling points, T_counter is the count value of the cycle counter, Tbuffer[23] is a 24^{th} cached value of a buffer Tbuffer, and the buffer Tbuffer is used to store the outputted value of the cycle counter T_counter, the buffer Tbuffer has a depth of 24 and follows a principle of first in first out; and
(212) updating the buffer Tbuffer.
(231) determining whether delta is 0, and if yes, proceeding to step (233), otherwise, proceeding to step (232), wherein delta is a differential result of the filtered outputted value;
(232) clearing Count_delta, wherein Count_delta is a count value when delta is 0, and proceeding to step (234);
(233) incrementing Count_delta by 1 and proceeding to step (234);
(234) determining whether Count_delta is greater than a first constant, and if yes, proceeding to step (235); and
(235) clearing Count_delta, clearing Count_SumDiv4, taking a value of out_IIR as sum_Fop, and proceeding to step (24), where Count_SumDiv4 is a count value of SumDiv4, and SumDiv4 is a value obtained by right shifting the filtered outputted value by two bits,
wherein said executing a Fop point counting operation based on a right shifting method specifically comprises following steps:(23a) determining whether a current SumDiv4 is equal to a previous SumDiv4, and if yes, proceeding to step (23b), otherwise, proceeding to step (23c);
(23b) incrementing Count_SumDiv4 by 1 and proceeding to step (23d);
(23c) clearing Count_SumDiv4 and proceeding to step (23d);
(23d) using the current SumDiv4 to cover the previous SumDiv4;
(23e) determining whether Count_SumDiv4 is greater than or equal to a second constant and whether an absolute value of sum_delta is greater than a third constant, and if yes, proceeding to step (23f); and
(23f) clearing Count_SumDiv4, taking the value of out_IIR as sum_Fop, and proceeding to step (24).
(251) determining whether an absolute value of sum_delta is smaller than or equal to a fourth constant, and if yes, proceeding to step (252), otherwise, proceeding to step (253);
(252) taking clip_sum_delta= 0 as a modified sum_delta, and proceeding to step (254);
(253) modifying sum_delta in a section smaller than the fourth constant, and proceeding to step (254); and
(254) outputting data of the modified sum_delta.
(2531) determining whether the absolute value of sum_delta is greater than 31, and if yes, proceeding to step (2532), otherwise, proceeding to step (2535);
(2532) determining whether sum_delta is greater than 0, and if yes, proceeding to step (2533), otherwise, proceeding to step (2534);
(2533) taking clip_sum_delta=31 as the modified sum_delta, and proceeding to step (254);
(2534) taking clip_sum_delta= 31 as the modified sum_delta, and proceeding to step (254); and
(2535) directly taking the value of sum_delta as clip_sum_delta, and proceeding to step (254).
(31) determining whether clip_sum_delta changes between zero and a nonzero value, and if yes, proceeding to step (32);
(32) adding a value of clk_count to a value of reg_clk_count to obtain a new reg_clk_count, and clearing clk_count, where reg_clk_count is an accumulated value of a 4MHz clock counter, and clk_count is a count value of the 4MHz clock counter;
(33) performing data determination on reg_clk_count to obtain data_bit;
(34) outputting data according to data_bit; and
(35) outputting data, saving a latest bit_salve, and proceeding to step (4), wherein the outputted data is 0 or 1, bit_salve is a saved value of the data determination, and the saved value of the data determination is used to save a condition of a latest determined half cycle.
(331) determining whether reg_clk_count is greater than or equal to a threshold value a, and if yes, proceeding to step (332), otherwise, proceeding to step (333);
(332) clearing reg_clk_count, outputting a data determination result as data_bit = 8, and proceeding to step (4);
(333) determining whether clip_sum_delta changes from a nonzero value to zero, and if yes, proceeding to step (333), otherwise, proceeding to step (338);
(334) determining whether reg_clk_count is greater than a threshold value a, and if yes, proceeding to step (335), otherwise, proceeding to step (336);
(335) skipping the determination and proceeding to step (34);
(336) determining whether bit_salve is equal to 3, and if yes, recording the data determination result as case a, otherwise, recording the data determination result as case b;
(337) subtracting a threshold value b from a value of reg_clk_count to obtain a new reg_clk_count, and proceeding to step (34);
(338) determining whether reg_clk_count is smaller than a threshold value e, and if yes, recording the data determination result as case c and proceeding to step (339), otherwise, proceeding to step (3310);
(339) clearing reg_clk_count, and proceeding to step (34);
(3310) determining whether reg_clk_count is smaller than a threshold value d, and if yes, proceeding to step (3311), otherwise, proceeding to step (3312);
(3311) determining whether bit_salve is equal to 2, and if yes, recording the data determination result as case d, otherwise, recording the data determination result as case e, and proceeding to step (339);
(3312) determining whether reg_clk_count is smaller than a threshold value c, and if yes, proceeding to step (3313), otherwise, proceeding to step (3315);
(3313) determining whether bit_salve is equal to 2, and if yes, recording the data determination result as case f and proceeding to step (339), otherwise, proceeding to step (3314);
(3314) determining whether bit_salve is equal to 3, and if yes, recording the data determination result as case g, otherwise, recording the data determination result as case h, and proceeding to the step (339);
(3315) determining whether reg_clk_count is smaller than the threshold value b, and if yes, proceeding to step (3316), otherwise, recording the data determination result as case j and proceeding to the step (339) ;
(3316) determining whether bit_salve is equal to 2, and if yes, recording the data determination result as case j and proceeding to the step (339), otherwise, proceeding to step (3317); and
(3317) determining whether bit_salve is equal to 3, and if yes, recording the data determination result as case k, otherwise, recording the data determination result as case 1, and proceeding to the step (339).
(341) determining whether data_bit is equal to 8, and if yes, proceeding to step (342), otherwise, proceeding to step (343);
(342) clearing reg_clk_count;
(343) determining a value of data_bit; and
(344) ascertaining the outputted data according to the value of data_bit, saving a latest bit_salve, the outputted data being 0 or 1, and proceeding to step (4).
REFERENCES CITED IN THE DESCRIPTION
Patent documents cited in the description