(19)
(11)EP 3 577 767 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
21.10.2020 Bulletin 2020/43

(21)Application number: 18705985.2

(22)Date of filing:  05.02.2018
(51)International Patent Classification (IPC): 
H03M 13/13(2006.01)
(86)International application number:
PCT/IB2018/050719
(87)International publication number:
WO 2018/142367 (09.08.2018 Gazette  2018/32)

(54)

ALTERATION OF SUCCESSIVE CANCELLATION ORDER IN DECODING OF POLAR CODES

ÄNDERUNG DER REIHENFOLGE DER SUKZESSIVEN LÖSCHUNGEN IN DER DEKODIERUNG VON POLARKODES

ALTÉRATION DE L'ORDRE D'ANNULATIONS SUCCESSIVES DANS LE DÉCODAGE D'UN CODE POLAIRE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 06.02.2017 US 201762455322 P

(43)Date of publication of application:
11.12.2019 Bulletin 2019/50

(73)Proprietor: Telefonaktiebolaget LM Ericsson (publ)
164 83 Stockholm (SE)

(72)Inventors:
  • HUI, Dennis
    Sunnyvale, California 94087 (US)
  • BLANKENSHIP, Yufei
    Kildeer, Illinois 60047 (US)

(74)Representative: Ericsson 
Patent Development Torshamnsgatan 21-23
164 80 Stockholm
164 80 Stockholm (SE)


(56)References cited: : 
EP-A1- 2 953 307
US-A1- 2013 117 344
  
  • BHARATH KUMAR REDDY L ET AL: "A GPU implementation of belief propagation decoder for polar codes", ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS. CONFERENCE RECORD, IEEE COMPUTER SOCIETY, US, 4 November 2012 (2012-11-04), pages 1272-1276, XP032351087, ISSN: 1058-6393, DOI: 10.1109/ACSSC.2012.6489228 ISBN: 978-1-4673-5050-1
  • VANGALA HARISH ET AL: "A new multiple folded successive cancellation decoder for polar codes", 2014 IEEE INFORMATION THEORY WORKSHOP (ITW 2014), IEEE, 2 November 2014 (2014-11-02), pages 381-385, XP032694569, ISSN: 1662-9019, DOI: 10.1109/ITW.2014.6970858 [retrieved on 2014-12-01]
  • VALERIO BIOGLIO ET AL: "Low-Complexity Puncturing and Shortening of Polar Codes", ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, 23 January 2017 (2017-01-23), XP080750896,
  • NADINE HUSSAMI ET AL: "Performance of Polar Codes for Channel and Source Coding", ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, 16 January 2009 (2009-01-16), XP080357414, DOI: 10.1109/ISIT.2009.5205860
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Technical Field



[0001] Polar codes, Cyclic Redundancy Check (CRC), error detection

Background



[0002] Polar codes, proposed by Arikan [1], are the first class of constructive coding schemes that are provable to achieve the symmetric capacity of the binary-input discrete memoryless channels under a low-complexity Successive Cancellation (SC) decoder. However, the finite-length performance of polar codes under SC is not competitive compared to other modern channel coding schemes such as Low-Density Parity-Check (LDPC) codes and Turbo codes. Later, a SC List (SCL) decoder is proposed in [2], which can approach the performance of an optimal Maximum-Likelihood (ML) decoder. By concatenating a simple Cyclic Redundancy Check (CRC) coding, it was shown that the performance of concatenated polar code is competitive with that of well-optimized LDPC and Turbo codes. As a result, polar codes are being considered as a candidate for future Fifth Generation (5G) wireless communication systems. The main idea of polar coding is to transform a pair of identical binary-input channels into two distinct channels of different qualities, one better and one worse than the original binary-input channel. By repeating such a pair-wise polarizing operation on a set of 2M independent uses of a binary-input channel, a set of 2M "bit-channels" of varying qualities can be obtained. Some of these bit channels are nearly perfect (i.e., error free) while the rest of them are nearly useless (i.e., totally noisy). The point is to use the nearly perfect channel to transmit data to the receiver while setting the input to the useless channels to have fixed or frozen values (e.g., 0) known to the receiver. For this reason, those input bits to the nearly useless and the nearly perfect channel are commonly referred to as frozen bits and non-frozen (or information) bits, respectively. Only the non-frozen bits are used to carry data in a polar code. An illustration of the structure of a length 8 polar code is illustrated in Figure 1.

[0003] Figure 2 illustrates the labeling of the intermediate information bits sl,i, where l ∈ {0,1,···,n} and i ∈ {0,1,···, N - 1} during polar encoding with N = 8. The intermediate information bits are related by the following equation:



for i ∈ {0,1,···, N - 1} and l ∈ {0,1,···, n - 1}, with s0,iui being the information bits, and sn,ixi being the code bits, for i ∈ {0,1,···, N - 1}.

[0004] In this discussion, we assume a butterfly based decoder as illustrated in Figure 3 for the case of N = 8. Messages passed in the decoder are Log-Likelihood Ratio (LLR) values denoted as LI,i, where I and i correspond to the graph stage index and row index, respectively. In addition, Ln,i is the LLR directly calculated from the channel output yi. The basic components of the decoder are two functions given by:



for l ∈ {0,1,···, n - 1} and i ∈ {0,1,····, N - 1}, where B(l,i) denotes the lth significant bit in the binary representation of i, and where l,i denotes an estimate of the intermediate information bit sl,i.

[0005] Some background information can be found in Bharath Kumar et al., "A GPU implementation of belief propagation decoder for polar codes", Asilomar Conference on Signals, Systems and Computers, IEEE Computer Society, US, 4 November 2012, pages 1272-1276, which discloses performing a bit reversal permutation before and after polar decoding, and in Vangala Harish et al., "A new multiple folded successive cancellation decoder for polar codes", 2014 IEEE Information Theory Workshop (ITW 2014), 2 November 2014, pages 381-385. Further background information can be found in US 2013/117344 and Nadine Hussami et al., "Performance of Polar Codes for Channel and Source Coding", arxiv.org, Cornell University Library, 22 May 2009. This latter document discloses performing belief propagation decoding on a plurality of polar code graphs, for example three graphs, which are derived from the original polar code graph by permuting the stages of the graph. The input and output bits are not permuted.

Summary



[0006] Systems and methods for performing polar decoding using a transformation of the coded bits prior to polar decoding and an inverse transformation of the resulting data bits after polar decoding are disclosed.

[0007] The invention concerns a method of operation of a receiving node as defined in claims 1-12, a receiving node as defined in claims 13-14, and a computer readable storage medium comprising a computer program as defined in claim 15.

Brief Description of the Drawings



[0008] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

Figure 1 is an illustration of the structure of a length 8 polar code;

Figure 2 illustrates the labeling of the intermediate information bits sl,i, where l ∈ {0,1,···,n} and i ∈ {0,1,···, N - 1} during polar encoding with N = 8;

Figure 3 illustrates a butterfly based decoder for the case of N = 8;

Figure 4 illustrates a polar encoder according to some embodiments of the present disclosure;

Figure 5 illustrates a polar decoder according to some embodiments of the present disclosure;

Figure 6 is a flow chart that illustrates the operation of a receiving node to perform polar decoding according to some embodiments of the present disclosure;

Figure 7 illustrates one example of non-overlapping decomposition of a length N polar code;

Figure 8 illustrates a decomposition of a polar code of length 16 into two polar codes of length 4 and one polar code of length 8, based on a prefix-free code C = {00,01,1};

Figure 9 is a flow chart that illustrates one example of a process (performed by a receiving node) to perform polar decoding for each of multiple component polar codes according to some embodiments of the present disclosure;

Figure 10 is a flow chart that illustrates one example of a process (performed by a receiving node) to perform polar decoding using L different transformations are applied, where L > 1, according to some embodiments of the present disclosure;

Figure 11 illustrates one example of an overlapping subtree decomposition for which conditional Transformed Successive Cancellation (TSC) decoding can be performed according to some embodiments of the present disclosure;

Figure 12 illustrates one example of a wireless system in which embodiments of the present disclosure may be implemented;

Figures 13 and 14 illustrate example embodiments of a wireless device in which embodiments of the present disclosure may be implemented; and

Figures 15 through 17 illustrate example embodiments of a network node in which embodiments of the present disclosure may be implemented.


Detailed Description



[0009] The embodiments set forth below represent information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure.

[0010] Radio Node: As used herein, a "radio node" is either a radio access node or a wireless device.

[0011] Radio Access Node: As used herein, a "radio access node" or "radio network node" is any node in a radio access network of a cellular communications network that operates to wirelessly transmit and/or receive signals. Some examples of a radio access node include, but are not limited to, a base station (e.g., a New Radio (NR) base station (gNB) in a Third Generation Partnership Project (3GPP) Fifth Generation (5G) NR network or an enhanced or evolved Node B (eNB) in a 3GPP Long Term Evolution (LTE) network), a high-power or macro base station, a low-power base station (e.g., a micro base station, a pico base station, a home eNB, or the like), and a relay node.

[0012] Core Network Node: As used herein, a "core network node" is any type of node in a core network. Some examples of a core network node include, e.g., a Mobility Management Entity (MME), a Packet Data Network Gateway (P-GW), a Service Capability Exposure Function (SCEF), or the like.

[0013] Wireless Device: As used herein, a "wireless device" is any type of device that has access to (i.e., is served by) a cellular communications network by wirelessly transmitting and/or receiving signals to a radio access node(s). Some examples of a wireless device include, but are not limited to, a User Equipment device (UE) in a 3GPP network and a Machine Type Communication (MTC) device.

[0014] Network Node: As used herein, a "network node" is any node that is either part of the radio access network or the core network of a cellular communications network/system.

[0015] Note that the description given herein focuses on a 3GPP cellular communications system and, as such, 3GPP terminology or terminology similar to 3GPP terminology is oftentimes used. However, the concepts disclosed herein are not limited to a 3GPP system.

[0016] Note that, in the description herein, reference may be made to the term "cell;" however, particularly with respect to 5G NR concepts, beams may be used instead of cells and, as such, it is important to note that the concepts described herein are equally applicable to both cells and beams.

[0017] The most widely used polar decoder types to date are the Successive Cancellation (SC) and the List decoding of SC (SCL). Both SC and SCL make a (tentative or final) decision on each information bit one after another, without taking into account the knowledge of the future frozen bits when making a decision on any particular information bit. Their performances are thus suboptimal in general, compared to a Maximum-Likelihood (ML) decoder. The performance gap varies with the frozen bit locations with respect to the information bit locations.

[0018] Due to the successive nature of SC and SCL decoding operations, the order by which the SC is done can play a substantial role in the performance. It is particularly important when the information bit location is not optimally chosen. This can be caused by situations when some information bits are known at the receiver from other information and thus effectively become frozen bits. In general, in order to improve performance, it is often desirable to change the order of decoding of information bits and frozen bits to account for the knowledge of some future frozen bits. However, for a given set of locations for the information bit, conventional SC and SCL decoders can only perform the decoding in a specific order that corresponds to the natural ordering of the bit indices.

[0019] In some embodiments of the present disclosure, a method is provided for performing successive decoding in different orderings that can allow the SC/SCL decoder to take into account some future information bits and frozen bits when making decision on a particular information bit. The main idea is to apply certain permutation(s) to the Log-Likelihood Ratios (LLRs) before or during the decoding process, perform a basic polar decoding algorithm (e.g., SC decoding) in the normal process based on natural ordering of the bit indices, and then apply the corresponding inverse permutation(s) to the information bits in the end of the decoding process. While simple permutation is the preferred method, linear transformation(s) in general can be used.

[0020] Due to the tree structure of polar codes, such a process can be performed conditionally in any subtree of the decoding tree in order to re-order the decoding process for the section of the information/frozen bits that correspond to that subtree while keeping other subtrees unaffected. This allows a higher flexibility in changing the decoding order and thus more degree of freedom to improve performance through localized linear transforms.

[0021] By re-ordering the successive decoding process, some of the future frozen bits can be swapped in front of some information bits during decoding. As a result, the conventional successive decoding based on natural ordering can be used while taking into account those future frozen bit values that would otherwise be ignored by the conventional SC/SCL decoders. As a result, the decoding performance can be enhanced without the need of increasing the decoding complexity, e.g. through an increased list size of a SCL decoder.

Self-Similar Transformations



[0022] In the present disclosure, we focus the discussion on binary polar codes in the binary field

The basic idea can be straightforwardly generalized to non-binary polar codes.

[0023] Let GN0 be a kernel matrix of size N0 × No, with all its elements in

, based on which the generating matrix of a polar code is generated. The most commonly used kernel matrix is the Arikan matrix [1]:



[0024] The generating matrix of the polar code G of mother code block length N is given by repeatedly applying Kronecker operation on GNo, i.e.

where ⊗ denotes the Kronecker operation. Given a data vector u = (u0, u1,···, uN-1), the vector of coded bits after polar encoding is given by x = uGN. For polar encoding, the data vector u is typically composed of both information bits and frozen bits. The information bits are assigned to bit locations of higher reliability. The frozen bits have known values (typically '0') and are assigned to bit locations of lower reliability.

[0025] The vector of coded bits x is then transmitted by the transmitter over the channel, possibly after further operations such as coded bit puncturing, interleaving, modulation symbol formulation, etc. The vector of coded bits x is received by the receiver as the corresponding vector y of the same length, after receiver processing including, for example, channel estimation, channel LLR calculation, de-interleaving, de-puncturing, etc. The vector y is the input to the polar decoder, which attempts to produce as output an estimate v of the information vector u. From v, the estimated information bits are delivered to higher layer for further processing, while the frozen bits are discarded. Typically the vector y is in the format of LLR values, which is the case when soft-decoding is used. However, one of skill in the art will readily appreciate that, if hard-decoding is alternatively used, then the vector y is in the format of hard decision values.

[0026] The basic idea of the present disclosure is that there exists some invertible transformation T such that the following equation is satisfied for the polar generating matrix G:



[0027] We refer to such a transformation (matrix) TN as a self-similar transformation (matrix) for the polar code of code length N or for its generating matrix GN. Self-similar transformations allow polar codes to be decoded successively in the transformed domain, as further illustrated below. It is noted that the invention is limited to transformation matrices which re-order coded bits in the received coded bit vector.

[0028] First we give some examples of self-similar transformation. There are many different self-similar transmissions. To simplify discussions, we focus on the case when the kernel matrix is the Arikan matrix. For this case, several kinds are of particular interests in practice, which are described below.

Bit-Reversal Permutation



[0029] The first kind is the bit-reversal permutation characterized by the bit-reversal matrix RN that performs permutation in such a way that eiRN = er(i), for all i ∈ {0,1,2,···, N - 1}, where ei denotes a vector with all zeros except at the ith position where the element is one, and where r(i) ∈ {0,1,2,···, N - 1} denotes a number whose binary representation is in a reversed bit order as the binary representation of the number i. For this kind of self-similar transformation, we have

and


Least-Significant Bit (LSB) to Most Significant Bit (MSB) (or MSB-to-LSB) Permutation



[0030] The second kind of self-similar transformation is the last-to-first permutation matrix FN of the following form:

where IN/2 is the (N/2) × (N/2) identity matrix. This matrix permutes the input vector in such a way that eiFN = eφ(i), for all i ∈ {0,1,2, ···, N - 1}, where φ(i) ∈ {0,1,2, ···, N - 1} denotes a number whose binary representation is almost the same binary representation of the number i except that the LSB of the index i becomes the MSB of i. In other words, the last-to-first permutation matrix permutes such that the LSB of the index of the input becomes the MSB of the index of the output. It is easy to verify that

and thus

In other words, multiplying a vector from the left on

effectively permutes the vector so that the MSB of the binary representation of the component indices is moved to the LSB, i.e. the inverse operation of multiplying the vector by FN.

[0031] It follows that Equation (1) is satisfied by setting TN = FN or setting

as





[0032] So FN is also a self-similar transformation for any N. It can easily be verified that

and




Any-Bit-to-MSB (or Any-Bit-to-LSB) Permutation



[0033] An important kind of self-similar transformation that generalizes an LSB-to-MSB (or alternatively MSB-to-LSB) permutation is to move any bit (instead of just the LSB) in the binary representation of bit indices to the MSB (or alternatively LSB). This can be achieved by performing Kronecker products on FN (or

) as

for any M that is a power of 2 and is no larger than N. The effect of the transformation AM,N is to permute the input vector in such a way that the (log2 M)th MSB in the binary representation of the bit indices moves to the MSB location. It follows easily that Equation (1) is satisfied since

where the identity (AB)(CD) = (ACBD) is used in the second equality above.

[0034] In general, the product of any self-similar transformation is also self-similar in the same dimension, and the Kronecker product of any self-similar transformation is also self-similar (for the corresponding larger matrix), which can be proven straightforwardly with derivations similar as that shown above.

Arbitrary Bit Permutation



[0035] By applying the Any-Bit-to-MSB permutations multiple times, one can achieve any permutation of the binary representation of the bit indices. More specifically, let µ: {1,2,···, log2 N} → {1,2,···, log2 N) be any permutation mapping on the bits in the binary representation of each bit-channel index, with µ(1) and µ(log2 N) point to the LSB and MSB, respectively. One can define an arbitrary bit permutation transformation matrix as

where

can be chosen one-by-one in a straightforward manner such that the µ(i)-th bit is in the i-th position in the final permuted binary representation. Since the product of any self-similar transformation is also self-similar, we have Sµ,N satisfying Equation (1) in the following form:


Transformed Successive Cancellation (TSC) Decoding



[0036] The reason for studying self-similar transformations is that it allows us to perform polar encoding and decoding in the transformed domain. Since

the encoding procedure of x = u GN is equivalent to

for any self-similar transformation TN. The polar encoding with transformation can be described as the following. The data vector uN is transformed by TN to obtain the transformed data vector

The basic polar encoder takes

as input and generates the transformed code bit vector

as output:

By applying the inverse transform

to

the final encoder output xN is obtained, which is ready to be transmitted over the channel. This is illustrated in Figure 4. Note that the blocks illustrated in Figure 4 may be implemented in hardware or a combination of hardware and software.

[0037] Correspondingly, the polar decoding with transformation can be described as the following. Corresponding to code bit vector xN, the received code bit vector yN is taken as input to the decoding process. First transform the channel LLR vector yN, received for example from the demodulator, by TN to obtain the transformed code bit vector

The vector

is the input to the basic polar decoder to obtain the transformed data bit vector

The basic polar decoder typically performs the SC or SCL decoding to obtain the estimated transformed data vector

Finally, the inverse transform is applied to obtain the estimated data bit vector vN from

The estimated information bits are then extracted from the information bit locations within vN, while discarding the rest (which are typically frozen bits).

[0038] The decoding of polar code with transformation is illustrated in Figure 5. Note that the blocks illustrated in Figure 5 may be implemented in hardware or a combination of hardware and software. Note that the estimated (transformed) data vectors

and vN may be represented by formats: (a) binary value (i.e., hard bits) of the data bits; or (b) soft information (e.g., LLRs) of the data bits.

[0039] The decoder output is a correct estimation, if vN = uN (here it is assumed that vN is the hard-decision output of the decoder). Otherwise the decoder output is erroneous, which may result due to poor channel condition.

[0040] When TN is a permutation matrix, like those described in the previous section, the decoding procedure can be carried out using any of the permutations. As a result, using this transformed decoding structure, any two sets of information bit locations (or information set) can be transformed into each other using these permutations of the index bits of the binary representation of the bit channels. Each set of information bit locations can be used together with the basic polar decoder (typically SC or SCL decoding) and yield an estimate of the information bits being carried.

[0041] In general, when the transformation TN is self-similar, the transformation in transformed polar encoding does not need to be performed, since it produces the same output as the ordinary polar encoding without transformation. In contrast, the transformed polar decoding is useful in that the transformation introduces different order of estimating the bit values in traversing the tree that may improve the decoding performance. However, when the transformation TN is not self-similar, transformed polar encoding is different from the ordinary polar encoding without transformation, and the transformation cannot be omitted. In this case, the transformed polar decoding is a corresponding method of decoding the transformed polar code.

[0042] Figure 6 illustrates a polar decoding process in accordance with at least some of the embodiments described herein. This processing is performed by a receiving node (e.g., a radio node in a wireless system operating to receive a wireless signal transmitted by another radio node in the wireless system, as described below). As described herein, the receiving node transforms a received code bit vector yN in accordance with a transformation TN to thereby provide a transformed code bit vector

(step 100). As discussed above, the transformation TN is a self-similar transformation, i.e., the transformation TN satisfies

Examples of the self-similar transformation are provided above.

[0043] The receiving node performs polar decoding (e.g., SC decoding or SCL decoding) of the transformed code bit vector

to thereby provide a transformed data bit vector

(step 102). The receiving node then inversely transforms the transformed data bit vector

in accordance with the inverse transformation

to thereby provide an estimated data bit vector

(step 104). Optionally, the receiving node extracts information bits, as opposed to known, frozen bits, from the estimated data bit vector

(step 106).

Conditional TSC Decoding


Non-Overlapping Decomposition



[0044] Polar code has a tree structure. Each of the leaf nodes of the tree represents a data bit. A polar code of code length N can be formed by combining the two polar codes of length/2, as illustrated in Figure 7 where a polar code of length N = 16 can be viewed as the combination of two codes of length N = 8, each represented by a subtree. Each of the two subtrees of length N = 8 corresponds to conditioning on the two possible values (0 or 1) of the MSB in the binary representation of the bit-channel indices that can be used to carry a data bit. This decomposition or conditioning into smaller subtrees can be recursively performed until a polar code of smallest block length of N = 2 is reached.

[0045] During a typical SC or SCL decoding process, each of the leaf nodes in the tree shown in Figure 7 is processed from left-to-right one by one to make a decision (or a tentative decision in the case of list decoding) on the corresponding data bit. The computation of LLRs are traversed through the tree in a depth-first-search manner. In effect, polar codes of smallest block length (N = 2) are processed one at a time from left to right until all information bits are decoded (or leaf nodes are traversed).

[0046] In general, one can decompose a polar code of length N into multiple independent polar codes of smaller lengths according to any (possibly) variable-length prefix-free code C = {b1, b2,····, bQ} of which each codeword bi has a maximum length of N bits, where Q is an integer no larger than (log2 N) - 2. A prefix-free code is a code where no codeword is a prefix of another codeword. Each component polar code that the original polar code is decomposed into is represented by a subtree of the overall tree structure, where the overall tree structure represents the original polar code of length N. The prefix-free property ensures that the subtrees that represent all component polar codes do not overlap with each other. For example, Figure 8 shows a decomposition of a polar code of length 16 into two polar codes of length 4 and one polar code of length 8, based on a prefix-free code C = {00,01,1}.

[0047] According to some embodiments of the present disclosure, the transformed polar encoding and decoding can be applied to each of these component polar codes individually, possibly each with a different self-similar transformation matrix TNi that corresponds to a codeword bi. In other words, during successive SC or SCL decoding of a polar code of length N, individual transforms of corresponding sizes may be applied for each of the component polar codes.

[0048] Figure 9 is a flow chart that illustrates one example of a process (performed by a receiving node) to perform polar decoding for each of multiple component polar codes. In Figure 9, the index "i" is an index to the component polar codes and, likewise, an index to the codeword bi in the prefix-free code C = {b1, b2,···, bQ}. Again, optional steps are illustrated with dashed lines.

[0049] As illustrated, the receiving node optionally decomposes the length N polar code (which was used by the transmitting node for polar encoding) into multiple component codes as described above (step 200). The decomposition is not necessarily performed by the receiving node (e.g., the decomposition may be predefined). The index i is set to 1 (step 202). As described herein, the receiving node transforms a received code bit vector yN in accordance with a transformation TNi to thereby provide a transformed code bit vector

(step 204). As discussed above, the transformation TNi is a self-similar transformation. Further, different transformations TNi may be used for different component polar codes, as described above.

[0050] The receiving node performs polar decoding (e.g., SC decoding or SCL decoding) of the transformed code bit vector

to thereby provide a transformed data bit vector

(step 206). The receiving node then inversely transforms the transformed data bit vector

in accordance with the inverse transformation

to thereby provide an estimated data bit vector

(step 208). If the index has not yet reached that of the last component polar code (step 210, NO), the index is incremented (step 212) and the process returns to step 204 and is repeated for the next component polar code. Optionally, the receiving node extracts information bits, as opposed to known, frozen bits, from the estimated data bit vectors

(step 214).

[0051] The benefit of doing the conditional or tree-structured transformed SC or SCL decoding is that it provides more flexibility to permute the bit-channels. This allows more subtrees or component polar codes to have a special structure which can be then be exploited by specialized decoding implementation. For example, those methods of simplified SC and SCL decoding described in [3] achieved by specially treating subtrees or component polar codes with code rates that are (almost) zero and one may be used after transformation is performed in each of the component polar code. This can reduce the latency and energy consumption in the decoding process.

[0052] In other embodiments of the present disclosure, for a given polar tree (or subtree), L different transformations are applied, where L > 1. For each transformation, a SC decoding is applied to generate the i-th candidate tree (or subtree) output, i = 1,2,···, L. After obtaining the L candidates, the best candidate(s) is then selected as the final output of the tree (or subtree). The candidate can be selected according several different types of criteria, including:
  1. (a) Path metric magnitude;
  2. (b) Cyclic Redundancy Check (CRC) checksum; and
  3. (c) Parity-checksum.


[0053] Figure 10 is a flow chart that illustrates one example of a process (performed by a receiving node) to perform polar decoding using L different transformations are applied, where L > 1. In Figure 10, the index "i" is an index to the ith transformation TNi. Again, optional steps are illustrated with dashed lines. As illustrated, the receiving node optionally determines the L different transformations TNi for i = {1,2, ..., L} (step 300). The L different transformations TNi are not necessarily determined by the receiving node (e.g., they may be predefined or determined by another node). The index i is set to 1 (step 302). As described herein, the receiving node transforms a received code bit vector yN in accordance with a transformation TNi to thereby provide a transformed code bit vector

(step 304). As discussed above, the transformation TNi is a self-similar transformation.

[0054] The receiving node performs polar decoding (e.g., SC decoding or SCL decoding) of the transformed code bit vector

to thereby provide a transformed data bit vector

(step 306). The receiving node then inversely transforms the transformed data bit vector

in accordance with the inverse transformation

to thereby provide an estimated data bit vector

(step 308). If the index has not yet reached that of the last component polar code (step 310, NO), the index is incremented (step 312) and the process returns to step 304 and is repeated for the next component polar code.

[0055] Optionally, once all L different transformations TNi have been processed, the receiving node selects a best estimated data bit vector vN from among the estimated data bit vectors

(step 314). As discussed above, this selection may be based on any suitable criteria such as, e.g., one or more of a path metric magnitude, CRC checksum, and/or parity-checksum. Optionally, the receiving node extracts information bits, as opposed to known, frozen bits, from the estimated data bit vector vN (step 316).

Overlapping Decomposition



[0056] Non-overlapping decomposition of a polar code into smaller component polar codes is only one simple and possible way of conditional TSC decoding. In general, conditional TSC decoding can be performed with overlapping subtree decomposition as well as illustrated in Figure 11. This kind of decomposition can also be described by a variable-length code C with a special symbol ρ to represent the root of the tree. The main difference is that the code C may not be prefix-free. For example, Figure 11 describes a code {ρ, 01}, where ρ denotes the root of the tree. Same as non-overlapping decomposition, each codeword bi in the variable-length code represents a subtree and an associated linear transformation TNi.

[0057] TSC decoding with overlapping decomposition introduces further flexibility in changing the order by which the data bits are decoded.

[0058] TSC decoding with overlapping decomposition may be performed as illustrated in, e.g., Figure 9 but where the variable-length code C is not prefix-free.

Example System



[0059] Figure 12 illustrates one example of a wireless system 10 (e.g., a cellular communications network such as, for example, a 3GPP 5G or NR network) in which embodiments of the present disclosure may be implemented. As illustrated, a number of wireless devices 12 (e.g., UEs) wirelessly transmit signals to and receive signals from radio access nodes 14 (e.g., gNBs), each serving one or more cells 16. The radio access nodes 14 are connected to a core network 18. The core network 18 includes one or more core network nodes (e.g., MMEs, Serving Gateways (S-GWs), and/or the like).

[0060] Note that the polar decoder of Figure 5 as well as the polar decoding process described above (e.g., with respect to Figures 6-11) may be implemented in any radio node within the wireless system 10 such as, for example, the wireless devices 12 and/or the radio access nodes 14.

[0061] Figure 13 is a schematic block diagram of the wireless device 12 (e.g., UE) according to some embodiments of the present disclosure. As illustrated, the wireless device 12 includes processing circuitry 20 comprising one or more processors 22 (e.g., Central Processing Units (CPUs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs), and/or the like) and memory 24. The wireless device 12 also includes one or more transceivers 26 each including one or more transmitters 28 and one or more receivers 30 coupled to one or more antennas 32. In some embodiments, the functionality of the wireless device 12 described above may be implemented in hardware (e.g., via hardware within the circuitry 20 and/or within the processor(s) 22) or be implemented in a combination of hardware and software (e.g., fully or partially implemented in software that is, e.g., stored in the memory 24 and executed by the processor(s) 22).

[0062] In some embodiments, a computer program including instructions which, when executed by the at least one processor 22, causes the at least one processor 22 to carry out at least some of the functionality of the wireless device 12 according to any of the embodiments described herein is provided. In some embodiments, a carrier containing the aforementioned computer program product is provided. The carrier is one of an electronic signal, an optical signal, a radio signal, or a computer readable storage medium (e.g., a non-transitory computer readable medium such as memory).

[0063] Figure 14 is a schematic block diagram of the wireless device 12 (e.g., UE) according to some other embodiments of the present disclosure. The wireless device 12 includes one or more modules 34, each of which is implemented in software. The module(s) 34 provide the functionality of the wireless device 12 described herein.

[0064] Figure 15 is a schematic block diagram of a network node 36 (e.g., a radio access node 14 such as, for example, a gNB or a network node such as a core network node) according to some embodiments of the present disclosure. As illustrated, the network node 36 includes a control system 38 that includes circuitry comprising one or more processors 40 (e.g., CPUs, ASICs, DSPs, FPGAs, and/or the like) and memory 42. The control system 38 also includes a network interface 44. In embodiments in which the network node 36 is a radio access node 14, the network node 36 also includes one or more radio units 46 that each include one or more transmitters 48 and one or more receivers 50 coupled to one or more antennas 52. In some embodiments, the functionality of the network node 36 (e.g., the functionality of the radio access node 14) described above may be fully or partially implemented in software that is, e.g., stored in the memory 42 and executed by the processor(s) 40.

[0065] Figure 16 is a schematic block diagram that illustrates a virtualized embodiment of the network node 36 (e.g., the radio access node 14) according to some embodiments of the present disclosure. As used herein, a "virtualized" network node 36 is a network node 36 in which at least a portion of the functionality of the network node 36 is implemented as a virtual component (e.g., via a virtual machine(s) executing on a physical processing node(s) in a network(s)). As illustrated, the network node 36 optionally includes the control system 38, as described with respect to Figure 15. In addition, if the network node 36 is the radio access node 14, the network node 36 also includes the one or more radio units 46, as described with respect to Figure 15. The control system 38 (if present) is connected to one or more processing nodes 54 coupled to or included as part of a network(s) 56 via the network interface 44. Alternatively, if the control system 38 is not present, the one or more radio units 46 (if present) are connected to the one or more processing nodes 54 via a network interface(s). Alternatively, all of the functionality of the network node 36 described herein may be implemented in the processing nodes 54 (i.e., the network node 36 does not include the control system 38 or the radio unit(s) 46). Each processing node 54 includes one or more processors 58 (e.g., CPUs, ASICs, DSPs, FPGAs, and/or the like), memory 60, and a network interface 62.

[0066] In this example, functions 64 of the network node 36 described herein are implemented at the one or more processing nodes 54 or distributed across the control system 38 (if present) and the one or more processing nodes 54 in any desired manner. In some particular embodiments, some or all of the functions 64 of the network node 36 described herein are implemented as virtual components executed by one or more virtual machines implemented in a virtual environment(s) hosted by the processing node(s) 54. As will be appreciated by one of ordinary skill in the art, additional signaling or communication between the processing node(s) 54 and the control system 38 (if present) or alternatively the radio unit(s) 46 (if present) is used in order to carry out at least some of the desired functions. Notably, in some embodiments, the control system 38 may not be included, in which case the radio unit(s) 46 (if present) communicates directly with the processing node(s) 54 via an appropriate network interface(s).

[0067] In some particular embodiments, higher layer functionality (e.g., layer 3 and up and possibly some of layer 2 of the protocol stack) of the network node 36 may be implemented at the processing node(s) 54 as virtual components (i.e., implemented "in the cloud") whereas lower layer functionality (e.g., layer 1 and possibly some of layer 2 of the protocol stack) may be implemented in the radio unit(s) 46 and possibly the control system 38.

[0068] In some embodiments, a computer program including instructions which, when executed by the at least one processor 40, 58, causes the at least one processor 40, 58 to carry out the functionality of the network node 36 or a processing node 54 according to any of the embodiments described herein is provided. In some embodiments, a carrier containing the aforementioned computer program product is provided. The carrier is one of an electronic signal, an optical signal, a radio signal, or a computer readable storage medium (e.g., a non-transitory computer readable medium such as the memory 60).

[0069] Figure 17 is a schematic block diagram of the network node 36 (e.g., the radio access node 14) according to some other embodiments of the present disclosure. The network node 36 includes one or more modules 66, each of which is implemented in software. The module(s) 66 provide the functionality of the network node 36 described herein.

[0070] The following acronyms are used throughout this disclosure.
• 3GPP Third Generation Partnership Project
• 5G Fifth Generation
• ASIC Application Specific Integrated Circuit
• CPU Central Processing Unit
• CRC Cyclic Redundancy Check
• DSP Digital Signal Processor
• eNB Enhanced or Evolved Node B
• FPGA Field Programmable Gate Array
• gNB New Radio Base Station
• LDPC Low-Density Parity-Check
• LLR Log-Likelihood Ratio
• LSB Least-Significant Bit
• LTE Long Term Evolution
• ML Maximum-Likelihood
• MME Mobility Management Entity
• MSB Most Significant Bit
• MTC Machine Type Communication
• P-GW Packet Data Network Gateway
• NR New Radio
• SC Successive Cancellation
• SCEF Service Capability Exposure Function
• SCL List decoding of Successive Cancellation
• S-GW Serving Gateway
• TSC Transformed Successive Cancellation
• UE User Equipment

Reference List



[0071] 
  1. [1] E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, vol. 55, pp. 3051-3073, Jul. 2009.
  2. [2] I. Tal and A. Vardy, "List Decoding of polar codes," in Proceedings of IEEE Symp. Inf. Theory, pp. 1-5, 2011.
  3. [3] G. Sarkis P. Giard, A. Vardy, C. Thibeault, and W.J. Gross., "Fast Polar Decoders: Algorithm and Implementation," IEEE Journal on Selected Areas in Communications, VOL. 32, pp. 946-957, May, 2014.



Claims

1. A method of operation of a receiving node to perform polar decoding for polar code of code length N, comprising:

transforming (100) a received code bit vector yN in accordance with a transformation matrix TN that re-orders coded bits in the received coded bit vector to thereby provide a transformed code bit vector

performing (102) polar decoding of the transformed code bit vector

to thereby provide a transformed data bit vector

and

inversely transforming (104) the transformed data bit vector

in accordance with an inverse transformation matrix

to thereby provide an estimated data bit vector

wherein

is the inverse of TN; the method further comprising performing the steps of transforming (100), decoding (102), and inversely transforming (104) for each of a plurality of different transformation matrices TN to thereby provide a plurality of estimated data bit vectors.


 
2. The method of claim 1 wherein each transformation matrix TN satisfies:

where GN is a polar generating matrix of length N.
 
3. The method of claim 2 wherein one of the plurality of different transformation matrices TN is a bit-reversal matrix RN that performs permutation in such a way that an order of the bits in a binary representation of indices that address elements in the received code bit vector yN is reversed to provide the transformed code bit vector


 
4. The method of claim 2 or 3 wherein one of the plurality of different transformation matrices TN is a last-to-first permutation matrix FN that performs permutation in such a way that a last bit in a binary representation of indices that address elements of the received code bit vector yN becomes a first bit in a binary representation of indices that address elements of the transformed code bit vector


 
5. The method of any of claims 2-4 wherein one of the plurality of different transformation matrices TN is an any-bit-to-any-bit permutation matrix AM,N for any M that is a power of 2 and is no larger than N, wherein the any-bit-to-any-bit permutation matrix AM,N performs permutation in such a way that a bit at a first bit location in a binary representation of indices that address elements of the received code bit vector yN becomes a bit at a second bit location in a binary representation of indices that address elements of the transformed code bit vector

wherein the first bit location is different than the second bit location.
 
6. The method of any of claims 2-5 wherein one of the plurality of different transformation matrices TN is an arbitrary bit permutation matrix Sµ,N that performs multiple any-bit-to-most-significant bit permutations on bits in a binary representation of indices that address elements of the received code bit vector yN to provide the transformed code bit vector


 
7. The method of any one of claims 1-6 wherein performing (102) polar decoding of the transformed code bit vector

comprises performing (102) successive cancellation decoding of the transformed code bit vector

to thereby provide the transformed data bit vector


 
8. The method of any one of claims 1-6 wherein performing (102) polar decoding of the transformed code bit vector

comprises performing (102) successive cancellation list decoding of the transformed code bit vector

to thereby provide the transformed data bit vector


 
9. The method of any one of claims 1-8 wherein the received code bit vector yN is a vector of Log-Likelihood Ratios, LLRs.
 
10. The method of any one of claims 1-9 further comprising extracting (106) information bits, as opposed to frozen bits, from the estimated data bit vectors vN.
 
11. The method of any one of claims 1-10 further comprising selecting a best estimated data bit vector from among the plurality of estimated data bit vectors output based on the plurality of different transformations TN as a final estimated data bit vector.
 
12. The method of claim 11 wherein selecting the best estimated data bit vector comprises selecting the best estimated data bit vector from among the plurality of estimated data bit vectors output based on the plurality of different transformations TN based on one or more criteria comprising at least one of a path metric magnitude, a Cyclic Redundancy Check, CRC, checksum, and a parity-checksum.
 
13. A receiving node operable to perform polar decoding for polar code of code length N, the receiving node adapted to:

(i) transform a received code bit vector yN in accordance with a transformation matrix TN that re-orders the coded bits in the received coded bit vector to thereby provide a transformed code bit vector

(ii) perform polar decoding of the transformed code bit vector

to thereby provide a transformed data bit vector

and

(iii) inversely transform the transformed data bit vector

in accordance with an inverse transformation matrix

to thereby provide an estimated data bit vector

wherein

is the inverse of TN;

wherein the receiving node is further adapted to perform (i), (ii), and (iii) for each of a plurality of different transformation matrices TN to thereby provide a plurality of estimated data bit vectors.
 
14. The receiving node of claim 13 wherein the receiving node is further adapted to perform the method of any one of claims 2-12.
 
15. A computer readable storage medium comprising a computer program comprising instructions which, when executed on at least one processor, cause the at least one processor to carry out the method according to any one of claims 1-12.
 


Ansprüche

1. Betriebsverfahren für einen Empfangsknoten zum Durchführen von Decodierung für polaren Code mit einer Codelänge N, umfassend:

Transformieren (100) eines empfangenen Codebitvektors yN gemäß einer Transformationsmatrix TN, welche codierte Bits im empfangen Codebitvektor neu ordnet, um einen transformierten Codebitvektor

bereitzustellen;

Durchführen (102) von Polardecodierung des transformierten Codebitvektors

um dadurch einen transformierten Datenbitvektor

bereitzustellen; und

inverses Transformieren (104) des transformierten Datenbitvektors

gemäß einer inversen Transformationsmatrix

um dadurch einen geschätzten Datenbitvektor

bereitzustellen, wobei

die Inverse von TN ist;

wobei das Verfahren ferner ein Ausführen der Schritte des Transformierens (100), Decodierens (102) und inversen Transformierens (104) für jede einer Mehrzahl von verschiedenen Transformationsmatrizen TN umfasst, um dadurch eine Mehrzahl von geschätzten Datenbitvektoren bereitzustellen.
 
2. Verfahren nach Anspruch 1, wobei jede Transformationsmatrix TN erfüllt:

wobei GN eine polare erzeugende Matrix einer Länge N ist.
 
3. Verfahren nach Anspruch 2, wobei eine der Mehrzahl von verschiedenen Transformationsmatrizen TN eine Bitumkehrmatrix RN ist, die Permutation derart durchführt, dass eine Reihenfolge der Bits in einer Binärdarstellung von Indizes, die Elemente im empfangenen Codebitvektor yN adressieren, umgekehrt wird, um den transformierten Codebitvektor

bereitzustellen.
 
4. Verfahren nach Anspruch 2 oder 3, wobei eine der Mehrzahl von Transformationsmatrizen TN eine Last-to-first-Permutationsmatrix FN ist, die Permutation derart durchführt, dass ein letztes Bit in einer Binärdarstellung von Indizes, die Elemente des empfangenen Codebitvektors yN adressieren, ein erstes Bit in einer Binärdarstellung von Indizes wird, die Elemente des transformierten Codebitvektors

adressieren.
 
5. Verfahren nach einem der Ansprüche 2 bis 4, wobei eine der Mehrzahl von Transformationsmatrizen TN eine Any-bit-to-any-bit-Permutationsmatrix AM,N für jedes M ist, das eine Zweierpotenz ist und nicht größer als N ist, wobei die Any-bit-to-any-bit-Permutationsmatrix AM,N Permutation derart durchführt, dass ein Bit in einer ersten Bitposition in einer Binärdarstellung von Indizes, die Elemente des empfangenen Codebitvektors yN adressieren, ein Bit in einer zweiten Bitposition in einer Binärdarstellung von Indizes wird, die Elemente des transformierten Codebitvektors

adressieren, wobei die erste Bitposition eine andere als die zweite Bitposition ist.
 
6. Verfahren nach einem der Ansprüche 2 bis 5, wobei eine der Mehrzahl von Transformationsmatrizen TN eine Arbitrary-bit-Permutationsmatrix Sµ,N ist, die mehrere Any-bit-to-most-significant-bit-Permutationen an Bits in einer Binärdarstellung von Indizes durchführt, die Elemente des empfangenen Codebitvektors yN adressieren, um den transformierten Codebitvektor

bereitzustellen.
 
7. Verfahren nach einem der Ansprüche 1 bis 6, wobei das Durchführen (102) von Polardecodierung des transformierten Codebitvektors

ein Durchführen (102) von Successive-Cancellation-Decodierung des transformierten Codebitvektors

umfasst, um dadurch den transformierten Codebitvektor

bereitzustellen.
 
8. Verfahren nach einem der Ansprüche 1 bis 6, wobei das Durchführen (102) von Polardecodierung des transformierten Codebitvektors

ein Durchführen (102) von Successive-Cancellation-List-Decodierung des transformierten Codebitvektors

umfasst, um dadurch den transformierten Codebitvektor

bereitzustellen.
 
9. Verfahren nach einem der Ansprüche 1 bis 8, wobei der empfangene Codebitvektor yN ein Vektor von logarithmischen Wahrscheinlichkeitsverhältnissen, LLRs, ist.
 
10. Verfahren nach einem der Ansprüche 1 bis 9, ferner umfassend ein Extrahieren (106) von Informationsbits im Gegensatz zu gefrorenen Bits aus den geschätzten Datenbitvektoren vN.
 
11. Verfahren nach einem der Ansprüche 1 bis 10, ferner umfassend ein Auswählen eines besten geschätzten Datenbitvektors aus der Mehrzahl von geschätzten Datenbitvektoren, die basierend auf der Mehrzahl von verschiedenen Transformationen TN ausgegeben werden, als einen endgültigen geschätzten Datenbitvektor.
 
12. Verfahren nach Anspruch 11, wobei das Auswählen des besten geschätzten Datenbitvektor ein Auswählen des besten geschätzten Datenbitvektors aus der Mehrzahl von geschätzten Datenbitvektoren, die basierend auf der Mehrzahl von verschiedenen Transformationen TN ausgegeben werden, basierend auf einem oder mehreren Kriterien umfasst, die mindestens eine von einer Pfadmetrikgröße, einer Prüfsumme einer zyklischen Redundanzprüfung, CRC, und einer Paritätsprüfsumme umfassen.
 
13. Empfangsknoten, der zum Durchführen von Polardecodierung für polaren Code mit einer Codelänge N betrieben werden kann, wobei der Empfangsknoten ausgelegt ist zum:

(i) Transformieren eines empfangenen Codebitvektors yN gemäß einer Transformationsmatrix TN, welche die codierten Bits im empfangenen Codebitvektor neu ordnet, um einen transformierten Codebitvektor

bereitzustellen;

(ii) Durchführen von Polardecodierung des transformierten Codebitvektors

um dadurch einen transformierten Datenbitvektor

bereitzustellen; und

(iii) inversen Transformieren des transformierten Datenbitvektors

gemäß einer inversen Transformationsmatrix

um dadurch einen geschätzten Datenbitvektor

bereitzustellen, wobei

die Inverse von TN ist;

wobei der Empfangsknoten ferner zum Ausführen von (i), (ii) und (iii) für jede einer Mehrzahl von verschiedenen Transformationsmatrizen TN ausgelegt ist, um dadurch eine Mehrzahl von geschätzten Datenbitvektoren bereitzustellen.
 
14. Empfangsknoten nach Anspruch 13, wobei der Empfangsknoten ferner zum Durchführen des Verfahrens nach einem der Ansprüche 2 bis 12 ausgelegt ist.
 
15. Computerlesbares Speichermedium, umfassend ein Computerprogramm, das Anweisungen umfasst, die bei Ausführung auf mindestens einem Prozessor den mindestens einen Prozessor zum Durchführen des Verfahrens nach einem der Ansprüche 1 bis 12 veranlassen.
 


Revendications

1. Procédé de fonctionnement d'un nœud de réception pour réaliser un décodage polaire pour un code polaire d'une longueur de code N, comprenant :

la transformation (100) d'un vecteur de bits de code reçu yN selon une matrice de transformation TN qui réordonne des bits codés dans le vecteur de bits codé reçu pour fournir de ce fait un vecteur de bits de code transformé

la réalisation (102) d'un décodage polaire du vecteur de bits de code transformé

pour fournir de ce fait un vecteur de bits de données transformé

et

la transformation inverse (104) du vecteur de bits de données transformé

selon une matrice de transformation inverse

pour fournir de ce fait un vecteur de bits de données estimé

dans lequel

est l'inverse de TN ;

le procédé comprenant en outre la réalisation des étapes de la transformation (100), du décodage (102), et de la transformation inverse (104) pour chacune d'une pluralité de matrices de transformation différentes TN pour fournir de ce fait une pluralité de vecteurs de bits de données estimés.
 
2. Procédé selon la revendication 1, dans lequel chaque matrice de transformation TN satisfait :

GN est une matrice de génération polaire d'une longueur N.
 
3. Procédé selon la revendication 2, dans lequel l'une de la pluralité de matrices de transformation différentes TN est une matrice d'inversion de bits RN qui réalise une permutation de telle manière qu'un ordre des bits dans une représentation binaire d'indices adressant des éléments dans le vecteur de bits de code reçu yN soit inversé pour fournir le vecteur de bits de code transformé


 
4. Procédé selon la revendication 2 ou 3, dans lequel l'une de la pluralité de matrices de transformation différentes TN est une matrice de permutation du dernier au premier FN qui réalise une permutation de telle manière qu'un dernier bit dans une représentation binaire d'indices adressant des éléments du vecteur de bits de code reçu yN devienne un premier bit dans une représentation binaire d'indices adressant des éléments du vecteur de bits de code transformé


 
5. Procédé selon l'une quelconque des revendications 2 à 4, dans lequel l'une de la pluralité de matrices de transformation différentes TN est une matrice de permutation de n'importe quel bit à n'importe quel bit AM,N pour n'importe quel M qui est une puissance de 2 et n'est pas plus grand que N, dans lequel la matrice de permutation de n'importe quel bit à n'importe quel bit AM,N réalise une permutation de telle manière qu'un bit à un premier emplacement de bit dans une représentation binaire d'indices adressant des éléments du vecteur de bits de code reçu yN devienne un bit à un deuxième emplacement de bit dans une représentation binaire d'indices adressant des éléments du vecteur de bits de code transformé

dans lequel le premier emplacement de bit est différent du deuxième emplacement de bit.
 
6. Procédé selon l'une quelconque des revendications 2 à 5, dans lequel l'une de la pluralité de matrices de transformation différentes TN est une matrice de permutation de bits arbitraires Sµ,N qui réalise de multiples permutations de n'importe quel bit à un bit de poids fort sur des bits dans une représentation binaire d'indices adressant des éléments du vecteur de bits de code reçu yN pour fournir le vecteur de bits de code transformé


 
7. Procédé selon l'une quelconque des revendications 1 à 6, dans lequel la réalisation (102) d'un décodage polaire du vecteur de bits de code transformé

comprend la réalisation (102) d'un décodage par éliminations successives du vecteur de bits de code transformé

pour fournir de ce fait le vecteur de bits de données transformé


 
8. Procédé selon l'une quelconque des revendications 1 à 6, dans lequel la réalisation (102) d'un décodage polaire du vecteur de bits de code transformé

comprend la réalisation (102) d'un décodage de liste par éliminations successives du vecteur de bits de code transformé

pour fournir de ce fait le vecteur de bits de données transformé


 
9. Procédé selon l'une quelconque des revendications 1 à 8, dans lequel le vecteur de bits de code reçu yN est un vecteur de logarithmes de rapports de vraisemblance, LLR.
 
10. Procédé selon l'une quelconque des revendications 1 à 9, comprenant en outre l'extraction (106) de bits d'informations, au lieu de bits figés, des vecteurs binaire de données estimés vN.
 
11. Procédé selon l'une quelconque des revendications 1 à 10, comprenant en outre la sélection du meilleur vecteur de bits de données estimé parmi la pluralité de vecteurs de bits de données estimés délivrés sur la base de la pluralité de transformations différentes TN en tant que vecteur de bits de données estimé final.
 
12. Procédé selon la revendication 11, dans lequel la sélection du meilleur vecteur de bits de données estimé comprend la sélection du meilleur vecteur de bits de données estimé parmi la pluralité de vecteurs de bits de données estimés délivrés sur la base de la pluralité de transformations différentes TN sur la base d'un ou plusieurs critères comprenant au moins l'une parmi : une grandeur de métrique de chemin, une somme de contrôle de contrôle de redondance cyclique, CRC, et une somme de contrôle de parité.
 
13. Nœud de réception utilisable pour réaliser un décodage polaire pour un code polaire d'une longueur de code N, the nœud de réception étant apte à :

(i) transformer un vecteur de bits de code reçu yN selon une matrice de transformation TN qui réordonne les bits codés dans le vecteur de bits codé reçu pour fournir de ce fait un vecteur de bits de code transformé

(ii) réaliser un décodage polaire du vecteur de bits de code transformé

pour fournir de ce fait un vecteur de bits de données transformé

et

(iii) transformer inversement le vecteur de bits de données transformé

selon une matrice de transformation inverse

pour fournir de ce fait un vecteur de bits de données estimé

dans lequel

est l'inverse de TN ;

dans lequel le nœud de réception est en outre apte à réaliser (i), (ii), et (iii) pour chacune d'une pluralité de matrices de transformation différentes TN pour fournir de ce fait une pluralité de vecteurs de bits de données estimés.
 
14. Nœud de réception of claim 13, dans lequel le nœud de réception est en outre apte à réaliser un procédé selon l'une quelconque des revendications 2 à 12.
 
15. Support de stockage lisible par ordinateur comprenant un programme informatique comprenant des instructions qui, lorsqu'elles sont exécutées sur au moins un processeur, amènent l'au moins un processeur à réaliser le procédé selon l'une quelconque des revendications 1 à 12.
 




Drawing















































Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description




Non-patent literature cited in the description