(19)
(11)EP 3 588 502 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
25.03.2020 Bulletin 2020/13

(43)Date of publication A2:
01.01.2020 Bulletin 2020/01

(21)Application number: 19175812.7

(22)Date of filing:  21.05.2019
(51)International Patent Classification (IPC): 
G11C 11/16(2006.01)
H01L 27/06(2006.01)
H01L 21/768(2006.01)
H01L 27/22(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 28.06.2018 US 201816022519

(71)Applicant: Intel Corporation
Santa Clara, CA 95054 (US)

(72)Inventors:
  • MANIPATRUNI, Sasikanth
    Portland, OR 97229 (US)
  • GOSAVI, Tanay
    Hillsboro, OR 97124 (US)
  • YOUNG, Ian
    Portland, OR 97229 (US)
  • NIKONOV, Dmitri
    Beaverton, OR 97007 (US)

(74)Representative: Goddar, Heinz J. 
Boehmert & Boehmert Anwaltspartnerschaft mbB Pettenkoferstrasse 22
80336 München
80336 München (DE)

  


(54)MAGNETIC TUNNEL JUNCTION (MTJ) INTEGRATION ON BACKSIDE OF SILICON


(57) A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.







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