(19)
(11)EP 3 598 499 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
29.07.2020 Bulletin 2020/31

(43)Date of publication A2:
22.01.2020 Bulletin 2020/04

(21)Application number: 19185055.1

(22)Date of filing:  08.07.2019
(51)International Patent Classification (IPC): 
H01L 27/146(2006.01)
G01S 7/4914(2020.01)
G01S 17/36(2006.01)
G01S 17/931(2020.01)
G01S 7/481(2006.01)
G01S 17/88(2006.01)
G01S 17/894(2020.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 18.07.2018 JP 2018135395

(71)Applicant: Sony Semiconductor Solutions Corporation
Atsugi-shi, Kanagawa (JP)

(72)Inventors:
  • EBIKO, Yoshiki
    Kanagawa, 243-0014 (JP)
  • NEYA, Koji
    Kanagawa, 243-0014 (JP)
  • SANO, Takuya
    Kanagawa, 243-0014 (JP)

(74)Representative: MFG Patentanwälte Meyer-Wildhagen Meggle-Freund Gerhard PartG mbB 
Amalienstraße 62
80799 München
80799 München (DE)

  


(54)LIGHT RECEIVING ELEMENT, RANGING MODULE, AND ELECTRONIC APPARATUS


(57) Disclosed is a light receiving element (1) including an on-chip lens (47), a wiring layer (42), and a semiconductor layer (41) disposed between the on-chip lens and the wiring layer. The semiconductor layer includes a photodiode (PD), a first transfer transistor (TRG1) that transfers electric charge generated in the photodiode to a first charge storage portion (FD1), a second transfer transistor (TRG2) that transfers electric charge generated in the photodiode to a second charge storage portion (FD2), and an interpixel separation portion (61) that separates the semiconductor layers of adjacent pixels from each other, for at least part of the semiconductor layer in the depth direction. The wiring layer has at least one layer including a light blocking member (63). The light blocking member is disposed to overlap with the photodiode in a plan view.







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