(19)
(11)EP 3 605 113 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
30.03.2022 Bulletin 2022/13

(21)Application number: 19177281.3

(22)Date of filing:  29.05.2019
(51)International Patent Classification (IPC): 
G01R 13/02(2006.01)
(52)Cooperative Patent Classification (CPC):
G01R 13/0254

(54)

DIGITAL TRIGGERING SYSTEM AS WELL AS METHOD FOR PROCESSING DATA

DIGITALES AUSLÖSESYSTEM SOWIE VERFAHREN ZUR VERARBEITUNG VON DATEN

SYSTÈME DE DÉCLENCHEMENT NUMÉRIQUE AINSI QUE PROCÉDÉ DE TRAITEMENT DE DONNÉES


(84)Designated Contracting States:
AL AT BE BG CY CZ DE DK EE ES FI FR GB GR HR HU IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 03.08.2018 US 201816054261

(43)Date of publication of application:
05.02.2020 Bulletin 2020/06

(73)Proprietor: Rohde & Schwarz GmbH & Co. KG
81671 München (DE)

(72)Inventors:
  • Lagler, Andreas
    81671 München (DE)
  • Ramian, Florian
    81671 München (DE)

(74)Representative: Prinz & Partner mbB 
Patent- und Rechtsanwälte Rundfunkplatz 2
80335 München
80335 München (DE)


(56)References cited: : 
US-A1- 2008 082 278
US-A1- 2013 060 527
US-A1- 2012 197 598
US-B2- 7 765 086
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The invention provides a digital triggering system for processing data relating to a signal received. Further, the invention provides a method for processing data.

    [0002] In modern data processing devices, digital triggering systems are known that are assigned to In-phase and Quadrature-phase data (IQ data) of a digital signal processed which was digitized previously.

    [0003] The digital triggering system generally ensures that data relating to a certain portion of a signal is only acquired if a certain trigger event occurs in the signal, for instance to acquire data surrounding an event of interest within the input signal. Typically, a trigger event corresponds to an anomalous event that occurs in the signal received with regard to a certain signal processing parameter. For instance, the trigger event may occur with regard to the frequency, amplitude, phase or any other signal processing parameter.

    [0004] The triggering system typically comprises a trigger channel as well as an acquisition channel wherein the trigger channel processes the data received appropriately in order to identify the event of interest in the data processed corresponding to the trigger event. Once a trigger event is identified in the data processed, the trigger channel triggers the acquisition channel appropriately in order to acquire the respective data relating to the trigger event, in particular to acquire data surrounding the trigger event.

    [0005] For instance, US 7,765,086 B2 shows a digital triggering system that comprises several different trigger generators which each correspond to a respective triggering channel. The trigger generators each receive the same data as the acquisition channel wherein the respective channels, namely the triggering channel as well as the acquisition channel, also have the same signal processing parameters which, therefore, are dependent from each other.

    [0006] In fact, a trigger signal is generated once a trigger event is detected in the respective data, namely the IQ data provided by the IQ data source, with regard to a certain signal processing parameter wherein the respective data is acquired with regard to the same signal processing parameter that is used for triggering.

    [0007] However, data relating to a certain signal processing parameter may be of interest that comes together with an event of interest which occurs in the data or rather the signal with regard to another signal processing parameter.

    [0008] US 2008/082278 A1 shows a realtime spectrum trigger system on realtime oscilloscope, wherein the realtime spectrum trigger system comprises a trigger circuit that receives the same data as an acquisition channel such that a triggering channel as well as the acquisition channel have the same signal processing parameters.

    [0009] The invention provides a digital triggering system for processing data relating to a signal received, comprising:
    • an analog-to-digital converter for converting an analog input signal into a digital signal,
    • an IQ data source providing IQ data,
    • a first digital signal processor located downstream of said IQ data source, and
    • at least a second digital signal processor located downstream of said IQ data source,
    said first digital signal processor being connected with said IQ data source via a first signal path so that said first digital signal processor obtains the IQ data provided by said IQ data source,

    said second digital signal processor being connected with said IQ data source via a second signal path so that said second digital signal processor obtains the IQ data provided by said IQ data source,

    said first digital signal processor having at least a first signal processing parameter and said second digital signal processor having at least a second signal processing parameter, said first signal processing parameter and said second signal processing parameter being independent from each other,

    said first digital signal processor generating a trigger signal based upon a characteristic of the IQ data obtained from said IQ data source, and

    said first digital signal processor triggering said second digital signal processor via said trigger signal to acquire IQ data obtained from said IQ data source.



    [0010] Accordingly, a digital triggering system is provided that is enabled to acquire IQ data based upon a trigger event wherein the second digital signal processor used for acquiring the IQ data has a signal processing parameter that is independent from the signal processing parameter used by the first digital signal processor for triggering. Thus, the first digital signal processor is at least used as a trigger generator. Hence, both digital signal processors are enabled to use different data portions of the IQ data provided as they are assigned to independent signal processing parameters. Therefore, a wide variety of different signal processing parameters may be used for identifying a trigger event and acquiring data since the IQ data is acquired with regard to a signal processing parameter that is independent of the signal processing parameter used for triggering.

    [0011] In general, the characteristic of the IQ data may relate to a trigger event occurring in the signal which corresponds to the IQ data provided by the IQ data source.

    [0012] For instance, the first digital signal processor may investigate the signal or rather the IQ data obtained in the time domain such as power overtime or rather amplitude over time, whereas the second digital signal processor acquires data relating to frequency overtime. Hence, frequency and time data is acquired once the first digital signal processor identifies a trigger event in the power and time data or rather amplitude and time data. Accordingly, different signal processing parameters may be applied for triggering and acquisition. Put another way, the first signal processing parameter may relate to the time domain, particularly a parameter in the time domain, whereas the second signal processing parameter may relate to the frequency domain, particularly a parameter in the frequency domain, or vice versa. However, the first and second signal processing parameters may also relate to the same domain, namely time domain or frequency domain, but different parameters in the same domain.

    [0013] The IQ data obtained may be compared with a threshold value so as to identify an occurring trigger event. The trigger event may relate to reaching or rather exceeding the threshold value. For instance, the power or rather the amplitude of the signal is compared with the threshold value so as to provide an amplitude versus time triggering.

    [0014] The signal received may be converted into a digital signal, for instance by using the analog-to-digital converter, said digital signal being demodulated so as to obtain the IQ data provided by said IQ data source. This means that the signal has been modulated previously wherein it is demodulated in order to obtain the IQ data. Thus, the IQ data source may relate to a IQ demodulation module.

    [0015] According to an aspect, said first digital signal processor and said second digital signal processor have different signal processing parameters. Thus, the signal processing parameters used by the digital signal processors are not only independent from each other, but different.

    [0016] Said first digital signal processor and said second digital signal processor may be configured to capture the signal received on different portions of the spectrum of the signal. Therefore, a frequency focus may be applied since different frequencies or rather frequency spans are processed by the digital signal processors. In other words, the first digital signal processor may use a narrowband frequency span while investigating the signal or rather the IQ data obtained, for instance in the time domain (power over time or rather amplitude over time) whereas the second digital signal processor uses a wideband frequency span. Alternatively, the digital signal processors may relate to different frequency portions of the signal received as a filter or different filters are applied.

    [0017] According to another aspect, said first digital signal processor also acquires IQ data obtained from said IQ data source. Thus, both digital signal processors are used for acquiring IQ data. Therefore, the first digital signal processor is not only used as a trigger generator. Furthermore, both digital signal processors may acquire data with regard to different portions of the spectrum of the signal.

    [0018] In addition, both digital signal processors may acquire data with regard to different or at least independent signal processing parameters. Alternatively, both digital signal processors may acquire IQ data with regard to the same signal processing parameter. Hence, the first digital signal processor uses a first signal processing parameter for triggering and a second processing parameter for acquisition.

    [0019] Particularly, said IQ data acquired by said first digital signal processor and said IQ data acquired by said second digital signal processor relate to different portions of the spectrum of said signal received. The signal received corresponds to the IQ data provided by said IQ data source since the IQ data is generated from the signal received. Therefore, the spectrum of the signal received which is digitized and demodulated may be divided into different portions wherein the digital signal processors are assigned to dedicated portions so that they process different portions of the spectrum of the signal.

    [0020] Generally, a wideband frequency span as well as a narrowband frequency span of the signal received can be processed by the digital signal processors that relate to the different portions of the spectrum of the signal received. In these different portions, the independent signal processing parameters may be applied by the digital signal processors.

    [0021] In fact, it is no more necessary that real-time capable hardware for the whole bandwidth is used in order to acquire data in a wideband signal. Thus, the costs can be reduced significantly.

    [0022] Moreover, said first digital signal processor and said second digital signal processor may be connected with each other via a trigger line via which said first digital signal processor forwards said trigger signal to said second digital signal processor. Thus, the second digital signal processor may relate to a further stage with regard to the first digital signal processor as it also receives the trigger signal provided by the first digital signal processor.

    [0023] According to another embodiment, said first signal path and said second signal path both branch off from a common signal path line connected to said IQ data source. Thus, both signal paths are connected with a common signal path line so that the IQ data provided by the IQ data source is forwarded to both signal paths. The IQ data provided is, however, processed differently by the digital signal processors connected thereto, in particular with regard to the signal processing parameters and/or the portions of the spectrum of the signal processed by the digital signal processors.

    [0024] Furthermore, said first digital signal processor may use at least one of frequency domain triggering, time domain triggering, phase domain triggering, modulation domain triggering and demodulation domain triggering, for instance frequency mask triggering, amplitude versus time triggering, frequency modulation (FM) bandwidth triggering and FM bandwidth deviation triggering. For instance, minimum, maximum, peak, roots means square, average and/or slope may be applied for triggering. In addition, Quadrature Amplitude Modulation (QAM) triggering, Code Domain Multiple Access (CDMA) triggering, and Orthogonal Frequency Division Multiplexing (OFDM) triggering may be used.

    [0025] Accordingly, typical IQ based triggers can be used by the first digital signal processor in order to identify a trigger event.

    [0026] Besides the IQ based triggers mentioned above, any other IQ based trigger can be used by said first digital signal processor for identifying a trigger event and to generate the trigger signal that triggers the second digital signal processor to acquire IQ data respectively.

    [0027] According to another embodiment, a temporary intermediate storage for IQ data is provided that is assigned to at least one of said first digital signal processor and said second digital signal processor. In the temporary intermediate storage, IQ data is temporarily stored so that this temporarily stored data can be acquired if a trigger event occurs. This ensures that IQ data can be acquired even though the trigger event occurs later.

    [0028] Furthermore, a user interface may be provided via which a user is enabled to make settings of at least one of said first digital signal processor and said second digital signal processor. For instance, the user may set an offset with regard to the acquisition of IQ data so that IQ data is acquired by an offset earlier than the trigger event occurs.

    [0029] For this purpose, at least the second digital processor is assigned to the temporary intermediate storage so that the IQ data temporarily stored in the temporary intermediate storage may be acquired and forwarded to the acquisition memory.

    [0030] According to an aspect, the acquisition of IQ data via said second digital signal processor can be shifted by setting an offset. This shifting of the acquisition of IQ data relates to a time shift so that the acquisition of IQ data takes place earlier or even later depending on the offset set by the user. Hence, the offset is a time offset.

    [0031] For instance, the acquisition of IQ data via said second digital signal processor is started prior to a trigger event. The temporarily stored IQ data in the temporary intermediate storage is forwarded to the acquisition memory so that this data is acquired even though the trigger event occurs later. The trigger event is assigned to the characteristic of the IQ data obtained or rather the characteristic of the signal.

    [0032] According to another aspect, said digital triggering system comprises a measurement module, said measurement module providing further analysis. The data obtained or rather acquired may be further analyzed by using the measurement module that is part of the digital triggering system.

    [0033] For instance, said measurement module comprises said first digital signal processor at least in parts so as to generate said trigger signal. The trigger signal may be generated depending on an analysis done by the measurement module. For this purpose, the measurement module comprises the first digital signal processor at least in parts so that generating the trigger signal is controlled by the measurement module.

    [0034] Said measurement module may be assigned to said second signal path for further analyzing the IQ data processed by at least one of said second signal path and said second digital signal processor. Hence, the IQ data acquired by said second digital signal processor may be analyzed by the measurement module. Alternatively or additionally, the IQ data processed by said signal path may be analyzed by the measurement module.

    [0035] Moreover, an acquisition memory for IQ data may be provided to store the IQ data acquired, said acquisition memory being connected with at least one of said first digital signal processor and said second digital signal processor. For instance, the acquisition memory may also be connected with the temporary intermediate storage for IQ data so that the temporarily stored IQ data may be forwarded to the acquisition memory for acquiring purposes so that the respective data may be acquired depending on an offset set by the user.

    [0036] Generally, the acquisition memory being connected with both digital signal processors ensures that the IQ data acquired by both signals processors can be stored for further processing.

    [0037] Furthermore, the at least one second digital signal processor corresponds to a stage of the digital triggering system, wherein the digital triggering system may have several stages which receive said trigger signal from said first digital signal processor. In other words, the digital triggering system may comprise several digital signal processors established like the second digital signal processor so that the first digital signal processor triggers the several digital signal processors each using signal processing parameters being different to the one used by the first digital signal processor for triggering.

    [0038] Generally, a signal processing device may be provided that comprises the digital triggering system as described above.

    [0039] Hence, the signal processing device comprises the analog-to-digital converter, the IQ data source, the digital signal processors, the respective signal paths and/or lines, the temporary intermediate storage for IQ data, the user interface, the measurement module and/or the acquisition memory for IQ data.

    [0040] The invention also provides a method for processing data, comprising the following steps:
    • Converting an analog signal into a digital signal,
    • Obtaining IQ data from said digital signal,
    • Processing the IQ data obtained while a first signal processing parameter is taken into account by a first digital signal processor,
    • Generating a trigger signal via said first digital signal processor when a trigger event occurs in the IQ data processed with regard to said first signal processing parameter, thereby triggering a second digital signal processor via said trigger signal to acquire IQ data obtained from an IQ data source, and
    • Acquiring IQ data via said second digital signal processor which takes a second signal processing parameter into account that is independent from said first signal processing parameter.


    [0041] As already discussed, both digital signal processors use signal processing parameters which are independent from each other so that the acquired data is independent from the data used for triggering.

    [0042] The signal received may be captured on different portions of the spectrum of the signal by the digital signal processors. For instance, a frequency filter or a frequency sport may be applied.

    [0043] Moreover, IQ data may be acquired by both digital signal processors. Hence, the first digital signal processor is assigned to a triggering channel and an acquisition channel simultaneously.

    [0044] The foregoing aspects and many of the attendant advantages of the claimed subject matter will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
    • Figure 1 schematically shows a digital triggering system according to an embodiment of the invention; and
    • Figure 2 schematically shows a time chart of IQ data processed by both digital signal processors.


    [0045] The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed.

    [0046] In Figure 1, a digital triggering system 10 is shown that may be part of a signal processing device such as a measurement device and/or a signal analysis device.

    [0047] The digital triggering system 10 comprises an analog-to-digital converter 12 that converts an analog signal received via an input into a digital signal.

    [0048] The analog-to-digital converter 12 is connected with an IQ data source 14 that provides IQ data by processing the digitized signal received from the analog-to-digital converter 12. In fact, the digital signal received may be demodulated so that an IQ demodulation module may be said IQ data source 14 providing the IQ data.

    [0049] For instance, a radio frequency (RF) signal is converted into a digital signal.

    [0050] The digital triggering system 10 or rather the signal processing device having the digital triggering system 10 may comprise a radio frequency (RF) signal conditioner, a local oscillator for converting the RF signal into an intermediate frequency (IF) signal by mixing with a local oscillator frequency as well as a filter for filtering the IF signal obtained.

    [0051] The respective units may be located upstream of the analog-to-digital converter 12 so that the pre-processed IF signal is digitized.

    [0052] Downstream of the analog-to-digital converter 12, the digital triggering system 10 or rather the data processing device having the digital triggering system 10 may have a signal correction unit for correcting the amplitude and phase data of the digitized IF signal. The corrected and digitized IF signal is then processed or rather demodulated so as to generate a set of I (In-phase) data and Q (Quadrature-phase) data, namely the IQ data, that is provided by the IQ data source 14 for further processing.

    [0053] As shown in Figure 1, the IQ data source 14 is connected to a first digital signal processor 16 via a common signal path line 18 and a first signal path 20.

    [0054] Further, the IQ data source 14 is connected with a second digital signal processor 22 via the common signal path line 18 and a second signal path 24.

    [0055] Thus, the first signal path 20 and the second signal path 24 both are connected with the IQ data source 14 via the common signal path line 18. In other words, the first signal path 20 as well as the second signal path 24 both branch off from the common signal path line 18 being directly connected to the IQ data source 14.

    [0056] This ensures that both digital signal processors 16, 22 receive the same IQ data corresponding to the signal received that has been digitized previously.

    [0057] Both digital signal processors 16, 22 have signal processing parameters being independent from each other so that the first digital signal processor 16 has a first signal processing parameter whereas the second digital signal processor 22 has a second signal processing parameter. The signal processing parameters are independent from each other.

    [0058] In other words, both digital signal processors 16, 22 are configured to apply signal processing parameters being independent from each other so that the signal received, in particular the IQ data obtained from the signal, may be investigated in many ways.

    [0059] In fact, the signal processing parameters used by both signal processors 16, 22 can be different from each other.

    [0060] Furthermore, the first digital signal processor 16 is connected with the second digital signal processor 22 via a trigger line 26 so that acquisition of IQ data via the second digital signal processor 22 can be triggered via a trigger signal generated by the first digital signal processor 16 as will be described hereinafter.

    [0061] Since both digital signal processors 16, 22 use independent signal processing parameters, the first digital signal processor 16 may apply a certain trigger with regard to the first signal processing parameter once a dedicated characteristic (trigger event) occurs so as to generate the trigger signal based upon the characteristic or rather the trigger event.

    [0062] The trigger signal generated is forwarded to the second digital signal processor 22 via the trigger line 26 to trigger acquisition of IQ data obtained from the IQ data source 14 via the second digital signal processor 22 with regard to the second signal processing parameter.

    [0063] Generally, the first digital signal processor 16 investigates the IQ data forwarded by the IQ data source 14 so as to find a trigger event or rather a characteristic in the IQ data received while using the first signal processing parameter whereas the second digital signal processor 22 acquires IQ data while using the second signal processing parameter being independent from the first one.

    [0064] In addition, both digital signal processors 16, 22 may correspond to different frequency spans of the spectrum of the analog signal converted previously so that the different signal processing parameters are applied to different signal portions of the spectrum of the signal processed, for instance to a wideband signal portion and a narrowband signal portion. Accordingly, a frequency filter or rather a frequency spot may be applied (simultaneously).

    [0065] For this purpose, the digital signal processors 16, 22 may have respective filters so that the digital signal processors 16, 22 are configured to capture the signal received on different portions with regard to the frequency.

    [0066] Thus, high IQ bandwidth can be processed by the digital triggering system 10 easily without the need of having real-time capable hardware for the whole bandwidth. The costs for the digital triggering system 10 as well as the signal processing device having the digital triggering system 10 can be reduced significantly.

    [0067] Furthermore, the digital triggering system 10 comprises an acquisition memory 28 that is assigned to both digital signal processors 16, 22 so that both digital signal processors 16, 22 may acquire IQ data that can be stored in the acquisition memory 28.

    [0068] The IQ data acquired by the first digital signal processor 16 as well as the IQ data acquired by the second digital signal processor 22 may relate to different portions of the spectrum of the analog signal received wherein these different portions correspond to the IQ data provided by the IQ data source.

    [0069] Moreover, a temporary intermediate storage 30 for IQ data may be provided that is assigned to the second digital signal processor 22 so that IQ data can be stored temporarily in the temporary intermediate storage 30.

    [0070] The temporary intermediate storage 30 may also be assigned to the first digital signal processor 16 so that IQ data may also be temporarily stored in the intermediate storage 30 for IQ data wherein the respective IQ data relates to IQ data processed by the first digital signal processor 16.

    [0071] Furthermore, the digital triggering system 10 comprises a user interface 32 via which a user may be enabled to make settings such as inputting an offset for IQ data acquisition.

    [0072] This ensures that IQ data acquisition can be postponed or generally shifted in time so that IQ data may be acquired prior to the occurrence of a trigger event detected by the first digital signal processor 16.

    [0073] Therefore, IQ data temporarily stored in the temporary intermediate storage 30 is forwarded to the acquisition storage 28 so that the respective IQ data is acquired even though the data was obtained or rather captured prior to the trigger event used for generating the trigger signal used by the second digital signal processor 22.

    [0074] Moreover, the digital triggering system 10 may have a measurement module 34 for further analyzing the signal received.

    [0075] The measurement module 34 comprises the first digital signal processor 16 at least in parts so that the trigger signal is controlled by the measurement module 34. In other words, the measurement module 34 may analyze the IQ data obtained and processed by the first digital signal processor 16 so that the trigger signal is generated based on a control signal outputted by the measurement module 34.

    [0076] Alternatively or additionally, the measurement module 34 is assigned to the second signal path 24 and/or the second digital signal processor 22 so that the respective IQ data processed by the second signal path 24 and/or the second digital signal processor 22 is used for further analyzing purposes by the measurement module 34.

    [0077] In fact, the digital signal processors 16, 22 may relate to narrowband frequency spans as well as wideband frequency spans so that the triggering performed in realtime corresponds to a narrowband signal portion whereas acquisition of a wideband signal portion is triggered appropriately.

    [0078] Therefore, a digital triggering system 10 is provided that ensures processing high IQ bandwidth at low costs since real-time capable hardware for the whole bandwidth of the IQ data processed is not required due to the fact that both digital signal processors 16, 22 are configured to capture the signal received on different portions of the spectrum of the signal.

    [0079] In addition, the digital signal processors 16, 22 have signal processing parameters being independent from each other.

    [0080] Generally, the second digital signal processor 22 may correspond to an acquisition channel whereas the first digital signal processor 16 corresponds to a trigger channel and an acquisition channel simultaneously since the first digital signal processor 16 is also used to acquire IQ data.

    [0081] In Figure 2, a time chart of IQ data processed by both digital signal processors 16, 22 is shown.

    [0082] The lower graph illustrates the signal processing of the first digital signal processor 16 investigating the signal or rather the IQ data obtained in power over time or rather amplitude over time whereas the upper graph illustrates the signal processing of the second digital signal processor 22 investigating the signal or rather the IQ data obtained in frequency over time (spectrogram). Hence, different signal processing parameters are used by both digital signal processors 16, 22.

    [0083] Moreover, the first digital signal processor 16 is configured to capture the signal received in a narrowband (NB) frequency span of the spectrum of the signal received whereas the second digital signal processor 22 is configured to capture the signal received in a wideband (WB) frequency span of the spectrum of the signal received.

    [0084] Once the first digital signal processor 16 detects a characteristic of the IQ data obtained from said IQ data source 14, namely exceeding a pre-defined threshold value in the example shown, a trigger signal is generated for triggering the second digital signal processor 22 to acquire data with regard to the respective signal processing parameter and the respective frequency span, namely the wideband (WB) frequency span as shown in Figure 2.

    [0085] In addition, the graphs illustrate that the acquisition can be shifted in time by making certain settings as the acquisition of IQ data via said second digital signal processor 22 is started prior to a trigger event by the time t.

    [0086] The respective setting can be done via the user interface 32.

    [0087] In addition, the overview of Figure 2 illustrates that both digital signal processors 16, 22 acquire measurement data, namely IQ data, that is forwarded to the acquisition memory 28.

    [0088] The IQ data acquired by both digital signal processors 16, 22 may be done with regard to the same signal processing parameter so that the signal processing parameter used for generating the trigger signal may be independent with regard to the signal processing parameter used by the second digital signal processor for IQ data acquisition.

    [0089] Alternatively to the shown trigger, the digital triggering system 10, in particular the first digital signal processor 16, may use at least one of frequency domain triggering, time domain triggering, phase domain triggering, modulation domain triggering and demodulation domain triggering.

    [0090] Thus, a typical IQ based trigger can be used by the first digital signal processor in order to identify a trigger event.

    [0091] Generally, any other IQ based trigger can be used by said first digital signal processor 16 for identifying a trigger event and to generate the trigger signal that triggers the second digital signal processor 22 to acquire IQ data respectively.


    Claims

    1. A digital triggering system (10) for processing data relating to a signal received, comprising:

    - an analog-to-digital converter (12) for converting an analog input signal into a digital signal,

    - an In-phase and Quadrature-phase, IQ, data source (14) providing IQ data,

    - a first digital signal processor (16) located downstream of said IQ data source (14), and

    - at least a second digital signal processor (22) located downstream of said IQ data source (14),

    said first digital signal processor (16) being connected with said IQ data source (14) via a first signal path (20) so that said first digital signal processor (16) obtains the IQ data provided by said IQ data source (14),

    said second digital signal processor (22) being connected with said IQ data source (14) via a second signal path (24) so that said second digital signal processor (22) obtains the IQ data provided by said IQ data source (14),

    said first digital signal processor (16) having at least a first signal processing parameter and said second digital signal processor (22) having at least a second signal processing parameter, said first signal processing parameter and said second signal processing parameter being independent from each other,

    said first digital signal processor generating a trigger signal based upon a characteristic of the IQ data obtained from said IQ data source (14), and

    said first digital signal processor (16) triggering said second digital signal processor (22) via said trigger signal to acquire IQ data obtained from said IQ data source (14).


     
    2. The digital triggering system (10) of claim 1, wherein said first digital signal processor (16) and said second digital signal processor (22) have different signal processing parameters.
     
    3. The digital triggering system (10) of claim 1 or 2, wherein said first digital signal processor (16) and said second digital signal processor (22) are configured to capture the signal received on different portions of the spectrum of the signal.
     
    4. The digital triggering system (10) of any of the preceding claims, wherein said first digital signal processor (16) also acquires IQ data obtained from said IQ data source (14), in particular wherein said IQ data acquired by said first digital signal processor (16) and said IQ data acquired by said second digital signal processor (22) relate to different portions of the spectrum of said signal received.
     
    5. The digital triggering system (10) of any of the preceding claims, wherein said first digital signal processor (16) and said second digital signal processor (22) are connected with each other via a trigger line (26) via which said first digital signal processor (16) forwards said trigger signal to said second digital signal processor (22).
     
    6. The digital triggering system (10) of any of the preceding claims, wherein said first signal path (20) and said second signal path both (24) branch off from a common signal path line (18) connected to said IQ data source (14).
     
    7. The digital triggering system (10) of any of the preceding claims, wherein said first digital signal processor (16) uses frequency domain triggering, time domain triggering, phase domain triggering, modulation domain triggering and/or demodulation domain triggering.
     
    8. The digital triggering system (10) of any of the preceding claims, wherein a temporary intermediate storage (30) for IQ data is provided that is assigned to said first digital signal processor (16) and/or said second digital signal processor (22).
     
    9. The digital triggering system (10) of any of the preceding claims, wherein a user interface (32) is provided via which a user is enabled to make settings of said first digital signal processor (16) and/or said second digital signal processor (22).
     
    10. The digital triggering system (10) of any of the preceding claims, wherein the acquisition of IQ data via said second digital signal processor (22) can be shifted by setting an offset.
     
    11. The digital triggering system (10) of any of the preceding claims, wherein the acquisition of IQ data via said second digital signal processor (22) is started prior to a trigger event.
     
    12. The digital triggering system (10) of any of the preceding claims, wherein said digital triggering system (10) comprises a measurement module (34), said measurement module (34) providing further analysis, in particular wherein said measurement module (34) is assigned to said second signal path (24) for further analyzing the IQ data processed by said second signal path (24) and/or said second digital signal processor (22).
     
    13. The digital triggering system (10) of any of the preceding claims, wherein an acquisition memory (28) for IQ data is provided to store the IQ data acquired, said acquisition memory (28) being connected with said first digital signal processor (16) and/or said second digital signal processor (22).
     
    14. The digital triggering system (10) of any of the preceding claims, wherein the at least one second digital signal processor (22) corresponds to a stage of the digital triggering system (10), the digital triggering system (10) comprising several stages which receive said trigger signal from said first digital signal processor (16).
     
    15. A method for processing data, comprising the following steps:

    - Converting an analog signal into a digital signal,

    - Obtaining In-phase and Quadrature-phase, IQ, data from said digital signal,

    - Processing the IQ data obtained while a first signal processing parameter is taken into account by a first digital signal processor (16),

    - Generating a trigger signal via said first digital signal processor (16) when a trigger event occurs in the IQ data processed with regard to said first signal processing parameter, thereby triggering a second digital signal processor (22) via said trigger signal to acquire IQ data obtained from an IQ data source (14), and

    - Acquiring IQ data via said second digital signal processor (22) which takes a second signal processing parameter into account that is independent from said first signal processing parameter.


     


    Ansprüche

    1. Digitales Auslösesystem (10) zum Verarbeiten von Daten, die ein empfangenes Signal betreffen, das Folgendes umfasst:

    - einen Analog-Digital-Wandler (12) zum Umwandeln eines analogen Eingangssignals in ein digitales Signal,

    - eine In-Phase-und-Quadraturphase(IQ)-Datenquelle (14), die IQ-Daten bereitstellt,

    - einen ersten digitalen Signalprozessor (16), der sich stromabwärtig von der IQ-Datenquelle (14) befindet, und

    - mindestens einen zweiten digitalen Signalprozessor (22), der sich stromabwärtig von der IQ-Datenquelle (14) befindet,

    wobei der erste digitale Signalprozessor (16) via einen ersten Signalpfad (20) mit der IQ-Datenquelle (14) verbunden ist, derart, dass der erste digitale Signalprozessor (16) die IQ-Daten, die von der IQ-Datenquelle (14) bereitgestellt werden, erhält,

    wobei der zweite digitale Signalprozessor (22) via einen zweiten Signalpfad (24) mit der IQ-Datenquelle (14) verbunden ist, derart, dass der zweite digitale Signalprozessor (22) die IQ-Daten, die von der IQ-Datenquelle (14) bereitgestellt werden, erhält,

    wobei der erste digitale Signalprozessor (16) mindestens einen ersten Signalverarbeitungsparameter aufweist und wobei der zweite digitale Signalprozessor (22) mindestens einen zweiten Signalverarbeitungsparameter umfasst, wobei der erste Signalverarbeitungsparameter und der zweite Signalverarbeitungsparameter unabhängig voneinander sind,

    wobei der erste digitale Signalprozessor auf Basis einer Eigenschaft der IQ-Daten, die von der IQ-Datenquelle (14) erhalten werden, ein Auslösesignal erzeugt und

    wobei der erste digitale Signalprozessor (16) den zweiten digitalen Signalprozessor (22) via das Auslösesignal zum Erfassen von IQ-Daten, die von der IQ-Datenquelle (14) erhalten werden, auslöst.


     
    2. Digitales Auslösesystem (10) nach Anspruch 1, wobei der erste digitale Signalprozessor (16) und der zweite digitale Signalprozessor (22) verschiedene Signalverarbeitungsparameter aufweisen.
     
    3. Digitales Auslösesystem (10) nach Anspruch 1 oder 2, wobei der erste digitale Signalprozessor (16) und der zweite digitale Signalprozessor (22) dazu ausgelegt sind, das empfangene Signal in verschiedenen Abschnitten des Spektrums des Signals aufzunehmen.
     
    4. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei der erste digitale Signalprozessor (16) auch IQ-Daten, die von der IQ-Datenquelle (14) erhalten werden, erfasst, insbesondere wobei die IQ-Daten, die vom ersten digitalen Signalprozessor (16) erfasst werden, und die IQ-Daten, die vom zweiten digitalen Signalprozessor (22) erfasst werden, verschiedene Abschnitte des Spektrums des empfangenen Signals betreffen.
     
    5. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei der erste digitale Signalprozessor (16) und der zweite digitale Signalprozessor (22) via eine Auslöseleitung (26) miteinander verbunden sind, via die der erste digitale Signalprozessor (16) das Auslösesignal zum zweiten digitalen Signalprozessor (22) weiterleitet.
     
    6. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei der erste Signalpfad (20) und der zweite Signalpfad (24) von einer gemeinsamen Signalpfadleitung (18), die mit der IQ-Datenquelle (14) verbunden ist, abzweigen.
     
    7. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei der erste digitale Signalprozessor (16) eine Frequenzdomänenauslösung, eine Zeitdomänenauslösung, eine Phasendomänenauslösung, eine Modulationsdomänenauslösung und/oder eine Demodulationsdomänenauslösung verwendet.
     
    8. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei ein temporärer Zwischenspeicher (30) für IQ-Daten bereitgestellt ist, der dem ersten digitalen Signalprozessor (16) und/oder dem zweiten digitalen Signalprozessor (22) zugewiesen ist.
     
    9. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei eine Benutzerschnittstelle (32) bereitgestellt ist, via die ein Benutzer Einstellungen am ersten digitalen Signalprozessor (16) und/oder am zweiten digitalen Signalprozessor (22) vornehmen kann.
     
    10. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei die Erfassung der IQ-Daten via den zweiten digitalen Signalprozessor (22) durch Einstellen eines Versatzes verschoben werden kann.
     
    11. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei die Erfassung der IQ-Daten via den zweiten digitalen Signalprozessor (22) vor einem Auslöseereignis gestartet wird.
     
    12. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei das digitale Auslösesystem (10) ein Messmodul (34) umfasst, wobei das Messmodul (34) eine weitere Analyse bereitstellt, insbesondere wobei das Messmodul (34) zum weiteren Analysieren der IQ-Daten, die vom zweiten Signalpfad (24) und/oder vom zweiten digitalen Signalprozessor (22) verarbeitet werden, dem zweiten Signalpfad (24) zugewiesen ist.
     
    13. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei zum Speichern der erfassten IQ-Daten ein Erfassungsspeicher (28) für IQ-Daten bereitgestellt ist, wobei der Erfassungsspeicher (28) mit dem ersten digitalen Prozessor (16) und/oder mit dem zweiten digitalen Signalprozessor (22) verbunden ist.
     
    14. Digitales Auslösesystem (10) nach einem der vorhergehenden Ansprüche, wobei der mindestens eine zweite digitale Signalprozessor (22) einer Stufe des digitalen Auslösesystems (10) entspricht, wobei das digitale Auslösesystem (10) mehrere Stufen umfasst, die das Auslösesignal vom ersten digitalen Signalprozessor (16) empfangen.
     
    15. Verfahren zum Verarbeiten von Daten, das folgende Schritte umfasst:

    - Umwandeln eines analogen Signals in ein digitales Signal,

    - Erhalten von In-phase-und-Quadraturphasedaten vom digitalen Signal,

    - Verarbeiten der erhaltenen IQ-Daten, während der erste Signalverarbeitungsparameter von einem ersten digitalen Signalprozessor (16) berücksichtigt wird,

    - Erzeugen eines Auslösesignals via den ersten digitalen Signalprozessor (16), wenn in den verarbeiteten IQ-Daten mit Bezug auf den ersten Signalverarbeitungsparameter ein Auslöseereignis auftritt, dadurch Auslösen eines zweiten digitalen Signalprozessors (22) via das Auslösesignal, um IQ-Daten zu erfassen, die von einer IQ-Datenquelle (14) erhalten werden, und

    - Erfassen von IQ-Daten via den zweiten digitalen Signalprozessor (22), der einen zweiten Signalverarbeitungsparameter berücksichtigt, der vom ersten Signalverarbeitungsparameter unabhängig ist.


     


    Revendications

    1. Système de déclenchement numérique (10) pour traiter des données relatives à un signal reçu, comprenant :

    - un convertisseur analogique-numérique (12) pour convertir un signal d'entrée analogique en un signal numérique,

    - une source de données en phase et en quadrature de phase, IQ, (14) fournissant des données IQ,

    - un premier processeur de signal numérique (16) situé en aval de ladite source de données IQ (14), et

    - au moins un deuxième processeur de signal numérique (22) situé en aval de ladite source de données IQ (14),

    ledit premier processeur de signal numérique (16) étant connecté avec ladite source de données IQ (14) via un premier chemin de signal (20) de sorte que ledit premier processeur de signal numérique (16) obtienne les données IQ fournies par ladite source de données IQ (14),

    ledit deuxième processeur de signal numérique (22) étant connecté avec ladite source de données IQ (14) via un deuxième chemin de signal (24) de sorte que ledit deuxième processeur de signal numérique (22) obtienne les données IQ fournies par ladite source de données IQ (14),

    ledit premier processeur de signal numérique (16) ayant au moins un premier paramètre de traitement de signal et ledit deuxième processeur de signal numérique (22) ayant au moins un deuxième paramètre de traitement de signal, ledit premier paramètre de traitement de signal et ledit deuxième paramètre de traitement de signal étant indépendants l'un de l'autre,

    ledit premier processeur de signal numérique générant un signal de déclenchement basé sur une caractéristique des données IQ obtenue à partir de ladite source de données IQ (14), et

    ledit premier processeur de signal numérique (16) déclenchant ledit deuxième processeur de signal numérique (22) via ledit signal de déclenchement pour acquérir des données IQ obtenues à partir de ladite source de données IQ (14).


     
    2. Système de déclenchement numérique (10) selon la revendication 1, dans lequel ledit premier processeur de signal numérique (16) et ledit deuxième processeur de signal numérique (22) ont des paramètres de traitement de signal différents.
     
    3. Système de déclenchement numérique (10) selon la revendication 1 ou 2, dans lequel ledit premier processeur de signal numérique (16) et ledit deuxième processeur de signal numérique (22) sont configurés pour capturer le signal reçu sur différentes parties du spectre du signal.
     
    4. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel ledit premier processeur de signal numérique (16) acquiert également des données IQ obtenues à partir de ladite source de données IQ (14), en particulier dans lequel lesdites données IQ acquises par ledit premier processeur de signal numérique (16) et lesdites données IQ acquises par ledit deuxième processeur de signal numérique (22) se rapportent à différentes parties du spectre dudit signal reçu.
     
    5. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel ledit premier processeur de signal numérique (16) et ledit deuxième processeur de signal numérique (22) sont connectés l'un à l'autre via une ligne de déclenchement (26) via laquelle ledit premier processeur de signal numérique (16) transmet ledit signal de déclenchement audit deuxième processeur de signal numérique (22).
     
    6. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel ledit premier chemin de signal (20) et ledit deuxième chemin de signal se ramifient tous deux (24) à partir d'un ligne de chemin de signal (18) commune connectée à ladite source de données IQ (14).
     
    7. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel ledit premier processeur de signal numérique (16) utilise un déclenchement dans le domaine fréquentiel, un déclenchement dans le domaine temporel, un déclenchement dans le domaine de phase, un déclenchement dans le domaine de la modulation et/ou un déclenchement dans le domaine de la démodulation.
     
    8. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel on fournit un stockage intermédiaire temporaire (30) pour des données IQ qui sont attribuées audit premier processeur de signal numérique (16) et/ou audit deuxième processeur de signal numérique (22).
     
    9. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel on fournit une interface utilisateur (32) via laquelle un utilisateur est autorisé à effectuer des réglages dudit premier processeur de signal numérique (16) et/ou dudit deuxième processeur de signal numérique (22).
     
    10. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel l'acquisition de données IQ via ledit deuxième processeur de signal numérique (22) peut être décalée en définissant un décalage.
     
    11. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel l'acquisition de données IQ via ledit deuxième processeur de signal numérique (22) est lancée avant un événement de déclenchement.
     
    12. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel ledit système de déclenchement numérique (10) comprend un module de mesure (34), ledit module de mesure (34) fournissant une analyse supplémentaire, en particulier dans lequel ledit module de mesure (34) est attribué audit deuxième chemin de signal (24) pour analyser davantage les données IQ traitées par ledit deuxième chemin de signal (24) et/ou ledit deuxième processeur de signal numérique (22).
     
    13. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel une mémoire d'acquisition (28) pour données IQ est fournie pour stocker les données IQ acquises, ladite mémoire d'acquisition (28) étant connectée avec ledit premier processeur de signal numérique (16) et/ou ledit deuxième processeur de signal numérique (22).
     
    14. Système de déclenchement numérique (10) selon l'une quelconque des revendications précédentes, dans lequel l'au moins un deuxième processeur de signal numérique (22) correspond à un stade du système de déclenchement numérique (10), le système de déclenchement numérique (10) comprenant plusieurs stades qui reçoivent ledit signal de déclenchement à partir dudit premier processeur de signal numérique (16).
     
    15. Procédé pour traiter des données, comprenant les étapes suivantes :

    - convertir un signal analogique en un signal numérique,

    - obtenir des données en phase et en quadrature de phase, IQ, à partir dudit signal numérique,

    - traiter les données IQ obtenues alors qu'un premier paramètre de traitement de signal est pris en compte par un premier processeur de signal numérique (16),

    - générer un signal de déclenchement via ledit premier processeur de signal numérique (16) lorsqu'un événement de déclenchement se produit dans les données IQ traitées en ce qui concerne ledit premier paramètre de traitement de signal, déclenchant ainsi un deuxième processeur de signal numérique (22) via ledit signal de déclenchement pour acquérir des données IQ obtenue à partir d'une source de données IQ (14), et

    - acquérir des données IQ via ledit deuxième processeur de signal numérique (22) qui prend un deuxième paramètre de traitement de signal en compte qui est indépendant dudit premier paramètre de traitement de signal.


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description