(19)
(11)EP 3 605 839 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
13.01.2021 Bulletin 2021/02

(21)Application number: 18186506.4

(22)Date of filing:  31.07.2018
(51)International Patent Classification (IPC): 
H03B 5/12(2006.01)

(54)

IMPROVEMENTS IN OR RELATING TO COLPITTS OSCILLATORS

VERBESSERUNGEN AN ODER IM ZUSAMMENHANG MIT COLPITTS-OSZILLATOREN

PERFECTIONNEMENTS APPORTÉS OU SE RAPPORTANT À DES OSCILLATEUR COLPITTS


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
05.02.2020 Bulletin 2020/06

(73)Proprietor: Stichting IMEC Nederland
5656 AE Eindhoven (NL)

(72)Inventors:
  • MATEMAN, Paul
    3001 Leuven (BE)
  • ZHOU, Cui
    3001 Leuven (BE)

(74)Representative: Gevers Patents 
Intellectual Property House Holidaystraat 5
1831 Diegem
1831 Diegem (BE)


(56)References cited: : 
US-A1- 2011 273 239
US-A1- 2018 175 796
US-A1- 2016 099 679
US-B1- 9 425 737
  
  • CHEN JUN ET AL: "A low-voltage high-swing colpitts VCO with Inherent tapped capacitors based dynamic body bias technique", 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE, 28 May 2017 (2017-05-28), pages 1-4, XP033156045, DOI: 10.1109/ISCAS.2017.8050374 [retrieved on 2017-09-25]
  • C Bender: "IEEE TRANSACTIONS ON CIRCUITS AND Express Letters I Capacitive Ladder Networks", , 31 January 1994 (1994-01-31), page 557, XP055541713, Retrieved from the Internet: URL:https://ieeexplore.ieee.org/ielx5/81/7 552/00311548.pdf?tp=&arnumber=311548&isnum ber=7552 [retrieved on 2019-01-14]
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Field of the disclosure



[0001] The present disclosure relates to improvements in or relating to Colpitts oscillators, and, is more particularly concerned with providing a reduced power supply voltage which is independent of threshold voltages of transistors in such oscillators.

Background of the disclosure



[0002] Switched resonator oscillators, transformer-based oscillators and mode-switching oscillators are widely implemented in phase-locked loop (PLL) circuits which are widely used for many applications including multimode, multi-band applications. However, whilst it is possible to improve the phase noise and tuning range trade-off using such oscillators, there is no improvement in the trade-off between tuning range and die area.

[0003] Noise-shifting differential Colpitts voltage-controlled oscillators (VCOs) have been proposed by Roberto Aparicio et al. in "A Noise-Shifting Differential Colpitts VCO" (IEEE Journal of Solid-State Circuits, Vol,. 37, No, 12, December 2002), referred to hereinafter as "Aparicio et al.", in which current switching is used to lower phase noise and improve the start-up condition. The oscillator topology utilizes cyclostationary noise alignment while providing a fully differential output and a large loop gain for reliable start-up. Two identical Colpitts oscillators are coupled together so that they share their source-to-ground capacitors. The centre node forms a differential virtual ground and is left floating with the operation of each oscillator remaining unchanged when each side oscillates 180° out of phase.

[0004] A low-voltage differential Colpitts VCO is described in "A 0.5V, 2.41GHz, 196.3dBc/Hz FoM Differential Colpitts VCO with an Output Voltage Swing Exceeding Supply and Ground Potential Requiring No Additional Inductor" (Joo-Myoung Kim et al., 2013 IEEE Radio Frequency Integrated Circuits Symposium, 978-1-4673-6062-3/13), referred to hereinafter as "Kim et al.", in which a differential Colpitts oscillator with low phase noise and small chip area is proposed. Enhanced output voltage swing is obtained above the supply voltage and below the ground potential by the combination of the differential output at the gate nodes of feedback transistors and capacitive dividers without requiring an additional inductor.

[0005] Whilst Aparicio et al. and Kim et al. describe circuits which reduce phase noise, increased tuning range is not addressed. In the article "Tuning Range Extension of a Transformer-Based Oscillator through Common-Mode Colpitts Resonance" by Mina Shahmohammadi et al. (IEEE Transactions on Circuits and Systems - 1: Regular Papers, Volume 64, No. 4, April 2017), referred to hereinafter as "Shahmohammadi et al.", a method of extending a tuning range of a CMOS LC-tank oscillator is described without sacrificing its area. The extra tuning range is obtained by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than its main differential-mode oscillation. Four inductors are coupled through four switching transistors to form two separate active circuits, sharing the same tank. The transformer-based tank is forced to oscillate either in a differential mode or a common mode. The tank is forced into common-mode oscillation by two injection locked Colpitts oscillators at the primary winding of the transformer while a two-port structure provides differential-mode oscillation. The oscillator is switched between resonant modes.

[0006] However, although tuning range can be extended in the circuit described by Shahmohammadi et al., phase noise in the common mode of the oscillator circuit is not improved.

[0007] US-A-2011/0273239 discloses a dual positive-feedbacks voltage controlled oscillator which includes an oscillation circuit and a cross coupled pair circuit. The oscillation circuit includes first and second transistors, and inductor and a plurality of capacitors which forms an LC tank. The gates of the first and second transistors are opposite one another and coupled to two points of the inductor. First and second capacitors of the LC tank are connected respectively to first and second outputs of the oscillation circuit and to the sources of respective ones of the first and second transistors. The cross coupled pair circuit includes third and fourth transistors which are cross coupled to two points of the inductor with respective gates of the third and fourth transistors being coupled to respective gates of the second and first transistors and respecitive drains of the third and fourth transistors being coupled to the sources of respective ones of the first and second transistors with the sources of the third and fourth transistors being groundec.

[0008] US 9 425 737 B1 discloses an example of an oscillator using a tapped inductor pair between the gates of two upper transistors.

[0009] There is therefore a need to provide an oscillator circuit which has both extended tuning range and reduced phase noise.

[0010] In addition, there is a need to maintain a positive feedback voltage while tuning the oscillation frequency of the oscillator circuit so that oscillation is maintained after start-up.

Summary of the disclosure



[0011] It is an object of the present disclosure to provide an improved differential Colpitts oscillator circuit which provides extended tuning range without reduced noise performance.

[0012] It is another object of the present disclosure to provide an improved differential Colpitts oscillator which maintains a positive feedback voltage while tuning the oscillation frequency of the oscillator circuit.

[0013] In accordance with one aspect of the present disclosure, there is provided a differential Colpitts oscillator circuit comprising:

a first transistor pair having a first tap point between a source of one transistor and a drain of the other transistor;

a first power supply connected to a first transistor of the first transistor pair;

a first inductor connected in a first line between a gate of the first transistor of the first transistor pair and a connecting point;

a second transistor pair having a second tap point between a source of one transistor and a drain of the other transistor;

a second power supply connected to a first transistor of the second transistor pair;

a second inductor connected in a second line between a gate of the first transistor of the second transistor pair and the connecting point;

a first variable capacitor connected in a third line between the first and second tap points; and

a resistor connected to a second transistor of the first transistor pair and to a second transistor of the second transistor pair, the resistor also being connected to a ground point;

characterized in that a gate of the second transistor of the second transistor pair is connected to a first tap point of the first inductor and a gate of the second transistor of the first transistor pair is connected to a second tap point of the second inductor.



[0014] By effectively cross-coupling the gates of the second transistors in the first and second transistor pairs with respective ones of the second and first inductors, it is possible to avoid large voltage swings at the transistors.

[0015] In an embodiment, the first and second tap points comprise centre-tap points.

[0016] By using centre-tap points of the first and second inductors, it is possible to reduce the minimum power supply voltage and bias voltage for the oscillator circuit.

[0017] In addition, each of the transistors in the first and second transistor pairs has the same size thereby providing a simpler circuit layout.

[0018] In an embodiment, the oscillator circuit comprises a voltage divider connected between the third line and between the gate of the first transistor of the first transistor pair and between the gate of the first transistor of the second transistor pair, the variable capacitor forming part of the voltage divider.

[0019] By having a capacitive ladder within the differential Colpitts oscillator circuit of the present disclosure, it is possible to increase the oscillation frequency range without compromising phase noise performance, area or power whilst still having the benefits of being able to avoid large voltage swings at the transistors and to reduce the minimum power supply voltage and bias voltage for the oscillator circuit.

[0020] The voltage divider may comprise at least a first pair of capacitors connected between the gate of the first transistor of the first transistor pair in the first line and the first tap point in the third line, at least a second pair of capacitors connected between the gate of the first transistor of the second transistor pair in the second line and the second tap point in the third line, and a second variable capacitor connected between intermediate points of the first and second capacitor pairs of capacitors and configured for determining tuning range of the circuit.

[0021] Such an arrangement enables both extension of tuning range by tuning the second variable capacitor and fine tuning of the oscillator circuit using the first variable capacitor.

[0022] By tuning only the second variable capacitor, there is less impact on the feedback voltage for the oscillator.

Brief description of the drawings



[0023] For a better understanding of the present disclosure, reference will now be made, by way of example, to the accompanying drawings in which:-

Figure 1 is a schematic illustration of a conventional single-ended Colpitts oscillator circuit;

Figure 2 is a schematic illustration of a conventional differential Colpitts oscillator circuit not covered by the present invention;

Figure 3 is a schematic illustrates of another conventional differential Colpitts oscillator circuit not covered by the present invention;

Figure 4 illustrates voltage swing at gates of transistors M3 and M4 of the circuit shown in Figure 3;

Figure 5 illustrates voltages across transistors M3 and M4 of the circuit shown in Figure 3;

Figure 6 is a schematic illustration of a differential Colpitts oscillator circuit with low power supply voltage having a low power supply in accordance with an embodiment of the present invention;

Figure 7 is similar to Figure 4 but for the circuit shown in Figure 6;

Figure 8 is similar to Figure 5 but for the circuit shown in Figure 6;

Figure 9 is a schematic illustration of a differential Colpitts oscillator circuit in accordance with another embodiment of the present invention; and

Figure 10 is a schematic illustration of a single-ended equivalent capacitive ladder or voltage divider forming part of the circuit of Figure 9.


Description of the disclosure



[0024] The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto. The drawings described are only schematic and are nonlimiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.

[0025] A conventional single-ended Colpitts oscillator circuit 10 is shown in Figure 1 and comprises first and second capacitors C1, C2, a resistor R, and an inductor L connected between a supply voltage VDD and ground 12. A transistor 14 is provided for applying a bias 16 to the circuit 10. A capacitive voltage divider is formed by the first and second capacitors C1 and C2 which provides a positive feedback path. The inductor L and the capacitive voltage divider formed by the first and second capacitors, C1 and C2, together form an oscillation tank.

[0026] The single-ended Colpitts oscillator circuit 10 has lower phase noise than most other oscillator topologies or circuits, and, its use is preferred in implementations where phase noise is an issue. However, the circuit 10 is sensitive to single-ended parasitics.

[0027] Figure 2 is a schematic illustration of a conventional differential Colpitts oscillator circuit 20. The circuit 20 can be considered to comprise two portions 20a, 20b corresponding to two identical single-ended Colpitts oscillators which are joined by a variable or tunable capacitor C2 at centre-tap points 24a, 24b with cross-connections between transistors as described below.

[0028] Portion 20a comprises transistors M1 and M3 where transistor M1 corresponds to transistor 14 in Figure 1. A bias 26a is applied to transistor M3. As shown, a capacitor C1a is positioned across transistor M1 and is connected to the line joining centre-tap points 24a, 24b containing the variable or tunable capacitor C2. Inductor La is connected to power supply VDD and to transistor M1. Transistor M3 is connected to ground 22.

[0029] Similarly, portion 20b comprises transistors M2 and M4 where transistor M2 corresponds to transistor 14 in Figure 1. A bias 26b is applied to transistor M2. As shown, a capacitor C1b is positioned across transistor M2 and is connected to the line joining centre-tap points 24a, 24b containing the variable or tunable capacitor C2. Inductor Lb connected to power supply VDD and to transistor M2. Transistor M4 is connected to ground 22.

[0030] The centre-tap points 24a, 24b are located between respective ones of the transistor pairs M1, M3 and M2, M4. The variable or tunable capacitor C2 is connected to a line joining the centre-tap points 24a, 24b.

[0031] Connections are provided between the respective transistor pairs M1, M3 and M2, M4 and respective gates of transistor M4 and transistor M3 as shown. The connections are made at points 28a and 28b with respect to respective ones of the transistor pairs M1, M3 and M2, M4. A differential output is provided by coupling the two portions 20a, 20b by sharing variable or tunable capacitor C2.

[0032] The differential Colpitts oscillator circuit 20 has the advantage of having low phase noise which is the same as the single-ended Colpitts oscillator circuit as shown in Figure 1. However, although the phase noise has not been increased, the circuit 20 is insensitive to common-mode parasitics and common-mode interferences.

[0033] Another conventional differential Colpitts oscillator circuit 30 not covered by the present invention; is shown in Figure 3. This circuit is similar to that described by Kim et al. as discussed above. As before, the circuit 30 can be considered to comprise two portions 30a, 30b corresponding to two identical single-ended Colpitts oscillators which are joined by a variable or tunable capacitor C2 at tap points 36a, 36b with cross-connections between transistors as described below.

[0034] Portion 30a comprises transistors M1 and M3 and a capacitor C1a connected between line 42a extending between a bias voltage node 40 and gate aa of transistor M1 and line 44 joining centre-tap points 36a, 36b containing the variable or tunable capacitor C2. Transistor M1 is connected to voltage supply VDD as shown with transistor M3 connected to ground 32 via resistor 34. Inductor La is connected in the line 42a between the bias voltage node 40 and gate aa of transistor M1. Gate a of transistor M3 is connected to line 42b at tap point 38b as shown.

[0035] Similarly, portion 20b comprises transistors M2 and M4 and a capacitor C1b between line 42b extending between the bias voltage node 40 and gate bb of transistor M2 and line 44 joining centre-tap points 36a, 36b containing the variable or tunable capacitor C2. Transistor M2 is connected to voltage supply VDD as shown with transistor M4 connected to ground 32 via resistor 34. Inductor Lb connected in the line 42b between the bias voltage node 40 and gate bb of transistor M2. Gate b of transistor M4 is connected to line 42a at tap point 38a as shown.

[0036] The tap points 36a, 36b are located between respective ones of the transistor pairs M1, M3 and M2, M4. The variable or tunable capacitor C2 is connected to a line joining the centre-tap points 36a, 36b.

[0037] A differential output is provided by coupling the two portions 30a, 30b by sharing variable or tunable capacitor C2.

[0038] However, by cross-coupling the transistors M3 and M4, it was found that the minimum supply voltage VDD was equal to the sum of the drain/source voltage Vds for transistor M1 and the threshold voltage Vth for transistor M3. Typically, the minimum power supply voltage needs to be -0.7V. Moreover, transistors M1 and M2 need to be large so that they can be fully switched by the bias voltage applied at bias voltage node 40.

[0039] The conventional way of realizing the tuning range is to tune the variable or tunable capacitor C2. When the capacitance of C2 increases, the oscillation frequency is reduced as the total capacitance Ctotal increases. The oscillation frequency/can be expressed as:

where

and C1, C2 and L respectively correspond to the capacitance value of C1, the capacitance value of C2 and the inductance of the inductor L.

[0040] The feedback voltage V2 can be expressed as:

where V1 is the power supply voltage VDD, and C1 and C2 are the capacitance values of the capacitors C1 and C2 respectively.

[0041] If the feedback voltage V2 decreases below a threshold value, start-up requirements for the oscillator cannot be met. The minimum power supply voltage VDD is limited by the sum of Vth (from transistor M3) and Vds (from transistor M1). The minimum bias voltage is limited by the sum of Vth (from transistor M1), Vth (from transistor M3) and Vds (from the resistor 34).

[0042] The limited tuning range is the main bottle neck for Colpitts oscillator implementation, and, the main problem is how to extend the tuning range without compromising on area, design complexity and phase noise.

[0043] When the capacitance C2 increases, the oscillation frequency and the feedback voltage V2 decrease, and, the positive feedback cannot sustain the oscillation. The difficulty is to maintain the positive feedback voltage while tuning the oscillation frequency.

[0044] Figure 4 illustrates plots of the voltage at gate aa of transistor M1 (line 50), the voltage at gate a of transistor M3 (line 52), and the bias voltage (line 54) applied to the bias node 40 for circuit 30 shown in Figure 3. It will be appreciated that the voltages are the same for gate bb of transistor M2 and gate b of transistor M4 as transistors M2 and M4 are identical to transistors M1 and M3.

[0045] Figure 5 illustrates plots of the transistor voltages for transistors M1 and M3 for the circuit 30 shown in Figure 3. The transistor voltages for transistors M2 and M4 are identical to respective ones of those for transistors M1 and M3. The gate/source voltage Vgs and the gate/drain voltage Vds for transistor M3 are shown by lines 60 and 62 respectively. The gate/source voltage Vgs and the gate/drain voltage Vgd for transistor M1 are shown by lines 64 and 66 respectively. It can be seen that the Vgs for transistor M3 is twice that of the Vgs for transistor M1 but the Vgd voltages are approximately the same for transistors M1 and M3. As a result of the difference in Vgs for transistors M3 and M1, transistor M3 can easily be destroyed by a high voltage swing.

[0046] A schematic illustration of a differential Colpitts oscillator circuit 10 according to the present invention is shown in Figure 6 which illustrates how a low power supply voltage may be implemented to address the issues with circuit 30 shown in Figure 3 and described with reference to Figures 4 and 5 above. The circuit 100 is similar to that shown in Figure 3 and comprises two portions 110, 120. Each portion 110, 120 comprises its own power supply VDD with variable or tunable capacitor C2 being shared therebetween as before. Portion 110 includes transistor M1 and transistor M3 connected in series with a resistor R to ground 130, and inductor La connected to gate aa of transistor M1. The inductor La is connected between the gate aa of transistor M1 and point 140 to which a bias voltage Vbias can be applied as shown.

[0047] Similarly, portion 120 includes transistor M2 and transistor M4 connected in series with the resistor R to ground 130 and inductor L connected to gate bb of transistor M2. The inductor Lb is connected between gate bb of transistor M2 and the point 140 to which the bias voltage Vbias can be applied as shown.

[0048] Variable or tunable capacitor C2 is connected between each of the transistor pairs M1, M3 and M2, M4 as shown at tap points 150, 160. Capacitor C1a in portion 110 is connected to line 170 between inductor La and gate aa of transistor M1 at one end and to line 180 between tap points 150, 160, including the variable or tunable capacitor C2, at the other end. Similarly, capacitor C1 in portion 120 is connected to line 180 between inductor Lb and gate bb of transistor M2 at one end and to line 190 between tap points 150, 160 at the other end.

[0049] Gate a of transistor M4 is connected to a centre-tap point A of the inductor La in the other portion 110 of the circuit 100, and, gate b of transistor M3 is connected to a centre-tap point B of the inductor Lb in the other portion 120 of the circuit 100, that is, the inductors La, Lb are crosscoupled with the gates a, b of transistors M3, M4 as shown.

[0050] The advantages of having the centre-tapped connection to points A and B of respective inductors La and Lb are shown in Figures 7 and 8.

[0051] Figure 7 is similar to Figure 4 but illustrates the plots for the voltages at gate aa of transistor M1 (line 70), at gate a of transistor M4 (line 72), at gate b of transistor M3 (line 74) and the bias voltage applied to point 140 (line 76). As will readily be understood, the plots of the voltage at gate bb of transistor M2 will be identical to that shown by line 70.

[0052] Figure 8 is similar to Figure 5 illustrating the voltages for transistors M1 and M3. As before, the transistor voltages for transistors M2 and M4 are identical to respective ones of those for transistors M1 and M3. The gate/source voltage Vgs and the gate/drain voltage Vds for transistor M3 are shown by lines 80 and 82 respectively. The gate/source voltage Vgs and the gate/drain voltage Vgd for transistor M1 are shown by lines 84 and 86 respectively. It can be seen that both the Vgs and Vgd values for transistor M3 are now similar to those for transistor M1, and, transistor M3 will no longer be destroyed by high voltage swings. This means that the size of transistors M1 and M3 can be the same thereby saving area.

[0053] The minimum bias voltage applied to point 140 is now no longer dependent on threshold voltage Vth, and, is now determined by the sum of Vds (for transistor M1) and Vds (for transistor M3). This provides an improvement of between around 100mV to 200mV. The voltage swing at gates aa, bb of respective transistors M1, M2 is much higher than that at sources of the associated transistors. As a result, the size of the transistors M3, M4 can be reduced, and an improved layout is achieved for the transistors M1, M2, M3 and M4.

[0054] Tuning can be improved using a Colpitts oscillator circuit 200 according to the present invention; shown in Figure 9. The circuit 200 is similar to that shown in Figure 3 but includes a capacitive ladder or voltage divider 300. As before, the circuit 200 comprises two portions 210, 220 each comprising its own power supply VDD with a variable capacitor C2' shared therebetween as before.

[0055] Portion 210 includes transistor M1 and transistor M3 connected in series with a resistor R to ground 230, and inductor La connected to gate aa of transistor M1. The inductor La is connected between gate aa of transistor M1 and point 240 to which a bias voltage Vbias can be applied as shown.

[0056] Similarly, portion 220 includes transistor M2 and transistor M4 connected in series with the resistor R to ground 230 and inductor Lb connected to gate bb of transistor M2. The inductor Lb is connected between gate bb of transistor M2 and the point 240 to which the bias voltage Vbias can be applied as shown.

[0057] Gate a of transistor M4 is connected to a centre-tap point A of the inductor La in the other portion 210 of the circuit 200, and, gate b of transistor M3 is connected to a centre-tap point B of the inductor Lb in the other portion 220 of the circuit 200, that is, the inductors La, Lb are crosscoupled with the gates a, b of transistors M3, M4 as shown.

[0058] Variable capacitor C2' is connected between each of the transistor pairs M1, M3 and M2, M4 as shown at tap points 250, 260. Instead of having a single capacitor C1a, C1b in each portion 210, 220 of the circuit 200, the single capacitor C1a, C1b is replaced by capacitors C1a, C1b and C3a, C3b arranged in series between line 270 and line 280 in portion 210 and between line 290 and line 280 in portion 220 as shown.

[0059] The capacitive ladder or voltage divider 300 comprises capacitors C1a, C1b and C3a, C3b in each of portions 210, 220 and a tunable capacitor Ctune' connected between tap point 310 in portion 210 and tap point 320 in portion 220 of circuit 200. The capacitance of capacitors C1a, C1b and C3a, C3b are and C3 respectively (as capacitors C1a and C1b are identical, and, capacitors C3a and C3b are identical) with the capacitance of capacitor Ctune' as Ctune/2 and the capacitance of capacitor C2' as C2/2. As there are now two variable or tunable capacitors C2' and Ctune' in parallel, the capacitance value of each capacitor C2' and Ctune' is now halved.

[0060] By using the centre-tapped configuration of Figure 6 with the capacitive ladder or voltage divider 300, an increased tuning range can be achieved whilst maintaining a low power supply voltage and protecting the transistors as the threshold voltage Vth is no longer relevant for determining the power supply voltage.

[0061] Figure 10 illustrates the effect of the capacitive ladder or voltage divider 300 where the effective capacitance thereof is Ctotal. Only one end of of the capacitive ladder is shown which with the other end, provides a total effective capacitance of Ctotal.

[0062] In contrast to Figure 6, the capacitive voltage divider 300 of Figure 9 provides positive feedback for the circuit 200.

[0063] The total equivalent capacitance Ctotal of the capacitive voltage divider 300 can be expressed as:



[0064] As can be seen from equation (2), the capacitance values C2 and Ctune have equal impact on the total capacitance Ctotal. In equation (2) above, C2 and Ctune correspond to C2' and Ctune' respectively as shown in Figure 9.

[0065] The positive feedback voltage can be calculated as:

with the denominator being simplified to:

where the capacitance C2 has the coefficient of the sum of capacitances C1 + C3 and the capacitance Ctune has the coefficient of the capacitance C3 where C2 and Ctune in equation (3) correspond to C2' and Ctune' respectively as shown in Figure 9. This means that the capacitance Ctune' has less impact on the feedback voltage. When comparing whether C2' and Ctune' should be tuned to determine which one would be more effective, for example, if C2' is tuned 10% more, then the denominator as expressed in equation (3) would become

and, if, Ctune' is tuned 10% more, then the denominator as expressed in equation (3) would become



[0066] As a result, positive feedback voltage changes when Ctune' is tuned are smaller than those when C2' is tuned.

[0067] Although the capacitor C2' is a variable capacitor, it is proposed to use only capacitor Ctune' to effect the frequency tuning; but fine-tuning of the oscillator circuit can be achieved by tuning capacitor C2'.

[0068] The term "fine-tuning" as used herein refers to making small precise adjustments in order to achieve the best or desired performance. This is in contrast to the term "tuning" which provides larger less precise adjustments.


Claims

1. A differential Colpitts oscillator circuit (100; 200) comprising:

a first transistor pair (M1, M3) having a first tap point (150; 250) between a source of one transistor (M1) and a drain of the other transistor (M3);

a first power supply (VDD) connected to a first transistor (M1) of the first transistor pair (M1, M3);

a first inductor (La) connected in a first line (170; 270) between a gate (aa) of the first transistor (M1) of the first transistor pair (M1, M3) and a connecting point (140; 240);

a second transistor pair (M2, M4) having a second tap point (160; 260) between a source of one transistor (M2) and a drain of the other transistor (M4);

a second power supply (VDD) connected to a first transistor (M2) of the second transistor pair (M2, M4);

a second inductor (Lb) connected in a second line (190; 290) between a gate (bb) of the first transistor (M2) of the second transistor pair (M2, M4) and the connecting point (140; 240);

a first variable capacitor (C2; C2') connected in a third line (180; 280) between the first and second tap points (150, 160; 250, 260); and

a resistor (R) connected to a second transistor (M3) of the first transistor pair (M1, M3) and to a second transistor (M4) of the second transistor pair (M2, M4), the resistor also being connected to a ground point (130; 230);

characterized in that a gate (a) of the second transistor (M4) of the second transistor pair (M2, M4) is connected to a first tap point (A) of the first inductor (La) and a gate (b) of the second transistor (M3) of the first transistor pair (M1, M3) is connected to a second tap point (B) of the second inductor (Lb).


 
2. A circuit according to claim 1, wherein the first and second tap points (A, B) comprise centre-tap points.
 
3. A circuit according to claim 1 or 2, further comprising a capacitive voltage divider (300) connected between the third line (280) and a line between the gate (aa) of the first transistor (M1) of the first transistor pair (M1, M3) and between the gate (bb) of the first transistor (M2) of the second transistor pair (M2, M4), the variable capacitor (C2') forming part of the capacitive voltage divider.
 
4. A circuit according to claim 3, wherein the voltage divider (300) comprises:

at least a first capacitor pair (C1a, C3a) connected between the gate (aa) of the first transistor (M1) of the first transistor pair (M1, M3) in the first line (270) and the first tap point (250) in the third line (280);

at least a second capacitor pair (C1b, C3b) connected between the gate (bb) of the first transistor (M2) of the second transistor pair (M2, M4) in the second line (290) and the second tap point (260) in the third line (280); and

a second variable capacitor (Ctune') connected between intermediate points (310, 320) of the first and second capacitor pairs (C1a, C3a, C1b, C3b) and configured for determining tuning range of the circuit.


 
5. A circuit according to claim 4, wherein the first variable capacitor (C2') is configured for fine-tuning the circuit.
 


Ansprüche

1. Eine differentielle Colpitts-Oszillator-Schaltung (100; 200), welche Folgendes umfasst:

ein erstes Transistorpaar (M1, M3) mit einer ersten Abgriffstelle (150; 250) zwischen einer Quelle eines Transistors (M1) und einem Drain des anderen Transistors (M3);

eine erste Stromversorgung (VDD) verbunden mit einem ersten Transistor (M1) des ersten Transistorpaares (M1, M3);

einen ersten Induktor (La) verbunden in einer ersten Leitung (170; 270) zwischen einem Gate (aa) des ersten Transistors (M1) des ersten Transistorpaares (M1, M3) und einer Verbindungsstelle (140; 240);

ein zweites Transistorpaar (M2, M4) mit einer zweiten Abgriffstelle (160; 260) zwischen einer Quelle eines Transistors (M2) und einem Drain des anderen Transistors (M4);

eine zweite Stromversorgung (VDD) verbunden mit einem ersten Transistor (M2) des zweiten Transistorpaares (M2, M4);

einen zweiten Induktor (Lb) verbunden in einer zweiten Leitung (190; 290) zwischen einem Gate (bb) des ersten Transistors (M2) des zweiten Transistorpaares (M2, M4) und der Verbindungsstelle (140; 240);

einen ersten variablen Kondensator (C2; C2') verbunden in einer dritten Leitung (180; 280) zwischen der ersten und der zweiten Abgriffstelle (150, 160; 250, 260); und

einen Widerstand (R) verbunden mit einem zweiten Transistor (M3) des ersten Transistorpaares (M1, M3) und mit einem zweiten Transistor (M4) des zweiten Transistorpaares (M2, M4), wobei der Widerstand auch mit einem Massepunkt (130; 230) verbunden ist;

dadurch gekennzeichnet, dass ein Gate (a) des zweiten Transistors (M4) des zweiten Transistorpaares (M2, M4) mit einer ersten Abgriffstelle (A) des ersten Induktors (La) verbunden ist und ein Gate (b) des zweiten Transistors (M3) des ersten Transistorpaares (M1, M3) mit einer zweiten Abgriffstelle (B) des zweiten Induktors (Lb) verbunden ist.


 
2. Eine Schaltung nach Anspruch 1, wobei die erste und die zweite Abgriffstelle (A, B) Mittelabgriffstellen umfassen.
 
3. Eine Schaltung nach Anspruch 1 oder 2, welche ferner einen kapazitiven Spannungsteiler (300) umfasst, verbunden zwischen der dritten Leitung (280) und einer Leitung zwischen dem Gate (aa) des ersten Transistors (M1) des ersten Transistorpaares (M1, M3) und zwischen dem Gate (bb) des ersten Transistors (M2) des zweiten Transistorpaares (M2, M4), wobei der variable Kondensator (C2') Teil des kapazitiven Spannungsteilers ist.
 
4. Eine Schaltung nach Anspruch 3, wobei der Spannungsteiler (300) Folgendes umfasst:

zumindest ein erstes Kondensatorpaar (C1a, C3a) verbunden zwischen dem Gate (aa) des ersten Transistors (M1) des ersten Transistorpaares (M1, M3) in der ersten Leitung (270) und der ersten Abgriffstelle (250) in der dritten Leitung (280);

zumindest ein zweites Kondensatorpaar (C1b, C3b) verbunden zwischen dem Gate (bb) des ersten Transistors (M2) des zweiten Transistorpaares (M2, M4) in der zweiten Leitung (290) und der zweiten Abgriffstelle (260) in der dritten Leitung (280); und

einen zweiten variablen Kondensator (Ctune') verbunden zwischen Zwischenpunkten (310, 320) des ersten und des zweiten Kondensatorpaares (C1a, C3a, C1b, C3b) und konfiguriert, um den Abstimmbereich der Schaltung festzulegen.


 
5. Eine Schaltung nach Anspruch 4, wobei der erste variable Kondensator (C2') konfiguriert ist, um die Schaltung feinabzustimmen.
 


Revendications

1. Circuit d'oscillateur Collpitts différentiel (100 ; 200) comprenant :

une première paire de transistors (M1, M3) présentant un premier point de branchement (150 ; 250) entre une source d'un transistor (M1) et un drain de l'autre transistor (M3) ;

une première alimentation électrique (VDD) connectée à un premier transistor (M1) de la première paire de transistors (M1, M3) ;

une première bobine d'induction (La) connectée dans une première ligne (170 ; 270) entre une grille (aa) du premier transistor (M1) de la première paire de transistors (M1, M3) et un point de connexion (140 ; 240) ;

une seconde paire de transistors (M2, M4) présentant un second point de branchement (160 ; 260) entre une source d'un transistor (M2) et un drain de l'autre transistor (M4) ;

une seconde alimentation électrique (VDD) connectée à un premier transistor (M2) de la seconde paire de transistors (M2, M4) ;

une seconde bobine d'induction (Lb) connectée dans une deuxième ligne (190 ; 290) entre une grille (bb) du premier transistor (M2) de la seconde paire de transistors (M2, M4) et le point de connexion (140 ; 240) ;

un premier condensateur variable (C2 ; C2') connecté dans une troisième ligne (180; 280) entre les premier et second points de branchement (150, 160 ; 250, 260) ; et

une résistance (R) connectée à un second transistor (M3) de la première paire de transistors (M1, M3) et à un second transistor (M4) de la seconde paire de transistors (M2, M4), la résistance étant également connectée à un point de masse (130 ; 230) ;

caractérisé en ce qu'une grille (a) du second transistor (M4) de la seconde paire de transistors (M2, M4) est connectée à un premier point de branchement (A) de la première bobine d'induction (La) et qu'une grille (b) du second transistor (M3) de la première paire de transistors (M1, M3) est connectée à un second point de branchement (B) de la seconde bobine d'induction (Lb).


 
2. Circuit selon la revendication 1, dans lequel les premier et second points de branchement (A, B) comprennent des points de branchement centraux.
 
3. Circuit selon la revendication 1 ou 2, comprenant en outre un diviseur de tension capacitif (300) connecté entre la troisième ligne (280) et une ligne entre la grille (aa) du premier transistor (M1) de la première paire de transistors (M1, M3) et la grille (bb) du premier transistor (M2) de la seconde paire de transistors (M2, M4), le condensateur variable (C2') faisant partie du diviseur de tension capacitif.
 
4. Circuit selon la revendication 3, dans lequel le diviseur de tension (300) comprend :

au moins une première paire de condensateurs (C1a, C3a) connectés entre la grille (aa) du premier transistor (M1) de la première paire de transistors (M1, M3) dans la première ligne (270) et le premier point de branchement (250) dans la troisième ligne (280) ;

au moins une seconde paire de condensateurs (C1b, C3b) connectés entre la grille (bb) du premier transistor (M2) de la seconde paire de transistors (M2, M4) dans la deuxième ligne (290) et le second point de branchement (260) dans la troisième ligne (280) ; et

un second condensateur variable (Ctune') connecté entre des points intermédiaires (310, 320) des première et seconde paires de condensateurs (C1a, C3a, C1b, C3b) et conçu pour déterminer une plage de réglage du circuit.


 
5. Circuit selon la revendication 4, dans lequel le premier condensateur variable (C2') est conçu pour le réglage fin du circuit.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description