(19)
(11)EP 3 606 299 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
31.08.2022 Bulletin 2022/35

(21)Application number: 18774710.0

(22)Date of filing:  23.03.2018
(51)International Patent Classification (IPC): 
H05K 1/09(2006.01)
H01L 23/12(2006.01)
H01L 23/36(2006.01)
C04B 37/02(2006.01)
H01L 23/13(2006.01)
H05K 1/03(2006.01)
(52)Cooperative Patent Classification (CPC):
C04B 37/02; H01L 2224/48091; H01L 2224/48137; C22C 9/02; C22C 30/02; C22C 30/04; H01L 23/3735; H01L 23/49531; H01L 23/49827; H01L 23/3677
 
C-Sets:
H01L 2224/48091, H01L 2924/00014;
(86)International application number:
PCT/JP2018/011645
(87)International publication number:
WO 2018/180965 (04.10.2018 Gazette  2018/40)

(54)

CERAMIC-COPPER CIRCUIT SUBSTRATE AND SEMICONDUCTOR DEVICE USING SAME

KERAMIK-KUPFER-SCHALTUNGSSUBSTRAT UND HALBLEITERBAUELEMENT DAMIT

SUBSTRAT DE CIRCUIT EN CUIVRE-CÉRAMIQUE ET DISPOSITIF À SEMI-CONDUCTEUR FAISANT APPEL AUDIT SUBSTRAT


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 30.03.2017 JP 2017068153

(43)Date of publication of application:
05.02.2020 Bulletin 2020/06

(73)Proprietors:
  • Kabushiki Kaisha Toshiba
    Minato-ku Tokyo 105-8001 (JP)
  • Toshiba Materials Co., Ltd.
    Yokohama-shi, Kanagawa 235-8522 (JP)

(72)Inventors:
  • KATO, Hiromasa
    Yokohama-shi, Kanagawa 235-8522 (JP)
  • SANO, Takashi
    Yokohama-shi, Kanagawa 235-8522 (JP)

(74)Representative: Henkel & Partner mbB 
Patentanwaltskanzlei, Rechtsanwaltskanzlei Maximiliansplatz 21
80333 München
80333 München (DE)


(56)References cited: : 
EP-A1- 2 579 696
WO-A1-2015/019602
JP-A- H11 121 889
JP-A- 2011 119 343
WO-A1-2013/015355
WO-A1-2017/006661
JP-A- 2007 299 974
JP-A- 2014 060 407
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    [Technical Field]



    [0001] The invention described herein relates to a ceramic copper circuit board and a semiconductor device based on the same.

    [Background Art]



    [0002] A ceramic copper circuit board is used in a semiconductor device in which a semiconductor element such as a power element or the like is mounted. The ceramic substrate and the copper circuit board are bonded via a bonding layer. A Ag brazing material that includes a reactive metal such as Ti or the like is used as the bonding layer. The bonding strength and the heat cycle characteristics are improved thereby. Due to the increase of the reliability of ceramic copper circuit boards, ceramic copper circuit boards are used favorably in inverters of automobiles (also including electric cars), electric railway vehicles, solar power generation equipment, and industrial machinery.

    [0003] In a semiconductor device such as a power module or the like, a semiconductor element is mounted on the copper circuit board. Also, wire bonding and/or a metal terminal may be bonded to the copper circuit board for the conduction of the semiconductor element. The semiconductor element, the wire bonding, the metal terminal, etc., are bonded to the copper circuit board to complete the semiconductor device.

    [0004] Patent Literature 1 describes a ceramic copper circuit board in which the reliability is increased. In Patent Literature 1, the reliability is increased by optimizing the side surface configuration of the copper circuit board. The bonding strength and the heat cycle resistance of the ceramic copper circuit board of Patent Literature 1 are improved.

    [0005] On the other hand, there is still room for improvement to increase the reliability of the assembly process in which the semiconductor element, the wire bonding, the metal terminal, etc., are bonded to the copper circuit board.

    [0006] Patent Literature 2 discloses a ceramic metal circuit board that ensures improved bondability of a front metal plate and a rear metal plate even when the parts to be connected are different between the front and rear metal plates. The ceramic metal circuit board comprises a ceramic substrate and metal plates bonded to both surfaces of the ceramic substrate through respective bonding layers, wherein a metal film is provided on a surface of one metal plate bonded to one surface of the ceramic substrate, and wherein at least a part of another metal plate bonded to another surface of the ceramic substrate is not provided with the metal film. In one embodiment, the ceramic substrate is a silicon nitride substrate having a thickness of 0.25 mm, the metal plates are copper plates having a thickness of 0.8 mm, and the bonding layers are formed from an Ag-Cu-Sn-Ti brazing material.

    [0007] Patent Literature 3 teaches a circuit board that has good heat dissipation properties, and in which the warpage of a circuit member due to heat generated during the operation of an electronic component mounted on the circuit member is low. The circuit board comprises a supporting substrate and a circuit member which is formed on a main surface of the supporting substrate, wherein the circuit member contains copper as a principal component and an upper surface of the circuit member serves as a mounting surface for an electronic component. In one embodiment, the supporting substrate is a silicon nitride substrate having a thickness of 0.32 mm, the circuit member consists of a first copper member and a second copper member having a total thickness of 1.5 mm, and the circuit member is bonded to the supporting substrate via a joining layer formed from an Ag-Cu-Sn-Ti-Mo brazing material.

    [0008] Patent Literature 4 relates to an oxide-based ceramic circuit board that has excellent thermal cycle test (TCT) characteristics and excellent bonding strength. The oxide-based ceramic circuit board comprises an oxide-based ceramic substrate and a copper plate which are bonded to each other by a direct bonding method, wherein, when the copper plate is peeled off, the area ratio of copper on the joining face side of the copper plate to the oxide-based ceramic substrate is 3000 µm × 60% or less per 3000 µm, and the bonding strength of the copper plate is 9.5 kgf/cm or more. In one embodiment, the oxide-based ceramic substrate is an aluminum oxide substrate having a thickness of 0.4 mm, and the copper plate has a thickness of 0.5 mm.

    [Prior Art Document]


    [Patent Document]



    [0009] 

    Patent Literature 1: WO 2013/094213 A1

    Patent Literature 2: WO 2017/006661 A1

    Patent Literature 3: EP 2 579 696 A1

    Patent Literature 4: WO 2013/015355 A1


    [Summary of Invention]


    [Problem to be Solved by Invention]



    [0010] Due to the higher performance of semiconductor elements in recent years, the junction temperature when operating a semiconductor device is 170 °C or more. Thicker copper circuit boards are being investigated to improve the heat dissipation. The heat dissipation is improved by reducing the thickness of the ceramic substrate and increasing the thickness of the copper circuit board. On the other hand, the reliability of the bonds of the semiconductor element and the like are affected by the thermal expansion of the copper plate.

    [0011] The invention is directed to solve such a problem and relates to a ceramic copper circuit board realizing both the reliability and the bondability of the semiconductor element and the like. The invention is defined by the claims.

    [Means for Solving Problem]



    [0012]  In a first aspect, the invention thus relates to a ceramic circuit board as defined in claim 1. The ceramic copper circuit board includes a ceramic substrate, and a copper circuit board provided at one surface of the ceramic substrate, wherein:

    a ratio of a thickness of the copper circuit board to a thickness of the ceramic substrate is 1.25 or more,

    a number of grain boundaries is not less than 5 and not more than 250 along every 10-mm straight line drawn in a front surface of the copper circuit board,

    an arithmetic average roughness Ra of the front surface of the copper circuit board is 0.4 µm or less,

    a ten-point average roughness Rzjis of the front surface is 4 µm or less, and a maximum height Rz of the front surface is 5 µm or less.



    [0013] In a second aspect, the invention relates to a semiconductor device as defined in claim 13. The semiconductor device comprises the ceramic copper circuit board of the first aspect, and a semiconductor element mounted to the copper circuit board via a bonding layer.

    [Brief Description of Drawings]



    [0014] 

    FIG. 1 is a view showing an example of a ceramic copper circuit board according to the invention.

    FIG. 2 is a view showing an example of a front surface of the copper circuit board.

    FIG. 3 is a view showing another example of the ceramic copper circuit board according to the invention.

    FIG. 4 is a view showing an example of a semiconductor device according to the invention.

    FIG. 5 is a view showing other example of the ceramic copper circuit board according to the invention.


    [Embodiments of Invention]



    [0015] The ceramic copper circuit board according to the invention is a ceramic copper circuit board in which a copper circuit board is provided on at least one surface of a ceramic substrate; a ratio of a thickness of the copper circuit board to a thickness of the ceramic substrate is 1.25 or more; and a number of grain boundaries is not less than 5 and not more than 250 along every 10-mm straight line drawn in the copper circuit board front surface.

    [0016] FIG. 1 shows an example of the ceramic copper circuit board. 1 is the ceramic copper circuit board. 2 is the ceramic substrate. 3 is the copper circuit board (the front copper plate). 4 is a bonding layer. 5 is a back copper plate. T1 is the thickness of the ceramic substrate. T2 is the thickness of the copper circuit board. FIG. 1 shows an example in which two copper circuit boards 3 are bonded to the ceramic substrate 2. The invention is not limited to such a form; and one, three, or more copper circuit boards 3 may be bonded to the ceramic substrate 2. In the example of FIG. 1, a back copper plate 5 also is bonded to the ceramic substrate 2. The back copper plate 5 functions not as a circuit but as a heat dissipation plate. The back copper plate 5 can be provided as necessary.

    [0017] The ratio (T2/T1) of the thickness T2 of the copper circuit board 3 to the thickness T1 of the ceramic substrate 2 is 1.25 or more. The thickness T2 of the copper circuit board 3 is taken as the thickest thickness of the copper plate within the copper plate used as the circuit board of the ceramic copper circuit board 1. Therefore, the thickness of the back copper plate 5 is not treated as T2.

    [0018] T2/T1 ≥ 1.25 means that the copper circuit board 3 is thicker than the ceramic substrate 2. The thermal resistance of the ceramic copper circuit board 1 can be lowered by making the copper circuit board 3 thicker and making the ceramic substrate 2 thinner. Therefore, it is favorable for T2/T1 to be 1.25 or more. More favorably, T2/T1 is 2.40 or more.

    [0019] It is favorable for the ceramic substrate 2 to be one type of an aluminum oxide substrate, an aluminum nitride substrate, or a silicon nitride substrate. Also, the ceramic substrate 2 may be an Alusil substrate. The Alusil substrate is made of a sintered body in which aluminum oxide and zirconium oxide are mixed.

    [0020] The three-point bending strength of an aluminum nitride substrate or an aluminum oxide substrate is about 300 to 450 MPa. The strength of an Alusil substrate is about 550 MPa. If the substrate thickness of a ceramic substrate having a strength of 550 MPa or less is reduced to be 0.4 mm or less, there is a risk that the ceramic substrate may break when performing a heat cycle test (TCT test).

    [0021] The three-point bending strength of a silicon nitride substrate is, for example, 600 MPa or more. Also, the strength can be increased so that the three-point bending strength is 700 MPa or more. The thermal conductivity of the silicon nitride substrate is, for example, 50 W/m·K or more. Also, the thermal conductivity can be 80 W/m·K or more. In particular, in recent years, there is a silicon nitride substrate that has both a high strength and a high thermal conductivity. If the three-point bending strength of the silicon nitride substrate is 600 MPa or more and the thermal conductivity is 80 W/m·K or more, the thickness of the substrate can be set to, for example, 0.40 mm or less. It is also possible to set the thickness to be thinner, i.e., 0.30 mm or less. By making the ceramic substrate thinner, T2/T1 can be 1.25 or more, or even 2.40 or more.

    [0022] Also, the ceramic substrate may be a single plate or may have a three-dimensional structure such as a multilayer structure, etc.

    [0023] The number of grain boundaries is not less than 5 and not more than 250 along every 10-mm straight line drawn in the copper circuit board front surface. FIG. 2 shows an example of the copper plate front surface. In FIG. 2, 3 is the copper circuit board. 6 is the copper crystal grains. 7 is the grain boundaries. The copper circuit board is made of a polycrystalline body of copper. An enlarged photograph is taken of the copper circuit board front surface. The enlarged photograph is enlarged enough that the grain boundaries can be confirmed. If a 10-mm straight line cannot be imaged in one field of view, imaging is performed by subdividing into a plurality. In the case where the copper circuit board is patterned into a pattern configuration, a portion that has a length of 10 mm or more in some direction is imaged.

    [0024] In the invention, for every 10-mm straight line drawn in the enlarged photograph, the number of grain boundaries along the straight line is not less than 5 and not more than 250.

    [0025] The semiconductor element, the wire bonding, the metal terminal, etc., are bonded to the copper circuit board 3. At this time, these components are bonded to each other via a bonding layer such as solder, etc. When there are grain boundaries in the front surface of the copper circuit board 3, an anchor effect for the bonding layer is obtained. The wettability with the bonding layer also is improved. If the number of grain boundaries in the 10-mm straight line is less than 5, the number of grain boundaries is low and insufficient. If the number of grain boundaries is low, the copper crystal grains are large; and the contact ratio between the bonding layer and the copper crystal grain surface is high. If the junction temperature of the semiconductor element becomes high, the thermal expansion of the copper plate becomes large. If the grain boundaries are few, peeling between the copper circuit board front surface and the bonding layer occurs easily because the anchor effect is insufficient. When the number of grain boundaries in the 10-mm straight line exceeds 250, the number of grain boundaries is too high. If the number of grain boundaries increases, the anchor effect is obtained; but the grain boundaries become too many; and the heat dissipation decreases. Therefore, along every 10-mm straight line, it is favorable for the number of grain boundaries to be not less than 5 and not more than 250, and more favorably not less than 20 and not more than 150. More favorably, the number of grain boundaries along every 10-mm straight line is not less than 80 and not more than 150. Because the number of grain boundaries is within the range recited above no matter where the 10-mm straight line is drawn in the copper circuit board 3 front surface, excellent reliability can be obtained no matter where the semiconductor element, etc., are bonded on the copper circuit board 3. In other words, the circuit board provides excellent ease of assembly of the semiconductor device.

    [0026] The number of grain boundaries may be adjusted by adjusting the crystal size in a rolling process that adjusts the thickness of the copper plate. The number of grain boundaries may be adjusted by utilizing a heat treatment process of the manufacturing processes of the ceramic copper circuit board. The recrystallization temperature of copper is about 220 °C. As described below, for example, the ceramic substrate and the copper plate are bonded using reactive metal bonding. In reactive metal bonding, the ceramic substrate and the copper plate are heated to 700 to 900 °C. The copper plate recrystallizes in this process. The recrystallized copper crystal grains become large. The number of grain boundaries also can be adjusted by utilizing this phenomenon.

    [0027] At the copper circuit board front surface, the arithmetic average roughness Ra is 0.4 µm or less, the ten-point average roughness Rzjis is 4 µm or less, and the maximum height Rz is 5 µm or less. Ra, Rzjis, and Rz which are the parameters of the surface roughness are based on the JIS-B-0601 (2001) standard.

    [0028] JIS-B-0601 (2001) corresponds to ISO 4287 (1997, Amd. 1: 2009). Ra, Rzjis, and Rz may be measured using ISO 4287. JIS is given priority for the portions different between JIS-B-0601 and ISO 4287.

    [0029] The arithmetic average roughness Ra is the average value of the roughness curve. The maximum height Rz is the maximum value in the vertical direction between the peak line and the course line of the roughness curve. The ten-point average roughness Rzjis is the total of the average value of the five highest hill peak portions and the average value of the five lowest dale bottom portions of the roughness curve.

    [0030] A copper circuit board front surface that has a small surface unevenness is obtained by setting Ra, Rzjis, and Rz respectively to the values described above. Considering the anchor effect of the copper circuit board to the bonding layer of solder or the like, it is considered that a rough front surface is good. On the other hand, if the thickness of the copper circuit board becomes large and the junction temperature of the semiconductor element becomes high, the thermal expansion of the copper circuit board becomes large. If the thermal expansion of the copper circuit board becomes large, stress is applied to the bonding layer more easily as the surface unevenness increases; and discrepancies such as breaking, etc., occur easily.

    [0031] Therefore, in the ceramic copper circuit board according to the invention, the arithmetic average roughness Ra of the copper circuit board front surface is 0.4 µm or less, the ten-point average roughness Rzjis is 4 µm or less, and the maximum height Rz is 5 µm or less. Even if the surface unevenness is reduced, the reliability of the copper circuit board can be increased by controlling the number of grain boundaries.

    [0032] It is favorable for the arithmetic average roughness Ra of the copper circuit board front surface to be not less than 0.1 µm and not more than 0.4 µm. It is favorable for the ten-point average roughness Rzjis of the copper circuit board front surface to be not less than 1.5 µm and not more than 4 µm. It is favorable for the copper circuit board front surface maximum height Rz to be not less than 1 µm and not more than 5 µm. There is a risk that planarizing the front surface further than this may cause an increase of the manufacturing cost.

    [0033] It is favorable for the skewness Rsk of the roughness curve of the copper circuit board front surface to be less than 0. Rsk being less than 0 means that Rsk is negative. Rsk being negative means that there are more dale portions in the roughness curve. The grain boundary portions of the copper circuit board are dales. By causing the grain boundary portions to be dale portions, the anchor effect of the copper circuit board to the solder (or the brazing material) when bonding the semiconductor element can be improved. Therefore, it is favorable for the skewness Rsk of the roughness curve of the copper circuit board front surface to be less than 0. More favorably, the skewness Rsk of the roughness curve is not more than -0.01 and not less than -0.10. By setting the skewness Rsk to be within this range, the anchor effect can be improved also for bonding of a leadframe and/or wire bonding other than the semiconductor element.

    [0034] The skewness Rsk of the roughness curve is measured using ISO 4287 (1997, Amd. 1: 2009).

    [0035] In the case where the back copper plate 5 is provided, it is favorable for the back copper plate 5 to have the following configuration.

    [0036] The ratio (T3/T1) of a thickness T3 of the back copper plate 5 to the thickness T1 of the ceramic substrate 2 is 1.25 or more. More favorably, T3/T1 is 2.40 or more.

    [0037] The number of grain boundaries is not less than 5 and not more than 250 along every 10-mm straight line drawn in the back copper plate front surface. Favorably, the number of grain boundaries is not less than 20 and not more than 150. More favorably, the number of grain boundaries is not less than 80 and not more than 150. The technique for counting the number of grain boundaries is similar to the technique for counting the number of grain boundaries for the front surface of the copper circuit board. The front surface of the back copper plate refers to the surface of the back copper plate 5 on the side opposite to the ceramic substrate 2.

    [0038] In the back copper plate front surface, it is favorable for the arithmetic average roughness Ra to be 0.4 µm or less, the ten-point average roughness Rzjis to be 4 µm or less, and the maximum height Rz to be 5 µm or less. It is favorable for the arithmetic average roughness Ra of the back copper plate front surface to be not less than 0.1 µm and not more than 0.4 µm. It is favorable for the ten-point average roughness Rzjis of the back copper plate front surface to be not less than 1.5 µm and not more than 4 µm. It is favorable for the back copper plate front surface maximum height Rz to be not less than 1 µm and not more than 5 µm. It is favorable for the skewness Rsk of the roughness curve of the back copper plate front surface to be less than 0. More favorably, the skewness Rsk of the roughness curve is not more than -0.01 and not less than -0.10.

    [0039] It is favorable for the ceramic substrate 2 and the copper circuit board 3 to be bonded via the bonding layer 4. In the case where the back copper plate 5 is bonded to the ceramic substrate 2 as well, it is favorable for the back copper plate 5 and the ceramic substrate 2 to be bonded via the bonding layer. It is favorable to provide the bonding layer 4 that includes Ag and Ti between the ceramic substrate 2 and the copper circuit board 3. The bonding layer 4 that includes Ag (silver) and Ti (titanium) includes a reactive metal brazing material. Ti is the reactive metal. Other than Ti, Zr and Hf also are examples of the reactive metal. A mixture of Ti, Ag (silver), and Cu (copper) is an example of the reactive metal brazing material. In the reactive metal brazing material, the content of Ti is not less than 0.1 wt% and not more than 10 wt%; the content of Cu is not less than 10 wt% and not more than 60 wt%; and the remainder is Ag. Not less than 1 wt% and not more than 15 wt% of one type or two types selected from In (indium) or Sn (tin) may be added to the reactive metal brazing material as necessary. In the reactive metal bonding using the reactive metal brazing material, the reactive metal brazing material paste is coated onto the ceramic substrate front surface; and the copper plate is disposed on the reactive metal brazing material paste. This configuration is bonded by heating at 700 to 900 °C. According to the reactive metal bonding, the bonding strength between the ceramic substrate and the copper circuit board can be not less than 16 kN/m.

    [0040] It is favorable for the thickness of the copper circuit board to be 0.6 mm or more. As described above, it is effective to make the ceramic substrate thinner or make the copper circuit board thicker to set the ratio (T2/T1) of the thickness T2 of the copper circuit board and the thickness T1 of the ceramic substrate to be 1.25 or more. The heat dissipation is improved by increasing the thickness of the copper circuit board. As described above, the occurrence of the bonding defects between the semiconductor element and the copper circuit board due to thermal expansion can be reduced by controlling the surface roughness of the copper circuit board. Considering the heat dissipation, it is favorable for the thickness of the copper circuit board to be 0.6 mm or more. More favorably, the thickness of the copper circuit board is 0.8 mm or more. Although the upper limit of the thickness of the copper circuit board is not particularly limited, it is favorable for the upper limit to be 5 mm or less. When the thickness of the copper circuit board exceeds 5 mm, there is a risk that the warp may increase when bonding by reactive metal bonding.

    [0041] When the copper circuit board is uniformly trisected in the thickness direction, it is favorable for Ag to exist in not less than 15% and not more than 60% of the surface area of the copper circuit board in the region of the copper circuit board on the bonding layer side. FIG. 5 Shows an example of the cross section of the copper circuit board. In FIG. 5, 2 is the ceramic substrate. 3 is the copper circuit board. 4 is the bonding layer. T2 is the thickness of the copper circuit board 3. The copper circuit board 3 is uniformly trisected in the thickness direction. This is the uniform trisection of the thickness T2 of the copper circuit board 3. When the copper circuit board 3 is uniformly trisected, the region on the bonding layer 4 side is taken as a region 3a; the region in the middle is taken as a region 3b; and the region on the front surface side is taken as a region 3c.

    [0042] Color mapping of the dispersion state of Ag in any cross section of the copper circuit board 3 is performed by EDX (energy dispersive X-ray spectrometry). For the cross section of the region 3a, when a randomly extracted unit area of 100 µm×100 µm is observed, the proportion of the surface area where Ag is dispersed per unit area is not less than 15% and not more than 60%. The cross section to be observed is polished so that the surface roughness Ra is 1 µm or less. SEM (scanning electron microscope)-EDX is used for the observation.

    [0043] The boundary between the copper circuit board 3 and the bonding layer 4 can be discriminated in the SEM image. When it is difficult to discriminate using the SEM image, a straight line is drawn from one end of the surface of the copper circuit board 3 on the bonding layer 4 side to the other end of the surface on the opposite side. A method may be used in which the straight line is considered to be the boundary between the copper circuit board 3 and the bonding layer 4. For example, for a configuration in which the bonding layer 4 juts from the end portion of the copper circuit board 3 as shown in FIG. 1, the method in which the straight line is drawn is applied easily.

    [0044] The stress of the copper plate becomes large when the thickness T2 of the copper circuit board is 0.6 mm or more or even 0.8 mm or more. When thermal stress is applied, breaking occurs easily in the ceramic substrate and the bonding layer due to the thermal expansion difference between the ceramic substrate and the copper plate. By diffusing much Ag, the thermal expansion amount of the copper circuit board can approach the thermal expansion amount of the ceramic substrate. The Ag diffuses mainly along the grain boundaries. The Ag easily diffuses to the depthward side of the copper plate by diffusing along the grain boundaries. In the invention, the ease of the Ag diffusion can be controlled because the number of grain boundaries of the copper circuit board is controlled.

    [0045] When a unit area of 100 µm×100 µm of the region 3a is observed, it is favorable for the proportion of the surface area where Ag is dispersed to the observed surface area to be not less than 15% and not more than 60%. More favorably, the proportion is not less than 25% and not more than 50%. In the invention, the proportion of the surface area where Ag is dispersed to the observed surface area is not less than 15% and not more than 60% no matter which unit area of 100 µm×100 µm of the region 3a is observed.

    [0046] When a unit area of 100 µm×100 µm of the region 3b is observed, it is favorable for the proportion of the surface area where Ag is dispersed to the observed surface area to be not less than 0% and not more than 40%. The proportion being 0% means that Ag is not detected by EDX. Also, the dispersion area of Ag in the region 3b is less than the Ag dispersion area in the region 3a.

    [0047] When a unit area of 100 µm×100 µm of the region 3c is observed, it is favorable for the proportion of the surface area where Ag is dispersed to the observed surface area to be 0. It is favorable for the proportion of Ag inside the region 3b to be set to 40% or less (including 0%) and for the proportion of Ag inside the region 3c to be set to 0%.

    [0048] By not diffusing Ag in the region 3a which is the front-surface-side region of the copper circuit board 3, the surface roughness and the number of grain boundaries of the copper circuit board front surface are controlled easily. Therefore, the adhesion between the semiconductor element and the solder (or the brazing material) can be maintained when mounting the semiconductor element. That is, the durability for thermal stress and the adhesion with the solder both can be realized.

    [0049] It is favorable for the diffusion state of Ag into the back copper plate 5 or a back copper circuit board 8 also to be similar to that of the copper circuit board 3.

    [0050] In other words, when the back copper plate 5 is uniformly trisected, the region on the bonding layer 4 side is taken as a first region; the region in the middle is taken as a second region; and the region on the front surface side is taken as a third region. The unit area of 100 µm×100 µm of each region is observed. In the first region, it is favorable for the proportion of the surface area where Ag is dispersed to the observed surface area to be not less than 15% and not more than 60%. More favorably, the proportion is not less than 25% and not more than 50%. In the second region, it is favorable for the proportion of the surface area where Ag is dispersed to the observed surface area to be not less than 0% and not more than 40%. In the third region, it is favorable for the proportion of the surface area where Ag is dispersed to the observed surface area to be 0%.

    [0051] In the ceramic copper circuit board 1, it is favorable for the warp amount of the ceramic substrate 2 to be less than 0.1 mm. The warp amount of the ceramic substrate 2 is measured by the following method. A virtual straight line is drawn from one end to the other end of a long side of the ceramic substrate 2. The distance between the straight line and the point of the ceramic substrate 2 most distal to the straight line is taken as the warp amount. As described above, the warp amount of the ceramic substrate 2 can be less than 0.1 mm by controlling the diffusion state of Ag.

    [0052] In particular, even in the case where a copper plate having a thickness of 0.6 mm or more is bonded using a silicon nitride substrate having a three-point bending strength of 600 MPa or more, the warp amount of the silicon nitride substrate can be less than 0.1 mm without a warp correction process. The warp correction process is a process of heating while loading the ceramic copper circuit board with pressure. The warp easily becomes large when bonding when the copper plate is made thicker and the strength of the ceramic substrate is low. The warp amount of the ceramic substrate can be reduced by performing the warp correction process. On the other hand, grain growth of the crystal grains of the copper plate occurs due to the heat loading of the warp correction process. When grain growth occurs, there is a risk that the number of grain boundaries per 10 mm of the copper plate front surface may be less than 5. If the warp correction process is not performed, the number of grain boundaries per 10 mm of the copper plate front surface is controlled easily to be 80 or more.

    [0053] By setting the number of grain boundaries per 10 mm of the copper plate front surface to be not less than 80 and not more than 150, the warp amount of the silicon nitride substrate can be less than 0.1 mm even when the volume ratio of the copper plate is different between the front and back. The total volume of the copper circuit board 3 is taken as A (mm3); and the total volume of the back copper plate 5 is taken as B (mm3). The warp amount of the silicon nitride substrate can be less than 0.1 mm even within the range of 0.5 ≤ A/B ≤ 0.8. The total volume A (mm3) of the copper circuit board 3 is the total of the volume of each of one of more copper circuit boards 3 bonded to the front surface side. The total volume B (mm3) of the back copper plate 5 is the total of the volume of each of one or more back copper plates 5 bonded to the backside. As described below, in the case where one or more back copper circuit boards are bonded to the ceramic substrate 2, the total of the volume of each of the back copper circuit boards is taken as the total volume B (mm3).

    [0054] For a ceramic copper circuit board in which a silicon nitride substrate having a three-point bending strength of 600 MPa or more and a copper plate having a thickness of 0.6 mm or more are bonded, it is favorable to control the number of grain boundaries per 10 mm of the copper plate front surface to be not less than 80 and not more than 150 and to control the diffusion state of Ag. Thereby, the warp amount of the silicon nitride substrate can be less than 0.1 mm, and further can be 0.05 mm or less without the warp correction process even for the range of 0.5 ≤ A/B ≤ 0.8.

    [0055] A through-hole may be provided in the ceramic substrate. It is favorable for the ceramic copper circuit board to have a structure in which the copper circuit board of the front and the copper circuit board of the back conduct via the through-hole. An example of a ceramic circuit board having a through-hole is shown in FIG. 3. FIG. 3 is a cross-sectional view of the portion having the through-hole. In FIG. 3, 1 is the ceramic copper circuit board. 2 is the ceramic substrate. 3 is the copper circuit board (the front copper plate). 4 is the bonding layer. 8 is the back copper circuit board. 9 is the through-hole. In FIG. 3, the conduction between the copper circuit board 3 (the front copper plate) and the back copper circuit board 8 is realized via the through-hole 9. In FIG. 3, the through-hole 9 is provided at each copper circuit board 3. The invention is not limited to such a structure. In the ceramic copper circuit board 1, the through-hole 9 may be provided at only a portion of the multiple copper circuit boards 3. The thickness T2 of the copper circuit board is taken as the thicker of the thickness of the copper circuit board 3 and the thickness of the back copper circuit board 8.

    [0056] It is favorable for the same material as the bonding layer 4 to be filled into the interior of the through-hole 9. The structure of the interior of the through-hole 9 is not particularly limited as long as conduction is provided between the copper plate of the front and the copper plate of the back. Therefore, a metal thin film may be provided at only the through-hole 9 inner wall. On the other hand, the bonding strength can be increased by filling the same material as the bonding layer 4. It is favorable for the back copper circuit board 8 to have a configuration similar to the back copper plate 5 described above.

    [0057] A metal thin film may be provided at the copper circuit board front surface. The major component of the metal thin film is one selected from Ni (nickel), Ag (silver), and Au (gold). The metal thin film is, for example, a plating film, a sputtered film, etc. By providing the metal thin film, the corrosion resistance can be improved.

    [0058] Such a ceramic copper circuit board is favorable in a semiconductor device. In the semiconductor device, a semiconductor element is mounted to the copper circuit board of the ceramic copper circuit board via the bonding layer.

    [0059] An example of the semiconductor device is shown in FIG. 4. In FIG. 4, 1 is the ceramic copper circuit board. 10 is the semiconductor device. 11 is the semiconductor element. 12 is the bonding layer. 13 is wire bonding. 14 is a metal terminal. In FIG. 4, the semiconductor element 11 is bonded onto the copper circuit board of the ceramic copper circuit board 1 via the bonding layer 12. Similarly, the metal terminal 14 is bonded via the bonding layer 12. The mutually-adjacent copper circuit boards conduct via the wire bonding 13. Other than the semiconductor element 11 in FIG. 4, the wire bonding 13 and the metal terminal 14 are bonded. The semiconductor device according to the invention is not limited to such a structure. For example, only one of the wire bonding 13 or the metal terminal 14 may be provided. The semiconductor element 11, the wire bonding 13, and the metal terminal 14 each may be multiply provided at the copper circuit board 3. The semiconductor element 11, the wire bonding 13, and the metal terminal 14 are bonded to the back copper circuit board 8 as necessary. Various configurations such as a leadframe configuration, a protruding configuration, etc., are applicable to the metal terminal 14.

    [0060] Solder, a brazing material, etc., are examples of the bonding layer 12 bonding the semiconductor element 11 or the metal terminal 14. Lead-free solder is favorable as the solder. It is favorable for the melting point of the solder to be 450 °C or less. It is favorable for the melting point of the brazing material to be 450 °C or less. A brazing material of which the melting point is 500 °C or more is called a high-temperature brazing material. An example of the high-temperature brazing material has Ag as a major component.

    [0061] In the ceramic copper circuit board according to the invention, the heat dissipation is excellent because T2/T1 is 1.25 or more. The reliability of the bonding layer bonding the semiconductor element, etc., can be increased because the number of grain boundaries of the copper circuit board front surface is controlled. In particular, the reliability of the bonding between the semiconductor element and the copper circuit board can be maintained even when the junction temperature of the semiconductor element is a high temperature of 170 °C or more. The number of grain boundaries along every 10-mm straight line drawn in the copper circuit board front surface is controlled to be within the prescribed range. Therefore, high reliability can be obtained no matter where the semiconductor element, the wire bonding, or a metal terminal are bonded to the copper circuit board front surface. A semiconductor device that has good ease of assembly can be provided by increasing the reliability of the bonding of the semiconductor element, the wire bonding, and the metal terminal.

    [0062] The placement positions of the semiconductor element, etc., on the copper circuit board are detected by image analysis using a CCD camera, etc. As the copper plate is made thicker, it becomes difficult to perform position detection referenced to the ceramic substrate. Therefore, by setting the number of grain boundaries of the copper circuit board front surface to be within the prescribed range beforehand, the position detection of the copper plate front surface is performed easily. In other words, according to the invention, a ceramic copper circuit board that has good ease of assembly can be provided.

    [0063] In recent years, the higher performance and downsizing of semiconductor elements are advancing; and the heat generation amount from the chip is increasing. Therefore, the improvement of the heat dissipation is important for a ceramic copper circuit board in which the semiconductor element is mounted. For higher performance of the semiconductor device (the semiconductor module), it is favorable for multiple semiconductor elements to be mounted on the ceramic copper circuit board. When one of the semiconductor elements exceeds the intrinsic temperature, the resistance becomes negative; and the temperature coefficient changes to the negative side. Accordingly, thermal runaway occurs in which the electrical power flows concentratively in the one semiconductor element; and a phenomenon occurs in which breakdown of the one semiconductor element undesirably occurs instantaneously. Thereby, it is extremely effective to increase the reliability of the bonding between the semiconductor element and the copper circuit board. The semiconductor device according to the invention can be used as a PCU, IGBT, or IPM module. The PCU, IGBT, or IPM module is used in an inverter of a device of an automobile (also including an electric car), an electric railway vehicle, industrial machinery, an air conditioner, etc. Research to make electric cars for automobiles is being performed aggressively. The safety of the automobile also improves as the reliability of the semiconductor device increases. This is similar for an electric railway, industrial devices, etc., as well.

    [0064] A method for manufacturing the ceramic copper circuit board according to the invention will now be described. As long as the ceramic copper circuit board has the configuration described above, the manufacturing method is not particularly limited. The following is an example of a method for manufacturing having good yield.

    [0065] First, the ceramic substrate and the copper plate are prepared. The relationship between the thickness T1 of the ceramic substrate and the thickness T2 of the copper plate is T2/T1 ≥ 1.25.

    [0066] It is favorable for the ceramic substrate to be one type selected from an aluminum oxide substrate, an aluminum nitride substrate, a silicon nitride substrate, and an Alusil substrate. In particular, it is favorable for the ceramic substrate to be a silicon nitride substrate having a thermal conductivity of 50 W/m·K or more and a three-point bending strength of 600 MPa or more. For such a silicon nitride substrate, the substrate thickness can be set to 0.40 mm or less. A copper plate that has a thickness of 0.6 mm or more is used.

    [0067] In the case where the copper plate on the front side and the copper plate on the backside conduct via a through-hole, a ceramic substrate that has the through-hole is prepared. In the case where the through-hole is provided in the ceramic substrate, the through-hole may be provided beforehand in the molded body stage. A process of providing the through-hole in the ceramic substrate (the ceramic sintered body) may be performed. Laser processing, machining, etc., are examples of the process of providing the through-hole. Boring such as drilling, etc., are examples of the machining.

    [0068]  It is favorable for the number of grain boundaries to be not less than 10 and not more than 300 along every 10-mm straight line in the front surface of the copper plate. More favorably, the number of grain boundaries is not less than 50 and not more than 120 along every 10-mm straight line in the front surface of the copper plate. In the case where reactive metal bonding is performed for the bonding between the ceramic substrate and the copper plate, the bonding temperature is about 700 to 900 °C. When the copper plate is exposed to this temperature, the copper recrystallizes. Thereby, the crystal grains become large; and the number of grain boundaries decreases. It is favorable to use a copper plate in which the number of grain boundaries is within the prescribed range described above while taking into account such a decrease.

    [0069] It is favorable for the ceramic substrate and the copper plate to be bonded by reactive metal bonding. A reactive metal brazing material in which Ag and a reactive metal such as Ti or the like are mixed is used in the reactive metal bonding. A mixture of Ti, Ag (silver), and Cu (copper) is an example of the reactive metal brazing material. In the reactive metal brazing material, the content of Ti is not less than 0.1 wt% and not more than 10 wt%. The content of Cu is not less than 10 wt% and not more than 60 wt%. The remainder is Ag. Not less than 1 wt% and not more than 15 wt% of one type or two types selected from In (indium) or Sn (tin) may be added to the reactive metal brazing material as necessary.

    [0070] The reactive metal brazing material is formed as a paste. The paste is obtained by mixing a brazing material component and an organic substance. The reactive metal brazing material paste is coated onto the ceramic substrate. The copper plate is disposed on the reactive metal brazing material paste. Then, the ceramic substrate and the copper plate are bonded by heating at 700 to 900 °C. The heating process is performed in a vacuum or in a nonoxidizing atmosphere as necessary. When performing in a vacuum, it is favorable for the pressure to be 1×10-2 Pa or less. A nitrogen atmosphere or an argon atmosphere is an example of the nonoxidizing atmosphere. The oxidization of the bonding layer can be suppressed by using a vacuum or a nonoxidizing atmosphere. The bonding strength can be increased thereby. The number of grain boundaries in the copper plate front surface can be adjusted by adjusting the bonding temperature and/or time.

    [0071] By controlling the number of grain boundaries in the copper plate beforehand, Ag diffuses along the grain boundaries. To control the diffusion state of Ag, it is favorable for the thermal bonding process to include a degreasing process of the reactive metal brazing material paste. In the thermal bonding process, a temperature range of 700 to 900 °C is maintained for the bonding. Before reaching this temperature, the organic substance inside the paste is degreased. The diffusion amount of Ag can be controlled thereby. This is because the brazing material that contacts the copper plate can be homogenized by degreasing the organic substance inside the brazing material paste at the bonding temperature beforehand.

    [0072] In the degreasing process of the brazing material paste, the temperature is maintained in a range of 250 to 450 °C. It is favorable for the time of maintaining this temperature range to be in a range of 5 to 60 minutes. As another method, it is also effective to set the temperature increase rate to be 10 °C/minute or less.

    [0073] The copper plate that is bonded may be pre-patterned in a pattern configuration or may not be patterned. In the case where a copper plate that is not patterned is used, the copper plate may be patterned into a pattern configuration by etching after bonding. When performing the etching, it is favorable to provide a side surface configuration of the copper plate shown in Patent Literature 1 and a jutting portion of the brazing material shown in Patent Literature 1.

    [0074] The ceramic copper circuit board is manufactured by the processes recited above. It is effective to perform chemical polishing to adjust the surface roughness of the copper circuit board of the ceramic copper circuit board that is obtained. An acidic liquid or an alkaline liquid is used in the chemical polishing. According to the chemical polishing, the copper circuit board front surface can be polished uniformly. Therefore, it is easy to control the arithmetic average roughness Ra to 0.4 µm or less, the ten-point average roughness Rzjis to 4 µm or less, and the maximum height Rz to 5 µm or less. By adjusting the chemical polishing time, Ra can be not less than 0.1 µm and not more than 0.4 µm; Rzjis can be not less than 1.5 µm and not more than 4 µm; and Rz can be not less than 1 µm and not more than 5 µm. The chemical polishing may not be performed in the case where the surface roughness recited above is obtained without performing the chemical polishing. It is sufficient to perform the chemical polishing only for the front surface of the copper plate used as the circuit. The locations where the chemical polishing is not performed are masked beforehand.

    [0075] Then, the process of bonding a semiconductor element, etc., is performed. A bonding layer is provided at the location where the semiconductor element is to be bonded. It is favorable for the bonding layer to be solder or a brazing material. The bonding layer is provided; and the semiconductor element is provided on the bonding layer. A metal terminal is bonded via the bonding layer as necessary. Wire bonding is provided as necessary. The numbers of each of the semiconductor element, the metal terminal, and the wire bonding are appropriately adjusted.

    [0076] In the ceramic copper circuit board according to the invention, the number of grain boundaries of the copper circuit board front surface is controlled. Thereby, excellent reliability can be obtained no matter where the semiconductor element, the metal terminal, and the wire bonding are bonded to the copper circuit board front surface. Therefore, the locations on the copper circuit board front surface where the semiconductor element, etc., are mounted are not limited. The ease of assembly when manufacturing the semiconductor device can be improved.

    [0077] Position detection that is referenced to the copper circuit board front surface also is easy. Therefore, even in the case where the semiconductor element, the metal terminal, the wire bonding, etc., are multiply provided, the positions do not shift easily. In other words, the ceramic copper circuit board according to the invention is favorable in a semiconductor device in which the semiconductor element, the metal terminal, and the wire bonding are multiply provided.

    [0078] A recognition display to improve the visibility for the positional alignment may be performed. Laser patterning or etching of the copper circuit board front surface, providing a resin layer on the copper circuit board front surface, etc., are examples of recognition display methods. A bar code display may be provided in the case where the resin layer is provided.

    (Example)


    (Examples 1 to 7 and comparative examples 1 and 2)



    [0079] First to third silicon nitride substrates shown in Table 1 were prepared as ceramic substrates. The size of each ceramic substrate is 50 mm long×40 mm wide. Two through-holes having diameters of 2 mm are provided in the third silicon nitride substrate.
    [Table 1]
     THERMAL CONDUCTIVITY (W/m▪K)THREE-POINT BENDING STRENGTH (MPa)SUBSTRATE THICKNESS T1 (mm)
    FIRST SILICON NITRIDE SUBSTRATE 90 650 0.32
    SECOND SILICON NITRIDE SUBSTRATE 85 750 0.25
    THIRD SILICON NITRIDE SUBSTRATE (WITH THROUGH-HOLE) 90 650 0.32


    [0080] Then, copper plates were prepared. Two types of thicknesses of the copper plate, i.e., 0.6 mm and 0.8 mm, were prepared. The ceramic substrate and the copper plates were bonded by reactive metal bonding. In the reactive metal brazing material used in the reactive metal bonding, the content of Ti is 2 wt%; the content of In is 10 wt%; the content of Cu is 30 wt%; and the remainder is Ag. Reactive metal paste was coated onto the two surfaces of the ceramic substrate; the copper plates were disposed; and a thermal bonding process was performed. The bonding temperature was maintained in the range of 780 to 850 °C; and the pressure was set to 1×10-2 Pa or less. The number of grain boundaries in the copper plate front surface was adjusted by changing the bonding time. For the examples, a brazing material paste degreasing process of maintaining the temperature in the range of 250 to 450 °C was performed. When the third silicon nitride substrate was used as the ceramic substrate, the copper plates were bonded after filling a reactive metal brazing material into the through-holes.

    [0081] The front copper plate was etched into a circuit configuration. The front copper plate had two to four circuit configurations. When the third silicon nitride substrate was used, the back copper plate also was etched into a circuit configuration. The total volume of the copper circuit board (the front copper plate) was taken as A (mm3); and the total volume of the back copper plate was taken as B (mm3).

    [0082] The ceramic copper circuit boards that were obtained are shown in Table 2.
    [Table 2]
     CERAMIC SUBSTRATECOPPER PLATE (THICKNESS T2)T2/T1A/B
    EXAMPLE 1 FIRST SILICON NITRIDE SUBSTRATE 0.6 1.88 0.8
    EXAMPLE 2 SECOND SILICON NITRIDE SUBSTRATE 0.6 2.4 0.7
    EXAMPLE 3 THIRD SILICON NITRIDE SUBSTRATE 0.6 1.88 0.8
    EXAMPLE 4 FIRST SILICON NITRIDE SUBSTRATE 0.8 1.33 0.8
    EXAMPLE 5 SECOND SILICON NITRIDE SUBSTRATE 0.8 2.4 0.5
    EXAMPLE 6 FIRST SILICON NITRIDE SUBSTRATE 1.2 3.75 0.6
    EXAMPLE 7 SECOND SILICON NITRIDE SUBSTRATE 1.2 4.8 0.7
    COMPARATIVE EXAMPLE 1 FIRST SILICON NITRIDE SUBSTRATE 0.6 1.88 0.8
    COMPARATIVE EXAMPLE 2 FIRST SILICON NITRIDE SUBSTRATE 0.6 1.88 0.8


    [0083] Then, the surface roughness of the examples 1 to 7 was adjusted by performing chemical polishing of the copper circuit board front surface. Chemical polishing was not performed for the comparative example 1 and the comparative example 2. The number of grain boundaries of the copper circuit board front surface and the surface roughness were measured for each ceramic copper circuit board.

    [0084] An enlarged photograph of the copper plate front surface was taken to count the number of grain boundaries. A 10-mm straight line was drawn randomly in the enlarged photograph; and the number of grain boundaries on the straight line was verified. This operation was performed to measure five locations (five random 10-mm straight lines); and the maximum value and the minimum value are shown. Also, the surface roughness Ra, Rzjis, and Rz were measured based on the JIS-B-0601 (2001) standard. The results are shown in Table 3.
    [Table 3]
     NUMBER OF GRAIN BOUNDARIES PER 10-mm STRAIGHT LINESURFACE ROUGHNESS
    ARITHMETIC AVERAGE ROUGHNESS Ra (µm)TEN-POINT AVERAGE ROUGHNESS Rzjis (µm)MAXIMUM HEIGHT Rz (µm)ROUGHNESS CURVE SKEWNESS Rsk
    EXAMPLE 1 83 ~ 105 0.4 3.8 4.7 - 0.10
    EXAMPLE 2 22 ∼ 38 0.2 2.8 3.7 - 0.09
    EXAMPLE 3 98 ∼ 116 0.3 2.2 3.0 - 0.07
    EXAMPLE 4 14 ∼ 18 0.1 1.9 2.4 - 0.04
    EXAMPLE 5 55 ∼ 72 0.3 2.7 2.9 - 0.04
    EXAMPLE 6 91 ∼ 132 0.1 2.5 2.9 - 0.01
    EXAMPLE 7 105 ∼ 145 0.2 3.4 3.6 - 0.03
    COMPARATIVE EXAMPLE 1 2 ∼ 4 0.8 6.3 9.2 +0.22
    COMPARATIVE EXAMPLE 2 288∼346 0.4 5.2 6.1 +0.17


    [0085] For the examples, it can be seen from Table 3 that the front surface of the copper circuit board of the ceramic copper circuit board was within the scope of the claims. On the other hand, the number of grain boundaries is too small in the comparative example 1. The number of grain boundaries is too high in the comparative example 2.

    [0086] Then, the warp amount and the diffusion state of Ag were verified for the ceramic copper circuit boards according to the examples and the comparative examples. The measurement of the warp amount was performed by drawing a straight line from one end to the other end of a long side of the silicon nitride substrate and by using the longest distance between the straight line and the silicon nitride substrate as the warp amount.

    [0087] The measurement of the diffusion state of Ag was performed by measuring any cross section of the copper circuit board by EDX. Color mapping of the dispersion state of Ag inside the copper circuit board was performed. The thickness T2 of the copper circuit board was uniformly trisected and taken as the region 3a, the region 3b, and the region 3c from the side proximal to the bonding layer. A unit area of 100 µm×100 µm was measured for each region; and the proportion (the diffusion area ratio) of Ag per unit area was measured. The diffusion area ratio of Ag was determined by performing this operation 3 times for each region. The results are shown in Table 4.
    [Table 4]
     CERAMIC SUBSTRATE WARP AMOUNT (mm)Ag DIFFUSION AREA RATIO (%) INSIDE COPPER CIRCUIT BOARD
    REGION 3aREGION 3bREGION 3c
    EXAMPLE 1 0.01 26 ∼ 56 5 ∼ 22 0
    EXAMPLE 2 0.06 18 ~ 38 2 ∼ 5 0
    EXAMPLE 3 0.02 30 ∼ 58 3 ∼ 19 0
    EXAMPLE 4 0.05 25 ∼ 42 0 ∼ 3 0
    EXAMPLE 5 0.07 17 ∼ 36 0 ∼ 2 0
    EXAMPLE 6 0.03 45 ∼ 60 0 -16 0
    EXAMPLE 7 0.04 38 ∼ 58 0-15 0
    COMPARATIVE EXAMPLE 1 0.22 0-2 0 0
    COMPARATIVE EXAMPLE 2 0.09 82∼ 90 36∼ 55 0


    [0088] The warp amount of the ceramic copper circuit board was less than 0.1 mm for the examples. The warp amount was small even though a warp correction process was not performed for any of the examples.

    [0089] For the ceramic copper circuit boards according to the invention, the diffusion area ratio of Ag was not less than 20% and not more than 80% in the region 3a proximal to the bonding layer. The diffusion area ratio of Ag was 20% or less (including 0) in the region 3b which is the region in the middle. The diffusion area ratio of Ag was 0% in the region 3c which is the front-surface-side region.

    [0090] Conversely, the warp amount was large for the ceramic copper circuit board of the comparative example 1. The diffusion area ratio of Ag was large for the ceramic copper circuit board of the comparative example 2. It can be seen that the number of grain boundaries in the copper plate affects the diffusion state of Ag.

    [0091] Then, the ease of assembly was evaluated for the ceramic copper circuit boards according to the examples and the comparative examples. The bondability and the alignment performance of the semiconductor element were evaluated as the evaluation of the ease of assembly.

    [0092] First, the semiconductor element and the metal terminal were bonded using lead-free solder. Further, conduction was realized by providing wire bonding. The semiconductor device was made thereby. Next, the occurrence rate of conduction defects was verified by performing a TCT test as a test of the bondability for the semiconductor device. Two types of TCT (Temperature Cycle Testing) tests were performed. In a first condition, -30 °C×30 minutes→room temperature×10 minutes→125 °C×30 minutes→room temperature×10 minutes was used as one cycle; and the occurrence rate of conduction defects after 2000 cycles was verified. In a second condition, -40 °C×30 minutes→room temperature×10 minutes→175 °C×30 minutes→room temperature×10 minutes was used as one cycle; and the occurrence rate of conduction defects after 2000 cycles was verified.

    [0093] For the alignment performance, position detection was performed using a CCD camera; and lead-free solder was coated onto the target location of the copper circuit board front surface. At this time, the proportion for which a misalignment of 0.5 mm or more occurred was verified.

    [0094] The results are shown in Table 5.
    [Table 5]
     CONDUCTION DEFECT RATE (%) AFTER TCT TESTALIGNMENT PERFORMANCE
    FIRST CONDITIONSECOND CONDITION0.5 mm OR GREATER MISALIGNMENT OCCURRENCE RATE (%)
    EXAMPLE 1 0 0 0
    EXAMPLE 2 0 0 0
    EXAMPLE 3 0 0 0
    EXAMPLE 4 0 0 2
    EXAMPLE 5 0 0 0
    EXAMPLE 6 0 0 0
    EXAMPLE 7 0 0 0
    COMPARATIVE EXAMPLE 1 0 8 4
    COMPARATIVE EXAMPLE 2 0 2 0


    [0095] It can be seen from the table that conduction defects did not occur for any of the examples or the comparative examples at the first condition (the high-temperature side being 125 °C). Conversely, at the second condition (the high-temperature side being 175 °C), a difference occurred between the occurrence rates of conduction defects. This is because the wettability of the solder and/or the bonding strength was increased by controlling the number of grain boundaries in the copper plate front surface. The alignment performance also improved for the examples. This result shows that the number of grain boundaries in the copper plate front surface affects the position detectability using the CCD camera. Misalignment occurred when the number of grain boundaries was less than 20 per 10-mm straight line as in the example 4. It was found that having the prescribed number of grain boundaries was effective when performing the position detection using the CCD camera.

    [0096] Conversely, as in the comparative example 1, there were many conduction defects at the second condition when the grain boundaries were few. This is because the distortion amount of the copper plate front surface due to the thermal expansion was large. When the number of grain boundaries is too high as in the comparative example 2, the heat dissipation decreases. When the heat dissipation decreases, it is difficult for the heat to be emitted. The conduction defect rate of the comparative example 2 is higher than those of the examples at the second condition because it is difficult for the heat to be emitted; and thermal stress is generated in the bonding layers between the semiconductor element and the copper circuit board.

    [0097] While certain embodiments have been described, these embodiments have been presented by way of example only. Indeed, the embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes may be made within the scope of the claims.


    Claims

    1. A ceramic copper circuit board (1), comprising:

    a ceramic substrate (2); and

    a copper circuit board (3) provided at one surface of the ceramic substrate (2),

    a ratio of a thickness of the copper circuit board (3) to a thickness of the ceramic substrate (2) being 1.25 or more, and

    a number of grain boundaries (7) being not less than 5 and not more than 250 along every 10-mm straight line drawn in a front surface of the copper circuit board (3),

    characterized in that an arithmetic average roughness Ra of the front surface of the copper circuit board (3) is 0.4 µm or less,

    a ten-point average roughness Rzjis of the front surface is 4 µm or less, and

    a maximum height Rz of the front surface is 5 µm or less.


     
    2. The ceramic copper circuit board (1) according to claim 1, wherein the number of grain boundaries (7) is not less than 20 and not more than 150 along every 10-mm straight line drawn in the front surface of the copper circuit board (3).
     
    3. The ceramic copper circuit board (1) according to claim 1 or 2, wherein the number of grain boundaries (7) is not less than 80 and not more than 150 along every 10-mm straight line drawn in the front surface of the copper circuit board (3) .
     
    4. The ceramic copper circuit board (1) according to any one of claims 1 to 3, wherein:

    an arithmetic average roughness Ra of the front surface of the copper circuit board (3) is not less than 0.1 µm and not more than 0.4 µm,

    a ten-point average roughness Rzjis of the front surface is not less than 1.5 µm and not more than 4 µm, and

    a maximum height Rz of the front surface is not less than 1 µm and not more than 5 µm.


     
    5. The ceramic copper circuit board (1) according to any one of claims 1 to 4, wherein a skewness Rsk of a roughness curve of the front surface of the copper circuit board (3) is less than 0.
     
    6. The ceramic copper circuit board (1) according to any one of claims 1 to 5, wherein the ceramic substrate (2) is one of an aluminum oxide substrate, an aluminum nitride substrate, or a silicon nitride substrate.
     
    7. The ceramic copper circuit board (1) according to any one of claims 1 to 6, further comprising a bonding layer (4) provided between the ceramic substrate (2) and the copper circuit board (3), the bonding layer (4) including Ag and Ti.
     
    8. The ceramic copper circuit board (1) according to claim 7, wherein when the copper circuit board (3) is uniformly trisected in a thickness direction, a proportion of a surface area where Ag exists in a region of the copper circuit board (3) on the bonding layer (4) side is not less than 20% and not more than 80%.
     
    9. The ceramic copper circuit board (1) according to any one of claims 1 to 8, wherein the thickness of the copper circuit board (3) is 0.6 mm or more.
     
    10. The ceramic copper circuit board (1) according to any one of claims 1 to 9, wherein a warp amount of the ceramic substrate (2) is less than 0.1 mm.
     
    11. The ceramic copper circuit board (1) according to any one of claims 1 to 10, further comprising a copper plate (8) provided at another surface of the ceramic substrate (2),

    a through-hole (9) being provided in the ceramic substrate (2),

    the copper circuit board (3) and the copper plate (8) conducting via the through-hole (9).


     
    12. The ceramic copper circuit board (1) according to claim 11, wherein the number of grain boundaries (7) is not less than 5 and not more than 250 along every 10-mm straight line drawn in a front surface of the copper plate (8).
     
    13. A semiconductor device (10), comprising:

    the ceramic copper circuit board (1) according to any one of claims 1 to 12; and

    a semiconductor element (11) mounted to the copper circuit board (3) via a bonding layer (12).


     
    14. The semiconductor device (10) according to claim 13, further comprising wire bonding (13) or a metal terminal (14) bonded to the copper circuit board (3).
     


    Ansprüche

    1. Keramik-Kupfer-Leiterplatte (1), umfassend:

    ein Keramiksubstrat (2); und

    eine Kupferleiterplatte (3), welche an einer Oberfläche des Keramiksubstrats (2) bereitgestellt ist,

    wobei das Verhältnis einer Dicke der Kupferleiterplatte (3) zu einer Dicke des Keramiksubstrats (2) 1.25 oder mehr beträgt, und

    wobei die Anzahl der Korngrenzen (7) entlang einer jeden 10 mm langen, in einer Frontoberfläche der Kupferleiterplatte (3) gezogenen geraden Linie nicht weniger als 5 und nicht mehr als 250 beträgt,

    dadurch gekennzeichnet, dass der arithmetische Mittenrauwert Ra der Frontoberfläche der Kupferleiterplatte (3) 0.4 µm oder weniger beträgt,

    der Zehn-Punkte-Mittenrauwert Rzjis der Frontoberfläche 4 µm oder weniger beträgt, und

    die maximale Höhe Rz der Frontoberfläche 5 µm oder weniger beträgt.


     
    2. Keramik-Kupfer-Leiterplatte (1) gemäß Anspruch 1, wobei die Anzahl der Korngrenzen (7) entlang einer jeden 10 mm langen, in der Frontoberfläche der Kupferleiterplatte (3) gezogenen geraden Linie nicht weniger als 20 und nicht mehr als 150 beträgt.
     
    3. Keramik-Kupfer-Leiterplatte (1) gemäß Anspruch 1 oder 2, wobei die Anzahl der Korngrenzen (7) entlang einer jeden 10 mm langen, in der Frontoberfläche der Kupferleiterplatte (3) gezogenen geraden Linie nicht weniger als 80 und nicht mehr als 150 beträgt.
     
    4. Keramik-Kupfer-Leiterplatte (1) gemäß einem der Ansprüche 1 bis 3, wobei:

    der arithmetische Mittenrauwert Ra der Frontoberfläche der Kupferleiterplatte (3) nicht weniger als 0.1 µm und nicht mehr als 0.4 µm beträgt,

    der Zehn-Punkte-Mittenrauwert Rzjis der Frontoberfläche nicht weniger als 1.5 µm und nicht mehr als 4 µm beträgt, und

    die maximale Höhe Rz der Frontoberfläche nicht weniger als 1 µm und nicht mehr als 5 µm beträgt.


     
    5. Keramik-Kupfer-Leiterplatte (1) gemäß einem der Ansprüche 1 bis 4, wobei die Schiefe Rsk einer Rauheitskurve der Frontoberfläche der Kupferleiterplatte (3) weniger als 0 beträgt.
     
    6. Keramik-Kupfer-Leiterplatte (1) gemäß einem der Ansprüche 1 bis 5, wobei es sich bei dem Keramiksubstrat (2) um ein Aluminiumoxidsubstrat, ein Aluminiumnitridsubstrat oder ein Siliziumnitridsubstrat handelt.
     
    7. Keramik-Kupfer-Leiterplatte (1) gemäß einem der Ansprüche 1 bis 6, weiterhin umfassend eine zwischen dem Keramiksubstrat (2) und der Kupferleiterplatte (3) bereitgestellte Bindeschicht (4), wobei die Bindeschicht (4) Ag und Ti enthält.
     
    8. Keramik-Kupfer-Leiterplatte (1) gemäß Anspruch 7, wobei, wenn die Kupferleiterplatte (3) in einer Dickenrichtung gleichmäßig in drei Teile unterteilt wird, der Anteil einer Oberfläche mit hierin vorhandenem Ag in einem Bereich der Kupferleiterplatte (3) auf der Seite der Bindeschicht (4) nicht weniger als 20% und nicht mehr als 80% beträgt.
     
    9. Keramik-Kupfer-Leiterplatte (1) gemäß einem der Ansprüche 1 bis 8, wobei die Dicke der Kupferleiterplatte (3) 0.6 mm oder mehr beträgt.
     
    10. Keramik-Kupfer-Leiterplatte (1) gemäß einem der Ansprüche 1 bis 9, wobei das Ausmaß der Verformung des Keramiksubstrats (2) weniger als 0.1 mm beträgt.
     
    11. Keramik-Kupfer-Leiterplatte (1) gemäß einem der Ansprüche 1 bis 10, weiterhin umfassend eine Kupferplatte (8), welche an einer anderen Oberfläche des Keramiksubstrats (2) bereitgestellt ist,

    wobei das Keramiksubstrat (2) mit einer Durchgangsbohrung (9) versehen ist, und

    wobei die Kupferleiterplatte (3) und die Kupferplatte (8) über die Durchgangsbohrung (9) leiten.


     
    12. Keramik-Kupfer-Leiterplatte (1) gemäß Anspruch 11, wobei die Anzahl der Korngrenzen (7) entlang einer jeden 10 mm langen, in einer Frontoberfläche der Kupferplatte (8) gezogenen geraden Linie nicht weniger als 5 und nicht mehr als 250 beträgt.
     
    13. Halbleitervorrichtung (10), umfassend:

    die Keramik-Kupfer-Leiterplatte (1) gemäß einem der Ansprüche 1 bis 12; und

    ein Halbleiterelement (11), welches über eine Bindeschicht (12) an der Kupferleiterplatte (3) befestigt ist.


     
    14. Halbleitervorrichtung (10) gemäß Anspruch 13, weiterhin umfassend einen Drahtanschluss (13) oder einen Metallanschluss (14), welcher mit der Kupferleiterplatte (3) verbunden ist.
     


    Revendications

    1. Plaque de circuit en cuivre céramique (1), comprenant :

    un substrat céramique (2) ; et

    une plaque de circuit en cuivre (3) fournie sur une surface du substrat céramique (2),

    un rapport d'une épaisseur de la plaque de circuit en cuivre (3) à une épaisseur du substrat céramique (2) étant de 1,25 ou supérieur, et

    un nombre de limites de grains (7) n'étant pas inférieur à 5 et pas supérieur à 250 le long de chaque ligne droite de 10-mm dans une surface avant de la plaque de circuit en cuivre (3),

    caractérisée en ce qu'une rugosité moyenne arithmétique Ra de la surface avant de la plaque de circuit en cuivre (3) est de 0,4 µm ou inférieure,

    une rugosité moyenne en dix points Rzjis de la surface avant est de 4 µm ou inférieure, et

    une hauteur maximum Rz de la surface avant est de 5 µm ou inférieure.


     
    2. Plaque de circuit en cuivre céramique (1) selon la revendication 1, dans laquelle le nombre de limites de grains (7) n'est pas inférieur à 20 et pas supérieur à 150 le long de chaque ligne droite de 10-mm dans la surface avant de la plaque de circuit en cuivre (3).
     
    3. Plaque de circuit en cuivre céramique (1) selon la revendication 1 ou 2, dans laquelle le nombre de limites de grains (7) n'est pas inférieur à 80 et pas supérieur à 150 le long de chaque ligne droite de 10-mm dans la surface avant de la plaque de circuit en cuivre (3).
     
    4. Plaque de circuit en cuivre céramique (1) selon l'une quelconque des revendications 1 à 3, dans laquelle :

    une rugosité moyenne arithmétique Ra de la surface avant de la plaque de circuit en cuivre (3) n'est pas inférieure à 0,1 µm et pas supérieure à 0,4 µm,

    une rugosité moyenne en dix points Rzjis de la surface avant n'est pas inférieure à 1,5 µm et pas supérieure à 4 µm, et

    une hauteur maximum Rz de la surface avant n'est pas inférieure à 1 µm et pas supérieure à 5 µm.


     
    5. Plaque de circuit en cuivre céramique (1) selon l'une quelconque des revendications 1 à 4, dans laquelle une asymétrie Rsk d'une courbe de rugosité de la surface avant de la plaque de circuit en cuivre (3) est inférieure à 0.
     
    6. Plaque de circuit en cuivre céramique (1) selon l'une quelconque des revendications 1 à 5, dans laquelle le substrat céramique (2) est un d'un substrat d'oxyde d'aluminium, un substrat de nitrure d'aluminium, ou un substrat de nitrure de silicium.
     
    7. Plaque de circuit en cuivre céramique (1) selon l'une quelconque des revendications 1 à 6, comprenant de plus une couche de liaison (4) fournie entre le substrat céramique (2) et la plaque de circuit en cuivre (3), la couche de liaison (4) incluant Ag et Ti.
     
    8. Plaque de circuit en cuivre céramique (1) selon la revendication 7, dans laquelle lorsque la plaque de circuit en cuivre (3) est uniformément divisée dans une direction d'épaisseur, une proportion d'une zone de surface où Ag existe dans une région de la plaque de circuit en cuivre (3) sur le côté couche de liaison (4) n'est pas inférieure à 20 % et pas supérieure à 80 %.
     
    9. Plaque de circuit en cuivre céramique (1) selon l'une quelconque des revendications 1 à 8, dans laquelle l'épaisseur de la plaque de circuit en cuivre (3) est de 0,6 mm ou supérieure.
     
    10. Plaque de circuit en cuivre céramique (1) selon l'une quelconque des revendications 1 à 9, dans laquelle une quantité de déformation du substrat céramique (2) est inférieure à 0,1 mm.
     
    11. Plaque de circuit en cuivre céramique (1) selon l'une quelconque des revendications 1 à 10, comprenant de plus une plaque en cuivre (8) fournie sur l'autre surface du substrat céramique (2),

    une perforation (9) fournie dans le substrat céramique (2),

    la plaque de circuit en cuivre (3) et la plaque de cuivre (8) conduisant via la perforation (9).


     
    12. Plaque de circuit en cuivre céramique (1) selon la revendication 11, dans laquelle le nombre de limites de grains (7) n'est pas inférieur à 5 et pas supérieur à 250 le long de chaque ligne droite de 10-mm dans une surface avant de la plaque en cuivre (8).
     
    13. Dispositif semi-conducteur (10), comprenant :

    la plaque de circuit en cuivre céramique (1) selon l'une quelconque des revendications 1 à 12 ; et

    un élément semi-conducteur (11) monté sur la plaque de circuit en cuivre (3) via une couche de liaison (12).


     
    14. Dispositif semi-conducteur (10) selon la revendication 13, comprenant de plus une liaison par fil (13) ou une borne en métal (14) liée à la plaque de circuit en cuivre (3).
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description