(19)
(11)EP 3 618 070 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
22.07.2020 Bulletin 2020/30

(43)Date of publication A2:
04.03.2020 Bulletin 2020/10

(21)Application number: 19183484.5

(22)Date of filing:  28.06.2019
(51)International Patent Classification (IPC): 
G11C 11/22(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 28.08.2018 US 201816114272

(71)Applicant: INTEL Corporation
Santa Clara, CA 95054 (US)

(72)Inventors:
  • MORRIS, Daniel H.
    San Francisco, CA California 94131 (US)
  • KIM, Seiyon
    Portland, OR Oregon 97229 (US)
  • AVCI, Uygar E.
    Portland, OR Oregon 97225 (US)
  • YOUNG, Ian A.
    Portland, OR Oregon 97229 (US)

(74)Representative: HGF 
1 City Walk
Leeds LS11 9DX
Leeds LS11 9DX (GB)

  


(54)MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSISTOR GATE


(57) Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a "FE capacitor"). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.







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