(19)
(11)EP 3 621 101 A1

(12)EUROPEAN PATENT APPLICATION

(43)Date of publication:
11.03.2020 Bulletin 2020/11

(21)Application number: 18192466.3

(22)Date of filing:  04.09.2018
(51)International Patent Classification (IPC): 
H01L 21/20(2006.01)
H01L 29/778(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(71)Applicant: IMEC vzw
3001 Leuven (BE)

(72)Inventors:
  • LANGER, Robert
    3001 LEUVEN (BE)
  • WALDRON, Niamh
    3001 LEUVEN (BE)
  • KUNERT, Bernadette
    3001 HEVERLEE (BE)

(74)Representative: Plasseraud IP 
66, rue de la Chaussée d'Antin
75440 Paris Cedex 09
75440 Paris Cedex 09 (FR)

  


(54)INTEGRATED CIRCUIT INCLUDING AT LEAST ONE NANO-RIDGE TRANSISTOR


(57) An integrated circuit is produced from a silicon substrate (1) and includes at least one nano-ridge transistor formed from III-V semiconducting crystal portions (4-7). The III-V portions are grown epitaxially from the silicon substrate using an intermediate portion (3) which is adapted for producing aspect ratio trapping. The nano-ridge transistor has reduced footprint on the silicon substrate, may be adapted for power RF-applications, and can be combined with MOS- or CMOS transistors within one and same integrated circuit.




Description


[0001] The invention relates to an integrated electronic circuit which includes at least one transistor, and a method for producing the same.

-- BACKGROUND OF THE INVENTION --



[0002] III-V semiconductors are deemed to be advantageous materials for producing transistors intended to operate at high frequency and/or for power applications. In particular, they are contemplated for RF-emitters of mobile terminals, in particular smart phones. However, a major issue is to obtain crystal portions of such III-V semiconductors which are almost free of crystal defects, because crystal defects such as dislocations are responsible for a major part of the decrease in the electrical efficiency of a transistor.

[0003] Another issue relates to combining III-V semiconductor-based transistors with MOS- or CMOS technology in a cost-efficient manner. In particular, it is necessary to combine III-V semiconductor-based transistors with using a silicon substrate, and also ensure that the contact level and metallization levels in the complete integrated circuit architecture can be shared between the III-V semiconductor-based transistors and other MOS- and/or CMOS transistors that are also formed from the silicon substrate.

[0004] Additional issues are also reducing the footprint of each III-V semiconductor-based transistor at the substrate surface, and compatibility with high integration levels.

[0005] The article entitled "III/V nano ridge structures for optical applications on patterned 300 mm silicon substrate" by B. Kunert et al., Applied Physics Letters 109, 091101, 2016, discloses producing ridges of III-V material through epitaxial growth from a silicon substrate with (001) orientation of the substrate surface. To this end, the silicon substrate is covered with a silica (SiO2) layer in which trenches are provided so as to expose the silicon surface at the bottom of the trenches. The trenches are 20 nm (nanometer) to 500 nm in width, and are implemented to limit laterally the epitaxial crystal growth during a first period of the growing duration. In this way, selective epitaxial growth is achieved in desired areas of the substrate surface, and the technique known as "Aspect Ratio Trapping", or ART, allows reducing in a great extent the amount of crystal defects that are present in the epitaxially grown material. Lateral overgrowth occurs once the upper surface of the crystal grown becomes higher that the upper edges of the trenches. In this way, a trade-off is obtained between the footprint at the substrate surface and the useful cross-section of the III-V semiconductor portions that are obtained above the silica layer. The silica layer with the trenches may be produced through the well-known Shallow Trench Isolation (STI) process.

[0006] Starting from this situation, one object of the present invention consists in providing III-V semiconductor-based transistors from a silicon substrate, in particular such transistors which are suitable for power RF-applications.

[0007] Additional objects of the invention include compatibility with additional MOS- or CMOS transistors on one and same silicon substrate, and high integration level.

-- SUMMARY OF THE INVENTION --



[0008] For meeting at least one of these objects or others, a first aspect of the present invention proposes an integrated electronic circuit which includes at least one transistor, called nano-ridge transistor, this circuit comprising:
  • a crystal silicon substrate having a silicon surface;
  • the nano-ridge transistor, which comprises at least three III-V semiconducting crystal portions superposed so that at least part of one of the III-V portions is intermediate between respective parts of two other ones of the III-V portions along a superposition direction, and a first one of the III-V portions is connected to the silicon surface of the substrate through an epitaxial material transition, and those of the III-V portions which are next to one another have epitaxial interfaces in-between;
  • at least three electrical connections which are arranged so that three parts of the III-V portions of the nano-ridge transistor are each electrically contacted by at least one of these electrical connections; and
  • an electrically insulating portion which is supported by the silicon substrate and abuts laterally against at least one of the III-V portions.


[0009] According to the invention, the first III-V portion of the nano-ridge transistor is connected to the silicon surface through an intermediate portion which contains the epitaxial material transition. This intermediate portion is also abutted laterally by the electrically insulating portion, and is less in thickness than the electrically insulating portion, or equal, along a direction which is perpendicular to the silicon surface. In addition, the intermediate portion has an aspect ratio greater than unity, preferably greater than or equal to 1.7, this aspect ratio being equal to the thickness of the intermediate portion divided by its width measured parallel to the silicon surface. In this way, the intermediate portion is efficient for producing aspect ratio trapping with respect to crystal defects that may exist in the epitaxially grown material. Thus, the III-V portions can be almost free of crystal defects, and the transistor can have good electrical features. In particular, the transistor can be adapted for power RF-applications.

[0010] Preferably for increasing the efficiency of the aspect ratio trapping, an epitaxial interface between silicon and a material of the first III-V portion may have a V-shape within the intermediate portion, with the V-tip oriented towards the silicon substrate.

[0011] A function of the electrically insulating portion may be in particular to limit transversally a cross-sectional area of the intermediate portion, parallel to the silicon surface, so that aspect ratio trapping is ensured. Depending on various implementations of the invention, the electrically insulating portion may be partially formed through the Shallow Trench Isolation (STI) process, or be part of the buried oxide layer of a Silicon-On-Insulator (SOI) type substrate, or be formed using any material deposition process known in the art, without limitation. Also, the electrically insulating portion may be comprised of several parts which may be individually either formed through the Shallow Trench Isolation (STI) process, or be part of the buried oxide layer of a Silicon-On-Insulator type substrate (SOI), or be formed using any material deposition process known in the art, without limitation.

[0012] According to first configurations, the whole nano-ridge transistor may be lower in height than a part of the electrically insulating portion which has opposed side faces that are parallel or almost parallel. In such configurations, the nano-ridge transistor is contained in a trench through the electrically insulating portion, between the parallel or almost parallel side faces thereof. Alternatively in other configurations, a cross-sectional area of the first III-V portion parallel to the silicon surface may increase when moving away from the silicon surface for at least part of this first III-V portion which is close to the intermediate portion.

[0013] Generally for the invention, the superposition direction of the III-V portions may be perpendicular or parallel to the silicon surface, for at least respective parts of the III-V portions which are superposed along this superposition direction. Possibly, at least one of the epitaxial interfaces existing between two of the III-V portions may have a U-shape in a cross-sectional plane which is perpendicular to the silicon surface, with two U-arms pointing towards the silicon substrate. A length of the U-arms with respect to a width of the first III-V portion parallel to the silicon surface may be any, thereby allowing any area for the interfaces between neighboring ones of the III-V portions.

[0014] In particular when respective parts of the III-V portions are superposed along a superposition direction which is parallel to the silicon surface, at least one of the electrical connections may have a contact interface with one of the III-V portions, which is perpendicular to the silicon surface. This allows having a large contact area between the III-V portion of the nano-ridge transistor and the electrical connection, for reducing a contact resistance existing between the III-V portion and the electrical connection. This may be advantageous in particular for a power transistor.

[0015] Generally for the invention, some of the electrical connections to the nano-ridge transistor may contact this latter through an upper surface thereof which is parallel to the silicon surface, or through at least one of the lateral faces of the nano-ridge transistor which are perpendicular to the silicon surface. But other connection configurations are also possible, without limitation.

[0016] In preferred embodiments of the invention, the integrated circuit may further comprise at least one MOS- or CMOS transistor, and at least one of the electrical connections to the nano-ridge transistor and other electrical connections to the MOS- or CMOS transistor have respective segments which all belong to one and same connection level of the integrated circuit. In this way, one and same integrated circuit can combine nano-ridge transistors according to the invention and MOS- or CMOS transistors for producing a complete function, possibly including both a signal processing and a RF-emitter.

[0017] The nano-ridge transistor may be of various types depending on the III-V portions, including a Heterojunction Bipolar transistor (HBT) and a High Electron-Mobility transistor (HEMT).

[0018] For a heterojunction bipolar transistor, three of the III-V portions form an emitter, a base and a collector of the nano-ridge transistor, respectively, and optionally a fourth one of the III-V portions may form a sub-collector of the nano-ridge transistor. Then, in possible connection configurations, a portion of the silicon substrate which is connected to the first III-V portion through the intermediate portion may form one of the electrical connections, in particular to the emitter or the collector or sub-collector.

[0019] For a high electron-mobility transistor, the first III-V portion forms a non-doped buffer, a second one of the III-V portions forms a non-doped channel, a third one of the III-V portions forms a barrier which has a doping region spatially separate from the channel, and optionally a fourth one of the III-V portions may form a contact layer for the source and drain of the nano-ridge transistor.

[0020] A second aspect of the invention proposes a method for producing an integrated circuit which includes at least one nano-ridge transistor, this method comprising the following steps:
  1. /1/ providing a crystal silicon substrate, with part of a silicon surface thereof which is covered by an electrically insulating bottom portion, and with an aperture through this electrically insulating bottom portion where an area of the silicon surface is selectively exposed, and such that a ratio of a thickness of the electrically insulating bottom portion next to the aperture over a width of this aperture is greater than unity, preferably greater than or equal to 1.7, these thickness and width being measured perpendicular and parallel to the silicon surface, respectively;
  2. /2/from the exposed area of the silicon substrate, growing an intermediate portion and then a first III-V semiconducting crystal portion using an epitaxial growing process, the intermediate portion containing an epitaxial material transition between silicon and the first III-V portion, and being less in thickness than the electrically insulating bottom portion, or equal, along a direction perpendicular to the silicon surface, so that at least the intermediate portion is limited laterally during the epitaxial growing process by the electrically insulating bottom portion around the aperture;
  3. /3/ growing successively at least two further III-V semiconducting crystal portions, using epitaxial growing processes from the first III-V portion and then from the III-V portion just preceding, and so that at least part of one of these III-V portions is intermediate between respective parts of two other ones along a superposition direction; and
  4. /4/ forming at least three electrical connections which are arranged so that three parts of the III-V portions are each electrically contacted by at least one of these electrical connections.


[0021] The intermediate portion has a thickness-to-width ratio, called aspect ratio, greater than unity, preferably greater than 1.7, and the III-V portions form the nano-ridge transistor.

[0022] Generally for the invention, the method also comprises depositing additional electrically insulating material, so that this additional electrically insulating material abuts laterally against at least one of the III-V portions, in addition to the electrically insulating bottom portion abutting against the intermediate portion. The electrically insulating portion recited in the first invention aspect comprises at least both the electrically insulating bottom portion and the additional electrically insulating material. But depending on various invention implementations, the deposition of the additional electrically insulating material may be performed at various times with respect to the steps /1/ to /4/.

[0023] Such method allows obtaining an integrated circuit according to the first invention aspect.

[0024] Preferably, the silicon surface of the substrate may be perpendicular to a [001] crystal direction of silicon and of the III-V portions.

[0025] In advantageous implementations of the invention, step /1/ may comprise the following sub-steps:
  • etching the silicon substrate so as to form a cavity and lower the silicon surface; then
  • forming the electrically insulating bottom portion within the cavity; then
  • hollowing out the aperture and a volume in the electrically insulating bottom portion, the hollowed volume being in line with the aperture along the direction perpendicular to the silicon surface.


[0026] For such implementation, a depth of the hollowed volume may be selected so that the nano-ridge transistor is contained in this hollowed volume below the silicon surface of the substrate as existing before the substrate has been etched. This allows having the nano-ridge transistor below the silicon surface, so that the electrical connections to this nano-ridge transistor are at a same level as electrical connections to MOS- and/or CMOS transistors possibly also included in the same integrated circuit.

[0027] Generally for the invention, the silicon substrate may be of silicon-on-insulator type, thus comprising a bulk crystal silicon substrate, which is covered by a buried oxide layer and an upper layer of crystal silicon. In such case, the buried oxide layer may form the electrically insulating bottom portion, and the aperture is formed through at least part of the buried oxide layer. The intermediate portion is then grown in step /2/ from the bulk crystal silicon substrate, or from a crystal silicon extension which has been grown epitaxially from the bulk crystal silicon substrate in the aperture.

[0028] According to possible improvements of the invention which allow better control of the shape of the intermediate portion, step /1/ may comprise the following sub-steps:
  • forming a sacrificial intermediate template on the substrate, which intermediate template extends from the silicon surface of the substrate and has a shape which matches side faces of the intermediate portion;
  • forming the electrically insulating bottom portion on the silicon surface so that the intermediate template is embedded in the electrically insulating bottom portion;
  • polishing the electrically insulating bottom portion until the intermediate template becomes uncovered; and
  • selectively removing the intermediate template so that the silicon surface of the substrate becomes exposed through the electrically insulating bottom portion, thus forming the aperture.


[0029] Then step /2/ is carried out so that the intermediate portion replaces the intermediate template.

[0030] According to other possible improvements of the invention which allow better control of the shape of the nano-ridge transistor, step /2/ may comprise the following sub-steps:
  • growing the intermediate portion from the exposed area of the silicon substrate using the epitaxial growing process, the intermediate portion being limited laterally when growing by the electrically insulating bottom portion;
  • forming a sacrificial nano-ridge template which extends above and from the intermediate portion and has a shape which matches side faces of the nano-ridge transistor;
  • depositing the additional electrically insulating material on the electrically insulating bottom portion, so that the nano-ridge template is embedded in this additional electrically insulating material;
  • polishing the additional electrically insulating material until the nano-ridge template becomes uncovered;
  • selectively removing the nano-ridge template so that the intermediate portion becomes exposed through the additional electrically insulating material; and
  • growing epitaxially the first III-V portion and the subsequent at least two further III-V portions from the exposed intermediate portion, so that the first and further III-V portions replace the nano-ridge template.

-- BRIEF DESCRIPTION OF THE DRAWINGS --



[0031] The invention will be now described with reference to the following figures which illustrate several embodiments or implementations of the invention, but without limitation with respect to any combination thereof and equivalent step implementations:

Figures 1a-1g are cross-sectional views of integrated electronic circuits according to seven embodiments of the invention.

Figures 2a-2e illustrate steps of a method suitable for producing integrated circuits according figures 1a-1g.

Figures 3a-3b illustrate steps of a method suitable for producing integrated circuits according to an alternative implementation of the invention.

Figures 4a-4c illustrate steps of a method suitable for producing integrated circuits according to another alternative implementation of the invention.

Figures 5a-5b illustrate steps of a method suitable for producing integrated circuits according to still another alternative implementation of the invention.

Figures 6a-6c illustrate steps of a method suitable for producing integrated circuits according to still another alternative implementation of the invention.

Figures 7a-7f illustrate steps of two methods suitable for producing integrated circuits according to still other implementations of the invention.

Figures 8a-8b illustrate steps of a method suitable for producing integrated circuits according to still another alternative implementation of the invention.



[0032] For clarity sake, element sizes which appear in these figures do not correspond to actual dimensions or dimension ratios. Also, same reference numbers which are indicated in different ones of these figures denote identical elements of elements with identical function.

-- DETAILED DESCRIPTION OF THE INVENTION --



[0033] Figure 1a shows a first embodiment of the invention. Reference number 1 denotes a silicon substrate with silicon surface S. Reference number 2 denotes an electrically insulating portion, which may be generally of silica (SiO2) but resulting from composite material formation sequence. In most of the invention embodiments, the portion 2 is comprised of two sub-parts 2a and 2b, which may be formed using different processes and at separate times during the production of the integrated circuit, as described below. A general function of the sub-part 2a, called electrically insulating bottom portion, will be controlling the shape of an intermediate portion 3. The sub-part 2b, called additional electrically insulating material, will be either dedicated to controlling the shape of a nano-ridge transistor, of will have a filling function for integrity of the integrated circuit.

[0034] The nano-ridge transistor of the integrated electronic circuit or Figure 1a is of Heterojunction Bipolar Transistor (HBT) type. It is comprised of at least three III-V semiconductor crystal portions labelled 4, 5 and 6. The III-V portion 4 forms the emitter of the HBT transistor and is doped N+, and the III-V portion 5 forms the base of the HBT transistor and is doped P+. The collector of the HBT transistor may be formed by the portion 6 alone, which is doped N+ in such case. But preferably, the collector may be formed by a combination of the portion 6 doped N- with a further III-V portion 7 which is doped N+ and forms a sub-collector. In a known manner, the emitter-base-collector functions for the III-V portions may be reversed with respect to the location order of these III-V portions from the intermediate portion 3.

[0035] In the invention embodiment of Figure 1a, the III-V portions 4-7 in the center part of the nano-ridge transistor are superposed along a direction D1 which is perpendicular to the silicon surface S. They are also superposed in both lateral parts of the nano-ridge transistor but along another direction D2 which is parallel to the silicon surface S, as this appears in the figure.

[0036] All the III-V portions 4-7 have crystal structures with epitaxial interfaces therebetween. In addition, the intermediate portion 3 contains an epitaxial material transition which forms a bridge between the crystal silicon of the substrate 1 and the crystal composition of the III-V portion 4. Possibly, a bottom part of the intermediate portion 3, close to the substrate 1, may still be of silicon for obtaining an improved epitaxial growth of the III-V materials, with less crystal defects. The upper limit of such bottom part may have a V-shape, with the V-tip pointing toward the substrate 1. In the figures, this V-shape is indicated in broken line, and indicates a possible location where the chemical composition has been started to move from silicon to the III-V composition of the portion 4. As explained below, the function of the intermediate portion 3 is trapping the crystal defects through aspect ratio effect. To this end, a mean width w of the intermediate portion 3 is to be less than a thickness t of the same intermediate portion 3. Put another way, the ratio t/w, called aspect ratio, is to be higher than unity, preferably higher than 1.7. A possible variation - reduction - in width w of the intermediate portion 3 when moving away from the substrate surface S does not matter significantly, and may be due to etching behavior of the bottom portion 2a of the insulating portion 2. Typically, the width w of the intermediate portion 3 may be comprised between 20 nm (nanometer) and 500 nm.

[0037] III-V compositions which are suitable for the portions 3 and 4-7 are well known in the art, so that non-limiting examples are only provided now. Roman numerals III and V refer to columns of the Mendeleev element table. A first possible material combination is AIGaAs (Aluminium-Gallium-Arsenic) for the emitter, and GaAs for both the base and the collector but with different stoichiometric ratios. A second possible material combination is InP (Indium-Phosphorus) for the emitter, and InGaAs for both the base and the collector but again with different stoichiometric ratios. Other possible combinations are based on GaN (Gallium Nitride), with additional aluminium content for the emitter or additional indium content for the base. Still other possible combinations may include Sb (Antimony) contents. The appropriate material combinations for the III-V portions of the nano-ridge transistor are to be selected not only with respect to the electrical material properties, but also with respect to the lattice parameters which have to be compatible with that of silicon through epitaxial growth.

[0038] Reference numbers 14, 15 and 16 denote electrical connections arranged to contact the III-V portions 4, 5 and 7, respectively. These electrical connexions may be produced after the III-V portions 4-7 have been formed, from the circuit side which is opposite the substrate 1 and using a sequence of selective etching and filling steps which is known in the art. In particular, shafts which are etched through the III-V portions 5-7 for connecting the III-V portions 4 or 5 are to be lined internally with insulating material such as silica before being filled with conducting material. Reference signs 14a and 15a denote such insulating liners. The electrical connections 14-16 as shown in Figure 1a all intersect the cross-sectional plane of the view for illustrative purpose, but this may not be the case practically. In particular, it may be convenient to locate the electrical connections 14 and 15 in line with one another along a direction perpendicular to the cross-sectional plane of the view. Also, in practical implementations of the invention, the nano-ridge transistor may be elongated perpendicular to the cross-sectional plane of the view, and each of the electrical connections 14-16 may be repeated along this elongation direction.

[0039] Figure 1b illustrates another contact configuration for a nano-ridge transistor according to the invention, in which the function of electrically connecting the III-V portion 4 is achieved by the intermediate portion 3 and an appropriate conduction path within the substrate 1.

[0040] A method for producing the nano-ridge transistor of Figure 1a is now described with reference to figures 2a-2e. A silica layer may be first formed on the silicon surface S of the substrate 1, with an aperture 30, for forming the so-called electrically insulating bottom portion (Figure 2a). Such bottom portion 2a may be formed during the Shallow-Trench-Isolation (STI) process sequence, which is well known for producing integrated circuits. The aperture 30 is designed for exposing the silicon surface S through the bottom portion 2a. Possibly, the aperture 30 may be elongated perpendicular to the cross-sectional plane of the figure. Then, epitaxial material growth is implemented so as to form successively the intermediate portion 3 and the III-V portion 4. The epitaxial growing process which is used is controlled for varying the material composition in the intermediate portion 3 while maintaining crystal structure formation. Preferably, the epitaxial growing process may be started with depositing pure silicon, thus forming the bottom part of the intermediate portion 3 with V-shaped upper limit. Then the material composition is made to vary until the composition which is desired for the III-V portion 4 is obtained. Also preferably, the composition of the III-V portion 4 may be obtained before the growing surface of the epitaxial growing process has reached the upper surface S2a of the bottom portion 2a. This part of the epitaxially deposited material forms the intermediate portion 3, and it is limited laterally during the material growth by the width w of the aperture 30. So, the crystal material as grown abuts against the side walls of the bottom portion 2a on either side of the aperture 30. According to the invention, the ratio thickness-to-width t/w of the aperture 30 is higher than 1.0, preferably higher than 1.7, so that epitaxial growing of the intermediate portion 3 produces aspect ratio trapping. In this way, the III-V crystal material which is obtained above the upper surface S2a of the bottom portion 2a, for forming the portion 4, can have a low or very low amount of crystal defects. The epitaxial growing process is continued after the growing surface has passed above the surface S2a, preferably from now with constant composition of the material deposited. This continuation of the epitaxial growing process produces the III-V portion 4 in the form of a nano-ridge. In the implementation now described, such nano-ridge is located above the upper surface S2a of the bottom portion 2a, and is no longer restricted laterally, i.e. no solid wall is present to abut against the material grown parallel to the upper surface S2a. In a known manner, the nano-ridge thus grown free of lateral bounds has a width which increases from the edges of the aperture 30, up to a maximum width value, and then is constant in width in a top part of the nano-ridge. Such shape of the III-V portion 4 is shown in Figure 2b. When continuing the epitaxial growing process, the maximum width of the III-V portion 4 increases, above angled intermediate faces which remain with constant angle with respect to the surface S2a, and the total height of the III-V portion 4 also increases. Such growing behaviour is due to the crystal structure of the material deposited, as known in the art of epitaxial deposition.

[0041] A layer of the additional electrically insulating material 2b is then deposited above the bottom portion 2a, so as to embed the III-V portion 4 (Figure 2c). Possibly, the additional material 2b may be silica deposited using a Chemical Vapour Deposition (CVD) process, for example a plasma-enhanced CVD process.

[0042] Chemical-Mechanical Polishing (CMP) is achieved in a next step so as to expose a top part of the III-V portion 4 (Figure 2d). In this way, a top surface S4 of the III-V portion 4 is uncovered and parallel to the silicon surface S.

[0043] Optionally, the layer of the additional insulating material 2b may be further etched, using an etching process that is selective with respect to the III-V material of the portion 4. The Man skilled in integrated circuit production knows such selective etching processes, depending on the additional material 2b and the composition of the III-V portion 4. For example, a wet etching process may be used when the additional material 2b is silica and the III-V portion 4 is of an AIGaAs or InP alloy. Thus, the additional material 2b has a top surface S2b which is lower than the top surface S4 of the III-V portion 4. The difference in height between the top surfaces S2b and S4, denoted h4 in Figure 2e, may be selected as desired by controlling a duration of the etch-back step.

[0044] Then the epitaxial growing process is resumed, or another epitaxial growing process, from the exposed surface of the III-V portion 4. It may be advantageous to achieve a cleaning step beforehand for removing pollutants that may be present on the exposed surface of the III-V portion 4. The composition of the material which is deposited epitaxially is controlled for matching the target compositions for the III-V portions 5-7. The III-V portions 5-7 are thus formed successively, preferably without interrupting the epitaxial growing process between them, but implementing discontinuities in the composition of the material being deposited when changing from the portion 5 to the portion 6, and subsequently from the portion 6 to the portion 7. These compositions have been selected for allowing epitaxial material transitions between the portions 4 and 5, between 5 and 6, and also between 6 and 7, and also so that they will produce the electrical functions desired for the transistor operation. Intrinsic doping of the III-V portions 4-7 is thus obtained.

[0045] The integrated circuit is completed by forming a further additional electrically insulating layer (not shown) on the top surface S2b, so as to embed the III-V portions 4-7 and also forming the so-called first low-k dielectric level, then producing the electrical connections 14-16. Thereafter, metallization layers may be produced in a usual way. For example, the further additional insulating layer may be produced using a process similar to that of the additional insulating material 2b. The integrated circuit of Figure 1a is thus obtained.

[0046] Figure 1c shows an alternative embodiment of the invention, which may be obtained through the production method just described but without implementing the etch-back step of Figure 2e. The epitaxial growing process is thus resumed immediately after the CMP step of Figure 2d, so that the top surfaces S2b and S4 are at a same level above the silicon surface S. The cleaning step for removing pollutants on the exposed surface of the III-V portion 4 may be maintained. Then the epitaxial growing of the III-V portions 5-7 leads to the cross-sectional outline shown in Figure 1c: the III-V portions 5-7 have a same width as the III-V portion 4. Then, the integrated circuit may be completed as mentioned above. In such embodiment of the invention, the III-V portions 4-7 are superposed along the direction D1 in the whole nano-ridge transistor.

[0047] The Man skilled in the art will understand that the cross-sectional outline of the III-V portions 5-7 may be controlled to be different from those represented in figures 1a and 1c. For example, Figure 1d represents still another outline which may be obtained if no additional electrically insulating material 2b is implemented before all the III-V portions 4-7 are grown epitaxially.

[0048] Figure 1e shows another alternative embodiment of the invention, in which the material of the III-V portion 4 has been selected for having an epitaxial growth speed value along the crystal axis which is perpendicular to the silicon surface S greater than the growth speed values along the crystal axes which are parallel to this surface S. In a same way as for the embodiment of Figure 1d, no additional insulating material 2b is implemented before the III-V portions 4-7 have been all grown epitaxially. Preferably, the III-V portion 4 may be comprised of two parts: a core part 4a which is grown epitaxially from the intermediate portion 3, and a surrounding part 4b which is grown epitaxially from the core part 4a and produces the electrical function desired for the III-V portion 4 in the transistor operation. The material of the core part 4a may be selected for its anisotropy in growth speed value so as to provide a desired height-to-width ratio to the core part 4a. In such embodiment, the intermediate portion 3, the core part 4a, the surrounding part 4b and III-V portions 5-7 may be grown successively from the area of the silicon surface S which is limited by the aperture 30, preferably without interruption of the epitaxial growing process. For example, the core part 4a may be comprised of a GaAs alloy, and the surrounding part may be comprised of a InGaP alloy. The integrated circuit may be completed again as already mentioned, but for such embodiment, it may be advantageous to produce the electrical connections 16 so that each one contacts the III-V portion 7 on a side-surface of this latter which is perpendicular to the silicon surface S. Contacts with lower resistance values can be obtained in this way. Figure 1e shows such embodiment, in which the electrical connection to the emitter 4 is optionally achieved through the core part 4a and the intermediate portion 3. In addition, the III-V portions 6 and 7 have been removed at the top of the nano-ridge, for example through CMP after deposition of the additional electrically insulating material 2b, to expose the III-V portion 5 and making it easier to access it with the electrical contact 15. Obviously, the electrical connexions 16 may alternatively have a design similar to that of the electrical connection 15, for contacting the III-V portion 7 at the top face of the nano-ridge as shown in Figure 1f. One advantage thereof is to produce the electrical connections 15 and 16 simultaneously, through common processing steps. Generally, the embodiments of figures 1e and 1f allow even more reduced footprint of the nano-ridge transistor at the silicon surface S, increased junction areas within the transistor, as defined by the height of the nano-ridge. They also allow decoupling of the base thickness as measured perpendicular to the junction surfaces and the base contact resistance value.

[0049] Figure 1g shows still another embodiment of the invention, which may be contemplated in particular when the material of the first III-V portion which is grown after the intermediate portion 3 has a growth speed value parallel to the silicon surface S higher than that along the direction perpendicular to this silicon surface S. For example in such embodiment, the growth order is first the III-V portion 7 which forms the N+ sub-collector, second the III-V portion 6 which forms the N- collector, third the III-V portion 5 which forms the P+ base, and at last the III-V portion 4 which forms the N+ emitter. The additional insulating material 2b may be deposited after all the III-V portions have been epitaxially grown. Then, the III-V portions 4-6 may be etched according to a stair-like outline as represented, for allowing contacting the III-V portions 4, 5 and 7 with the electrical connections 14-16 from above of the transistor, opposite the substrate 1. Possibly, when such nano-ridge transistor is elongated perpendicular to the sectional plane of the figure, each electrical connection may also be elongated parallel to the same direction for reducing all the contact resistance values.

[0050] Figures 3a and 3b relate to another implementation of the invention, in which the complete nano-ridge transistor in contained within the aperture 30 through the electrically insulating bottom portion 2a. To this end, the bottom portion 2a may be thicker than that of Figure 2a, along the direction D1 (Figure 3a). Then the epitaxial growth of the intermediate portion 3 and the III-V portions 4-7 is carried out as described earlier, but with the composition variations all performed before the epitaxial growth surface has reached the upper surface S2a of the bottom portion 2a. Figure 3b also shows an electrical connection 15 to the III-V portion 5, through the top face of the nano-ridge. Similar connections may be used to contact the III-V portions 4 and 7, respectively, but preferably out of the cross-sectional plane of the figure when the nano-ridge transistor is elongated perpendicular to this plane.

[0051] Figures 4a and 4b relate to still another implementation of the invention, which is designed for lowering the nano-ridge transistor below the silicon surface S. This allows easier co-integration of the nano-ridge transistor with MOS- and/or CMOS transistors on one and same silicon substrate 1. As shown in Figure 4a, a cavity is first formed in the silicon substrate 1 from its surface S, and filled with the electrically insulating bottom portion 2a, preferably using the STI process. The thickness t2a of the insulating bottom portion 2a may be increased with respect to usual STI implementations. Then a double selective etching is performed through the insulating bottom portion 2a: a first selective etching step for forming the aperture 30 down to the lower limit BTa of the insulating bottom portion 2a to expose part of the silicon material of the substrate 1, and a second selective etching step for hollowing out a volume 40 within the insulating bottom portion 2a and above the aperture 30. The hollowed volume 40 is to be sized in depth and width for containing the nano-ridge transistor. Reference signs h40 and w40 denote the depth and width of the hollowed volume 40, respectively. The thickness t2a has to be larger than the depth h40 for allowing the thickness t of the intermediate portion 3, so that aspect ratio trapping is effective again. Then, the intermediate portion 3 and the III-V portions 4-7 may be grown epitaxially from the aperture 30 as described above, for example according to the embodiment of Figure 1d. Growth of the III-V portion 7 may be continued until the top face thereof becomes a bit higher than the substrate surface S. The additional electrically insulating material 2b is deposited for complete filling of the volume 40 around the nano-ridge, and the integrated circuit is planarized, for example using a CMP process. The circuit structure of Figure 4b is thus obtained, in which the nano-ridge transistor is flush with the silicon surface S, but located below this surface S. The Man skilled in the art will acknowledge that the circuit substrate thus provided with one or several nano-ridge transistors can be processed thereafter according to the usual MOS- or CMOS process. Indeed, the nano-ridge transistors that have been produced in-substrate previously do not interfere with the MOS- or CMOS transistors to be produced next. In addition, the electrical connections 14-16 can be produced at the same time as those dedicated to connecting the MOS- or CMOS transistors. Figure 4c schematically represents a nano-ridge transistor according to the present invention embodiment and a MOS transistor 100 which are next to each other at the surface S of the silicon substrate 1. Reference numbers 101, 102 and 103 denote the grid, the source and the drain of the MOS transistor 100, and reference numbers 111, 112 and 113 denote the electrical connections to the grid 101, the source 102 and the drain 103. The electrical connections 14-16 and 111-113 all extend in the first low-k dielectric layer 2c which can be implemented as this is usual for MOS- or CMOS integrated circuits.

[0052] Figures 5a and 5b relate to still another implementation of the invention, which is designed from a SOI-type substrate 1. In a known manner, the SOI-type substrate 1 is comprised of a bulk silicon part 1a, a buried oxide (silica) layer 1b and an upper silicon layer 1c. For this embodiment, the upper silicon layer 1c and the buried oxide layer 1b are etched for forming the aperture 30 and the hollowed volume 40. A hard mask used for selectively hollowing out the volume 40 may be left on the upper silicon layer 1c. The aperture 30 extends through the buried oxide layer 1b to the bulk silicon part 1a, so that part of the crystal silicon material of the bulk silicon part 1a is exposed. Then the nano-ridge transistor can be produced in a way similar to that described with reference to Figure 4b, leading to the integrated circuit shown in Figure 5b. The hard mask outside the hollowed volume 40 ensures that no III-V material grows from the upper silicon layer 1c. As just before, such embodiment leads to the nano-ridge transistor located below the active surface S of the substrate 1.

[0053] Figures 6a-6c relate to still another implementation of the invention, for producing a nano-ridge transistor located just below the active surface of the integrated circuit. According to Figure 6a, a nano-ridge transistor which may be similar to that of Figure 1d is produced on a bulk silicon substrate 1. The insulating bottom portion 2a has been preferably obtained through the STI process. The III-V portions 3-7 have been embedded again in a layer of the additional insulating material 2b, for example silica. Then, this layer of the additional insulating material 2b and the insulating bottom portion 2a are etched outside an area A which comprises the III-V portions 3-7 (Figure 6b). The etching is continued until the silicon material of the substrate 1 is exposed, and silicon material is grown epitaxially from the exposed silicon substrate outside the area A, until the silicon growth surface reaches or passes above the top level of the III-V portions 4-7. The integrated circuit being manufactured may then be planarized using CMP process for producing the active circuit surface S0 (Figure 6c), which surface S0 is to be used to process further the integrated circuit, possibly including MOS- or CMOS transistor production.

[0054] Figures 7a-7f relate to still other implementations of the invention, which may allow improved control of the cross-sectional outline of the intermediate portion 3 and/or that of the nano-ridge formed by the III-V portions 4-7. The method starts with forming an intermediate template portion 31 which is intended to determine the shape of the intermediate portion 3. The intermediate template portion 31 is formed on the silicon surface S at a desired location and with the desired width w (Figure 7a). The thickness of the intermediate template portion 31 along the direction D1 is greater than that desired for the intermediate portion 3 and denoted t. The intermediate template portion 31 is thus formed using any process known in the art. It may be comprised of any material which can be etched selectively with respect to that of the electrically insulating bottom portion, and also preferably with respect to silicon. Then, the electrically insulating bottom portion 2a is deposited so as to embed the intermediate template portion 31. The circuit is planarized in a next step for providing the thickness t to both the intermediate template portion 31 and the electrically insulating bottom portion 2a (Figure 7b). Thereafter, the intermediate template portion 31 is removed selectively, so that a circuit configuration similar to that of Figure 2a is obtained. Wet etching may be implemented for the selective removal of the intermediate template portion 31. The method for producing the nano-ridge transistor and the whole integrated circuit can then be completed as already described.

[0055] Alternatively to such continuation of the circuit production method, a nano-ridge template portion 41 may be formed above the intermediate portion 3, with a shape intended to match that desired for the nano-ridge of the III-V portions 4-7 (Figure 7c). The nano-ridge template portion 41 is formed using any process known in the art, and may be comprised of any material which can be etched selectively with respect to the additional electrically insulating material. Then, the layer of the additional electrically insulating material 2b is deposited so as to embed the nano-ridge template portion 41. The circuit is planarized again in a next step for exposing a top part of the nano-ridge template portion 41 (Figure 7d). Thereafter, the nano-ridge template portion 41 is removed selectively, so as to expose the top part of the intermediate portion 3 (Figure 7e). Wet etching may be implemented for the selective removal of the nano-ridge template portion 41. Then, the III-V portions 4-7 can be grown epitaxially so as to replace exactly the nano-ridge template portion 41 (Figure 7f). The method for producing the integrated circuit can be completed again as already described.

[0056] In both cases, the intermediate template portion 31 and the nano-ridge template portion 41 have been said sacrificial in the general part of the description, because they do not remain in the final integrated circuit.

[0057] At least some of the methods previously described for producing a Heterojunction Bipolar Transistor (HBT) may also be implemented for producing a High Electron-Mobility Transistor (HEMT) from a silicon substrate. Figure 8a shows an epitaxial stack which comprises an intermediate portion 3 grown from the silicon material of the substrate 1, a portion 4 which now forms a non-intentionally doped buffer, a portion 5 which now forms a non-intentionally doped channel, a portion 6 which now forms a N- doped barrier, and a portion 7 which now forms a N+ doped contact layer. The portions 4-7 have III-V material compositions as before, but each selected appropriately with respect to the electronic function of the corresponding portion in the HEMT transistor operation. So intrinsic doping may be implemented again. The intermediate portion 3 extends again through the electrically insulating bottom portion 2a, so as to produce aspect ratio trapping. Preferably, the portion 7 may be grown in a manner suitable for wrapping the portion 6 and at least part of the portion 5. It is then patterned for forming separate contact portions 7a and 7b, which are located on opposed sides of the nano-ridge as shown in Figure 8b. The HEMT transistor may also be completed with embedding the transistor in a layer of additional electrically insulating material 2b, and then forming the electrical connections 14-16. In a known manner for such HEMT transistor, the electrical connection 15 is that of the grid, and the electrical connections 14 and 16 are those of the source and the drain, respectively. The Man skilled in the art will understand that such HEMT-type transistor may be combined with any of the transistor structures proposed by the invention and described previously for HBT-type transistors.

[0058] It should be understood that any embodiment of the invention may be combined with any technology used for producing contacts between the electrical connections and the III-V portions of the nano-ridge transistor. In particular, an intermediate material may be used between each electrical connection and the III-V portion contacted, in particular for lowering the contact resistance value and/or for avoiding that an element which belongs to the composition of the electrical connection diffuses into the III-V portion. Also, the well-known technique called contact regrowth may be implemented. It allows decoupling the doping of the III-V portion from that of the contact region.


Claims

1. An integrated circuit which includes at least one transistor, called nano-ridge transistor, said circuit comprising:

- a crystal silicon substrate (1) having a silicon surface (S);

- the nano-ridge transistor, which comprises at least three III-V semiconducting crystal portions (4-7) superposed so that at least part of one of the III-V portions is intermediate between respective parts of two other ones of said III-V portions along a superposition direction, and a first one (4) of said III-V portions is connected to the silicon surface (S) of the substrate (1) through an epitaxial material transition, and those of the III-V portions which are next to one another have epitaxial interfaces in-between;

- at least three electrical connections (14-16) which are arranged so that three parts of the III-V portions (4-7) of the nano-ridge transistor are each electrically contacted by at least one of said electrical connections; and

- an electrically insulating portion (2) which is supported by the silicon substrate (1) and abuts laterally against at least one of the III-V portions (4-7),

wherein the first III-V portion (4) of the nano-ridge transistor is connected to the silicon surface (S) through an intermediate portion (3) which contains the epitaxial material transition, said intermediate portion being also abutted laterally by the electrically insulating portion (2), and less in thickness than said electrically insulating portion, or equal, along a direction (D1) perpendicular to the silicon surface, and having an aspect ratio greater than unity, preferably greater than or equal to 1.7, said aspect ratio being equal to a thickness (t) of said intermediate portion divided by a width (w) of said intermediate portion which is measured parallel to the silicon surface.
 
2. The integrated circuit of claim 1, wherein an epitaxial interface between silicon and a material of the first III-V portion (4) has a V-shape within the intermediate portion (3), with a V-tip oriented towards the silicon substrate (1).
 
3. The integrated circuit of claim 1 or 2, wherein a cross-sectional area of the first III-V portion (4) parallel to the silicon surface (S) increases when moving away from said silicon surface for at least part of said first III-V portion which is close to the intermediate portion (3).
 
4. The integrated circuit of any one of the preceding claims, wherein the superposition direction is perpendicular or parallel to the silicon surface (S), for at least respective parts of the III-V portions (4-7) which are superposed along said superposition direction.
 
5. The integrated circuit of claim 4, wherein at least one of the epitaxial interfaces existing between two of the III-V portions (4-7) has a U-shape in a cross-sectional plane which is perpendicular to the silicon surface (S), with two U-arms pointing towards the silicon substrate (1).
 
6. The integrated circuit of claim 4 or 5, wherein at least one of the electrical connections (14-16) has a contact interface with one of the III-V portions (4-7), said contact interface being perpendicular to the silicon surface (S).
 
7. The integrated circuit of any one of the preceding claims, further comprising at least one MOS- or CMOS transistor (100), wherein at least one of the electrical connections (14-16) to the nano-ridge transistor and other electrical connections (111-113) to the MOS- or CMOS transistor have respective segments which all belong to one and same connection level of the integrated circuit.
 
8. The integrated circuit of any one of claims 1 to 7, wherein the nano-ridge transistor is a heterojunction bipolar transistor, with three of the III-V portions (4-7) forming an emitter, a base and a collector of said nano-ridge transistor, respectively, and optionally a fourth one of the III-V portions forming a sub-collector of said nano-ridge transistor.
 
9. The integrated circuit of claim 8, wherein a portion of the silicon substrate (1) which is connected to the first III-V portion (4) through the intermediate portion (3) forms one of the electrical connections.
 
10. The integrated circuit of any one of claims 1 to 7, wherein the nano-ridge transistor is a high electron-mobility transistor, with the first III-V portion (4) forming a non-doped buffer, a second one (5) of the III-V portions forming a non-doped channel, a third one (6) of said III-V portions forming a barrier which has a doping region spatially separate from the channel, and optionally a fourth one (7) of the III-V portions forming a contact layer for source and drain of said nano-ridge transistor.
 
11. Method for producing an integrated circuit which includes at least one transistor, called nano-ridge transistor, said method comprising the following steps:

/1/ providing a crystal silicon substrate (1), with part of a silicon surface (S) of said substrate which is covered by an electrically insulating bottom portion (2a), and with an aperture (30) through said electrically insulating bottom portion where an area of the silicon surface is selectively exposed, and such that a ratio of a thickness (t) of the electrically insulating bottom portion next to the aperture over a width (w) of said aperture is greater than unity, preferably greater than or equal to 1.7, said thickness and width being measured perpendicular and parallel to the silicon surface, respectively;

/2/from the exposed area of the silicon substrate (1), growing an intermediate portion (3) and then a first III-V semiconducting crystal portion (4) using an epitaxial growing process, wherein the intermediate portion contains an epitaxial material transition between silicon and the first III-V portion, and is less in thickness than the electrically insulating bottom portion (2a), or equal, along a direction (D1) perpendicular to the silicon surface (S), so that at least said intermediate portion is limited laterally during the epitaxial growing process by the electrically insulating bottom portion around the aperture (30);

/3/ growing successively at least two (5-7) further III-V semiconducting crystal portions, using epitaxial growing processes from the first III-V portion (4) and then from the III-V portion just preceding, and so that at least part of one of said III-V portions is intermediate between respective parts of two other ones of said III-V portions along a superposition direction; and

/4/forming at least three electrical connections (14-16) which are arranged so that three parts of the III-V portions (4-7) are each electrically contacted by at least one of said electrical connections,

wherein the intermediate portion (3) has a thickness-to-width ratio, called aspect ratio, greater than unity, preferably greater than 1.7, and the III-V portions (4-7) form the nano-ridge transistor,
and the method also comprising depositing additional electrically insulating material (2b), so that said additional electrically insulating material abuts laterally against at least one of the III-V portions (4-7), in addition to the electrically insulating bottom portion (2a) abutting against the intermediate portion (3).
 
12. The method of claim 11, wherein the silicon surface (S) of the substrate (1) is perpendicular to a [001] crystal direction of silicon and of the III-V portions (4-7).
 
13. The method of claim 11 or 12, implemented so as to produce an integrated circuit which is in accordance with any one of claims 2 to 10.
 
14. The method of any one of claims 11 to 13, wherein step /1/ comprises the following sub-steps:

- etching the silicon substrate (1) so as to form a cavity and lower the silicon surface (S); then

- forming the electrically insulating bottom portion (2a) within the cavity; then

- hollowing out the aperture (30) and a volume (40) in the electrically insulating bottom portion (2a), the hollowed volume being in line with the aperture (30) along the direction (D1) perpendicular to the silicon surface (S),

wherein a depth of the hollowed volume (h40) is selected so that the nano-ridge transistor is contained in said hollowed volume below the silicon surface (S) of the substrate (1) as existing before the substrate has been etched.
 
15. The method of any one of claims 11 to 14, wherein the silicon substrate (1) is of silicon-on-insulator type and comprises a bulk crystal silicon substrate (1a), which is covered by a buried oxide layer (1b) and an upper layer (1c) of crystal silicon, and wherein the buried oxide layer forms said electrically insulating bottom portion (2a), and the aperture (30) is formed through at least part of said buried oxide layer, and wherein the intermediate portion (3) is grown in step /2/from the bulk crystal silicon substrate, or from a crystal silicon extension which has been grown epitaxially from the bulk crystal silicon substrate in the aperture.
 
16. The method of any one of claims 11 to 15, wherein step /1/ comprises the following sub-steps:

- forming a sacrificial intermediate template (31) on the substrate (1), which intermediate template extends from the silicon surface (S) of said substrate and has a shape which matches side faces of the intermediate portion (3);

- forming the electrically insulating bottom portion (2a) on the silicon surface (S) so that the intermediate template (31) is embedded in said electrically insulating bottom portion;

- polishing the electrically insulating bottom portion (2a) until the intermediate template (31) becomes uncovered; and

- selectively removing the intermediate template (31) so that the silicon surface (S) of the substrate (1) becomes exposed through the electrically insulating bottom portion (2a), thereby forming the aperture (30), and wherein step /2/ is carried out so that the intermediate portion (3) replaces the intermediate template (1).


 
17. The method of any one of claims 11 to 16, wherein step /2/ comprises the following sub-steps:

- growing the intermediate portion (3) from the exposed area of the silicon substrate (1) using the epitaxial growing process, said intermediate portion being limited laterally when growing by the electrically insulating bottom portion (2a);

- forming a sacrificial nano-ridge template (41) which extends above and from the intermediate portion (3) and has a shape which matches side faces of the nano-ridge transistor;

- depositing the additional electrically insulating material (2b) on the electrically insulating bottom portion (2a), so that the nano-ridge template (41) is embedded in said additional electrically insulating material;

- polishing the additional electrically insulating material (2b) until the nano-ridge template (41) becomes uncovered;

- selectively removing the nano-ridge template (41) so that the intermediate portion (3) becomes exposed through the additional electrically insulating material (2b); and

- growing epitaxially the first III-V portion (4) and the subsequent at least two further III-V portions (5-7) from the exposed intermediate portion (3), so that said first and further III-V portions replace the nano-ridge template (41).


 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Non-patent literature cited in the description