(19)
(11)EP 3 623 940 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
06.05.2020 Bulletin 2020/19

(43)Date of publication A2:
18.03.2020 Bulletin 2020/12

(21)Application number: 19183497.7

(22)Date of filing:  28.06.2019
(51)Int. Cl.: 
G06F 9/30  (2018.01)
G06F 9/38  (2018.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 14.09.2018 US 201816131382

(71)Applicant: Intel Corporation
Santa Clara, CA 95054 (US)

(72)Inventors:
  • HUGHES, Christopher J.
    Santa Clara, CA 95051 (US)
  • TOLL, Bret
    Hillsboro, OR 97124 (US)
  • BAUM, Dan
    34354 Haifa (IL)
  • OULD-AHMED-VALL, Elmoustapha
    Chandler, AZ 85226 (US)
  • SADE, Raanan
    3658900 KIbutz Sarid (IL)
  • VALENTINE, Robert
    36054 Kiryat Tivon (IL)
  • CHARNEY, Mark J.
    Lexington, MA 02421 (US)
  • HEINECKE, Alexander F.
    San Jose, CA 95134 (US)

(74)Representative: Samson & Partner Patentanwälte mbB 
Widenmayerstraße 6
80538 München
80538 München (DE)

  


(54)SYSTEMS AND METHODS FOR PERFORMING HORIZONTAL TILE OPERATIONS


(57) Disclosed embodiments relate to systems and methods for performing instructions specifying horizontal tile operations. In one example, a processor includes fetch circuitry to fetch an instruction specifying a horizontal tile operation, a location of a M by N source matrix comprising K groups of elements, and locations of K destinations, wherein each of the K groups of elements comprises the same number of elements, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction by generating K results, each result being generated by performing the specified horizontal tile operation across every element of a corresponding group of the K groups, and writing each generated result to a corresponding location of the K specified destination locations.