(19)
(11)EP 3 629 374 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
22.07.2020 Bulletin 2020/30

(43)Date of publication A2:
01.04.2020 Bulletin 2020/14

(21)Application number: 19183099.1

(22)Date of filing:  28.06.2019
(51)International Patent Classification (IPC): 
H01L 27/108(2006.01)
H01L 27/06(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 25.09.2018 US 201816140890

(71)Applicant: INTEL Corporation
Santa Clara, CA 95054 (US)

(72)Inventors:
  • SHARMA, Abhishek A.
    OR 97124 Hillsboro (US)
  • RACHMADY, Willy
    Beaverton, OR Oregon 97007 (US)
  • PILLARISETTY, Ravi
    Portland, OR Oregon 97201 (US)
  • DEWEY, Gilbert
    Beaverton, OR Oregon 97006 (US)
  • KAVALIEROS, Jack T.
    Portland, OR Oregon 97229 (US)

(74)Representative: 2SPL Patentanwälte PartG mbB 
Postfach 15 17 23
80050 München
80050 München (DE)

  


(54)STACKED-SUBSTRATE DRAM SEMICONDUCTOR DEVICES


(57) A DRAM integrated circuit device is described in which at least some of the peripheral circuits associated with the memory arrays are provided on a first substrate. The memory arrays are provided on a second substrate stacked on the first substrate, thus forming a DRAM integrated circuit device on a stacked-substrate assembly. Vias that electrically connect the memory arrays on the second substrate to the peripheral circuits on the first substrate are fabricated using high aspect ratio via fabrication techniques.







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