(19)
(11)EP 3 635 777 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
13.01.2021 Bulletin 2021/02

(21)Application number: 18724587.3

(22)Date of filing:  23.05.2018
(51)International Patent Classification (IPC): 
H01L 21/762(2006.01)
(86)International application number:
PCT/EP2018/063427
(87)International publication number:
WO 2018/215498 (29.11.2018 Gazette  2018/48)

(54)

METHOD FOR MINIMIZING DISTORTION OF A SIGNAL IN A RADIOFREQUENCY CIRCUIT

VERFAHREN ZUR MINIMIERUNG DER VERZERRUNG EINES SIGNALS IN EINER HOCHFREQUENZSCHALTUNG

PROCÉDÉ PERMETTANT DE RÉDUIRE À UN MINIMUM LA DISTORSION D'UN SIGNAL DANS UN CIRCUIT RADIOFRÉQUENCE


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 23.05.2017 FR 1754567

(43)Date of publication of application:
15.04.2020 Bulletin 2020/16

(73)Proprietor: Soitec
38190 Bernin (FR)

(72)Inventors:
  • BROEKAART, Marcel
    38570 Theys (FR)
  • ALLIBERT, Frédéric
    38000 Grenoble (FR)
  • DESBONNET, Eric
    38660 Lumbin (FR)
  • RASKIN, Jean-Pierre
    1348 Louvain-La-Neuve (BE)
  • RACK, Martin
    1348 Louvain-La-Neuve (BE)

(74)Representative: Regimbeau 
20, rue de Chazelles
75847 Paris Cedex 17
75847 Paris Cedex 17 (FR)


(56)References cited: : 
EP-A1- 2 503 592
EP-A1- 3 144 958
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD OF THE INVENTION



    [0001] The present invention relates to a method for minimizing harmonic distortion and/or intermodulation distortion of a signal in a radiofrequency circuit.

    PRIOR ART



    [0002] Radiofrequency (RF) circuits formed on semiconductor substrates suffer from the non-linearity of the material forming said substrates.

    [0003] This non-linearity brings about interactions between the material of the substrate and the signal transmitted within the radiofrequency circuit, which interactions are reflected in harmonic distortion and/or intermodulation distortion (IMD).

    [0004] For optimum performance of the radiofrequency circuit, it is therefore sought to maximize the linearity of the substrate.

    [0005] In this respect, successive standards in the field of telecommunications are increasingly stringent.

    [0006] In radiofrequency applications, it is known to use substrates of silicon on insulator (SOI) type comprising, from its surface to its base, an electrically conductive thin layer, for example made of silicon, an electrically insulating layer and a silicon carrier substrate with high electrical resistivity.

    [0007] In the present text, 'high resistivity' is understood to mean an electrical resistivity of greater than 500 Ω.cm, preferably greater than 1000 Ω.cm, or even more.

    [0008] Figure 1A thus illustrates a perspective view of a radiofrequency circuit formed on an SOI whose carrier substrate is a silicon substrate 1 with high electrical resistivity. Said substrate is coated with an electrically insulating layer 2, for example made of silicon oxide (SiO2). Metal lines L intended to conduct the signal are formed on the electrically insulating layer 2. The semiconductor thin layer of the SOI, which layer is situated on the electrically insulating layer 2, has been removed at least locally in order to deposit the lines L, and is therefore not visible in Figure 1A or in Figures 1B and 1C described hereinafter.

    [0009] However, the linearity of such substrates remains too limited for certain applications.

    [0010] Moreover, SOI substrates with a charge trap layer situated under the electrically insulating layer have been developed. These substrates are usually referred to using the term 'trap rich' in the field of radiofrequency applications.

    [0011] Figure 1B thus illustrates a perspective view of a radiofrequency circuit successively comprising a silicon substrate 1 with high electrical resistivity, a polycrystalline silicon layer 3, an electrically insulating layer 2, for example made of silicon oxide, and metal lines L intended to conduct the signal. The polycrystalline silicon layer 3 performs the charge-trapping function by virtue of the presence of grain boundaries at which electric charges present under the electrically insulating layer can be trapped.

    [0012] Figure 1C illustrates a perspective view of a radiofrequency circuit with what is termed a 'double BOX' (or 'double buried oxide') structure, that is to say successively comprising a silicon substrate 1 with high electrical resistivity, a first electrically insulating layer 2a (for example made of silicon oxide), a polycrystalline silicon layer 3, a second electrically insulating layer 2b (for example made of silicon oxide), and metal lines L intended to conduct the signal.

    [0013] Although substrates of 'trap rich' type give good results in radiofrequency applications, increasing the requirements in terms of circuit performance makes it necessary to develop additional means for minimizing the generation of parasitic harmonics.

    [0014] The state of the art is disclosed in the following two documents: Document EP2503592 discloses a trap rich = poly-crystaline sylicon layer. It aims to define a method of manufacturing a HR-SOI (High Resistivity Silicon on Insulator) type substrate that minimises the loss of resistivity of the polycrystalline silicon layer.

    [0015] Document EP3144958 aims to reduce the thickness of the polycrystalline silicon layer without deteriorating the trapping efficiency of said layer.

    SUMMARY OF THE INVENTION



    [0016] One aim of the invention is therefore to design a method for controlling a radiofrequency circuit that makes it possible to reduce harmonic distortion and/or intermodulation distortion caused by the non-linearity of the substrate on which said circuit is formed.

    [0017] To this end, the invention proposes a method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing said distortion as a function of a power of the input or output signal exhibits a trough around a given power, said method being characterized in that it comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference chosen so as to move said trough towards a given operating power of the radiofrequency circuit.

    [0018] Particularly advantageously, said electrical potential difference is chosen so as to comply with the following equation: Vpk = |VGB - VFB|, where Vpk is the peak voltage of the radiofrequency signal and VFB is the flat band voltage of the metal (semiconductor lines of the radiofrequency circuit) - insulator - semiconductor structure.

    [0019] According to one embodiment, the semiconductor substrate has an electrical resistivity of greater than 500 Ω.cm.

    [0020] According to one embodiment, a polycrystalline silicon layer is arranged between the semiconductor substrate and the electrically insulating layer.

    [0021] Optionally, an additional electrically insulating layer may be arranged between the semiconductor substrate and the polycrystalline silicon layer.

    [0022] According to one embodiment, the semiconductor substrate is made of silicon.

    [0023] According to one embodiment of the invention, the method comprises adjusting the electrical potential difference applied between the semiconductor substrate and the radiofrequency circuit depending on the operating power of the radiofrequency circuit.

    [0024] Advantageously, the method may furthermore comprise measuring the temperature of the radiofrequency circuit, and adjusting the electrical potential difference applied between the semiconductor substrate and the radiofrequency circuit depending on the measured temperature.

    [0025] The curve representing the distortion of the signal is typically a curve of the level of generation of the second or of the third harmonic of the input signal or of the output signal as a function of the power of the input signal or of the fundamental component of the output signal.

    [0026] Another subject of the invention relates to a radiofrequency device in which such harmonic and/or intermodulation distortion is able to be minimized.

    [0027] Said device comprises:
    • a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer,
    • a contact connected electrically to the semiconductor substrate,
    • a means for applying a potential difference between said contact and the radiofrequency circuit,
    said device being characterized in that said application means is configured to apply said potential difference chosen so as to move a trough around a given power in a curve representing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in said circuit as a function of a power of the input or output signal towards a given operating power of said radiofrequency circuit.

    [0028] According to one embodiment, said means for applying the potential difference comprises a voltage generator and a voltage control module configured to adjust the voltage of said generator depending on the operating power of the radiofrequency circuit.

    [0029] According to one embodiment, the semiconductor substrate has an electrical resistivity of greater than 500 Ω.cm.

    [0030] According to one embodiment, a polycrystalline silicon layer is arranged between the semiconductor substrate and the electrically insulating layer.

    [0031] Optionally, an additional electrically insulating layer is arranged between the semiconductor substrate and the polycrystalline silicon layer.

    [0032] According to one embodiment, the semiconductor substrate is made of silicon.

    [0033] The device may furthermore comprise a temperature sensor coupled to the means for applying the potential difference, said means being configured to adjust said potential difference depending on the temperature measured by said sensor.

    DESCRIPTION OF THE FIGURES



    [0034] Other advantages and features of the invention will emerge from the following detailed description, with reference to the appended drawings, in which:
    • Figure 1A is a perspective view of a radiofrequency circuit formed on an SOI substrate with high electrical resistivity;
    • Figure 1B is a perspective view of a radiofrequency circuit formed on an SOI substrate of 'trap rich' type;
    • Figure 1C is a perspective view of a radiofrequency circuit formed on a 'trap rich' SOI of 'double BOX' type;
    • Figure 2 shows curves of the level of generation of the third harmonic (in dBm) as a function of the level of the first harmonic of the output signal (in dBm), for a silicon substrate with standard resistivity, for various potential differences applied between the substrate and the radiofrequency circuit;
    • Figure 3 shows curves of the level of generation of the second harmonic (in dBm) as a function of the level of the first harmonic of the input signal (in dBm), for a 'trap rich' SOI substrate with a silicon carrier substrate with high resistivity;
    • Figure 4 shows various configurations of the voltage to be applied between the semiconductor substrate and the radiofrequency circuit in order to attain the flat band voltage of the metal - insulator - semiconductor structure as a function of the peak voltage of the signal;
    • Figure 5 shows the principle of the performance optimization afforded by adjusting the position of the trough of the level of generation of the second harmonic as a function of the level of the first harmonic;
    • Figure 6 shows curves of the level of generation of the second harmonic (in dBm) as a function of the level of the first harmonic of the output signal (in dBm), for an SOI substrate with a silicon carrier substrate with high resistivity, for various potential differences applied between the semiconductor substrate and the radiofrequency circuit;
    • Figures 7A and 7B show curves of the level of generation of the second harmonic as a function of the level of the first harmonic for a 'trap rich' SOI substrate having, under the electrically insulating layer, a polycrystalline silicon layer, with a thickness of 0.4 µm and with a thickness of 1.7 µm, respectively, at temperatures of 60° and 90°C,
    • Figures 8A to 8C illustrate embodiments of the invention applied to an SOI substrate with a silicon carrier substrate with high resistivity, a 'trap rich' SOI substrate and a 'trap rich double BOX' SOI substrate, respectively.


    [0035] To make the figures legible, the various layers forming the substrates are not necessarily shown to scale.

    DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION



    [0036] The invention is based on the observation, with certain semiconductor substrates coated with an electrically insulating layer, of a local drop of the level of generation of a harmonic or of the level of intermodulation for a certain power of the input signal.

    [0037] The term 'level of generation of a harmonic' is understood, in the present text, to mean the power of a given harmonic measured at the output of the radiofrequency circuit, expressed in dBm. This power may be expressed for a power of the fundamental component of the input signal (the notation 'in' will then be used) or of the output signal (the notation 'out' will then be used).

    [0038] In the remainder of the description, consideration will often be given to the level of generation of the second harmonic (denoted HD2), but the invention may also be implemented with consideration to the level of a higher generated harmonic, for example the third harmonic (denoted HD3), or even a level of intermodulation. In a general manner, these levels represent the non-linearity of the substrate.

    [0039] In the remainder of the description, the example will generally be taken of a silicon substrate with high resistivity coated with a layer of silicon oxide, but the invention applies more generally to a semiconductor substrate coated with an electrically insulating layer. In general, these semiconductor substrates belong to SOI substrates whose semiconductor thin layer is at least locally removed in order to deposit the electrically conductive lines on the electrically insulating layer (the semiconductor thin layer may be kept in other regions of the substrate so as to form electronic components). As an alternative, the electrically insulating layer could be formed by oxidation of a semiconductor substrate, with high resistivity or with standard resistivity, without an SOI substrate being formed.

    [0040] A drop in the level of generation of the third harmonic is visible in Figure 2, which relates to a radiofrequency circuit formed on an SOI comprising a silicon substrate having a standard electrical resistivity (lower than the abovementioned high resistivity, for example of the order of 10 Ω.cm), for various potential differences VGB applied between the silicon substrate and the radiofrequency circuit.

    [0041] A drop in the level of generation of the second harmonic is also visible in Figure 3, which relates to a radiofrequency circuit formed on an SOI comprising a silicon substrate having a high electrical resistivity, for a given potential difference VGB applied between the silicon substrate with high electrical resistivity of the 'trap rich' SOI substrate and the radiofrequency circuit.

    [0042] Figures 2 and 3 show the level of generation of the third and of the second harmonic of the output signal, respectively, expressed in dBm, as a function of the level of the first harmonic, that is to say the fundamental component, of the input signal, also expressed in dBm.

    [0043] It is recalled that the powers Pin and Pout in dBm are simply offset by an interval corresponding to the losses of the conductive line in dBm. For example, if the losses are 3 dBm over the whole line at the frequency of the fundamental component, and a trough is observed in the curve Pin vs. HD2 at +20 dBm from Pin, this trough will be located at +17 dBm from Pout_H1 in the curve Pout_H1 vs. HD2.

    [0044] It is seen that these curves have a trough with a significant amplitude in a given range of the power Pin, this range being of small width and generally situated in the high power values, around a value denoted PDip in Figure 3.

    [0045] The presence of this trough implies that, surprisingly, in this power range, the level of generation of the third, respectively of the second, harmonic is substantially lower than if the curve had remained substantially straight.

    [0046] The inventors account for the position of this trough through the input power corresponding to the situation where the peak amplitude of the radiofrequency signal, denoted Vpk, reaches or exceeds the flat band voltage, denoted VFB. This trough therefore appears for a level of power in watts PDip, associated with a signal amplitude VpkDip, and expressed by the following equations:



    [0047] Therefore:

    where ZREF is the reference impedance of the system (generally 50 ohms), VGB is the electrical potential difference applied between the radiofrequency circuit and the semiconductor substrate, and VFB is the flat band voltage of the semiconductor - insulator - metal structure. This voltage characterizes a state of the semiconductor substrate under the electrically insulating layer that is neither in desertion regime nor in accumulation regime. In this state, the Fermi levels of the metal, of the insulator and of the semiconductor material are aligned.

    [0048] The trough thus can be positioned at the desired level of power by applying an appropriate potential difference VGB, so as to comply with the above equations.

    [0049] As illustrated in Figures 4 (a) to (d), various situations exist, depending on the positions of the voltages Vpk and VFB.

    [0050] In any case, it is possible to define a potential difference VGB that makes it possible to comply with this equation VpkDiP = |VGB - VFB| or at the very least to get close to it.

    [0051] It will be noted that there may be an attenuation along the conductive line, expressed in dB/mm. The loss in terms of Vpk on a substrate with high resistivity along a line of a few millimetres may thus be of a factor of 2.

    [0052] In such a case, it is possible, instead of considering a single value Vpk as above, to distinguish the terminals Vpk_in and Vpk_out:





    [0053] In particular, when consideration is given to a curve of HD2 of Pout as a function of H1 of Pout, and the trough PDip is located at a certain output power point (H1 of Pout), the value of Vpk to be considered is Vpk_out.

    [0054] It will be noted in the case of Figure 3 that the radiofrequency circuit is formed on an SOI substrate of 'trap rich' type that is of poor quality, that is to say for which the polycrystalline silicon layer has partially recrystallized. The trough phenomenon is attributed to the fact that the behaviour of the substrate is then similar to that of a silicon substrate with high resistivity.

    [0055] The inventors have therefore exploited the abovementioned phenomenon so as to minimize harmonic distortion and/or intermodulation distortion, as they are able to design and/or adjust the position of the trough to the desired operating power, so as to minimize the distortion or intermodulation terms that are generated.

    [0056] Thus, as is seen in Figure 5, if the straight line A, which corresponds to a first substrate, not having the abovementioned trough, is compared with the curve B of a second substrate having the trough, it is observed that, for a given power of the input signal, the level of generation of the second harmonic reaches a ceiling value that is below the value reached with the first curve.

    [0057] In the example illustrated, for a power Pin of the input signal corresponding to 20 dBm, the level of generation of the second harmonic is -80 dBm for the first substrate, and -95 dBm at most for the second substrate. Thus, there is a gain of around 15 dBm with the second substrate if the level of the first harmonic of the input signal is within the range corresponding to the trough.

    [0058] Adjusting the potential difference VGB makes it possible to move the trough of the distortion curve into a range that corresponds to the power of the input signal.

    [0059] Figure 6 shows curves of the level of generation of the second harmonic (in dBm) as a function of the level of the first harmonic of the output signal (in dBm), for various applied potential differences VGB.

    [0060] As can be seen in this figure, varying VGB makes it possible to significantly move the trough.

    [0061] According to one embodiment, the potential difference VGB is fixed.

    [0062] According to another embodiment, the potential difference VGB is adjusted dynamically, during operation of the radiofrequency circuit, so as to ensure that the trough of the distortion curve always corresponds to a given operating power of the radiofrequency circuit; said power may be in particular the maximum power of the input signal, or another power value chosen by a person skilled in the art.

    [0063] To this end, the radiofrequency device comprises a loop for servo-controlling the potential difference VGB to the power Pin of the input signal.

    [0064] It will be noted that the design of the semiconductor substrate and of the electrically insulating layer may make it possible to adjust the flat band voltage VFB. Thus, for example, the voltage VFB may be modified by modifying the quantity of electric charges in the electrically insulating layer. The voltage VFB may also be modified by doping the semiconductor substrate, but this solution is less preferable in particular in the case of a substrate with high resistivity given the fact that the dopants may lead to a reduction in the electrical resistivity of the semiconductor substrate and therefore to an amplification of its non-linear nature.

    [0065] Moreover, measurements have demonstrated the effect of the temperature of the radiofrequency circuit on the appearance of the trough in the distortion curve.

    [0066] Figures 7A and 7B thus show curves of the level of generation of the second harmonic as a function of the level of the first harmonic for a 'trap rich' SOI substrate having, under the electrically insulating layer, a polycrystalline silicon layer with a thickness of 0.4 µm (Figure 7A) and with a thickness of 1.7 µm (Figure 7B), at temperatures of 60° and 90°C.

    [0067] The curves are substantially linear for a temperature of 60°C.

    [0068] For a temperature of 90°C, a trough is observed in the curve of Figure 7A, whereas that of Figure 7B remains substantially linear.

    [0069] Figure 7A therefore demonstrates an effect of the temperature on the appearance of a trough in the level of generation of the second harmonic. This effect appears to be explained by the fact that the temperature generates charge carriers, which will fill the traps corresponding to the grain boundaries of the polycrystalline silicon whose thickness is small. The result of this is that, for a high power Pin, the 'trap rich' SOI substrate behaves like a substrate with high resistivity, and therefore becomes sensitive to the flat band phenomenon.

    [0070] The potential difference VGB may therefore advantageously be defined at the operating temperature envisaged for the radiofrequency circuit.

    [0071] It is also possible to exploit this observation to control the movement of the trough depending on the temperature.

    [0072] Thus, by virtue of a temperature sensor that makes it possible to sense the temperature of the radiofrequency circuit or of its immediate surroundings, it is possible to take into account the measured temperature so as to control the potential difference VGB, in order to ensure that the trough is always within the operating power range of the radiofrequency circuit (for example the maximum power of the signal).

    [0073] Such a temperature sensor may for example be of the type described in the article by Deng F, He Y, Li B, et al. Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips. Passaro VMN, ed. Sensors (Basle, Switzerland). 2015;15(5):11442-11453. doi:10.3390/s150511442.

    [0074] In practice, the invention may be implemented as follows.

    [0075] In a manner known per se, the radiofrequency circuit is designed, this generally involving designing the semiconductor substrate and the electrically insulating layer on which it is formed.

    [0076] From this design, it is possible to derive the flat band voltage of the metal - insulator - semiconductor structure.

    [0077] Where appropriate, it is possible to choose to modify the flat band voltage, this for example involving modifying the quantity of charges in the electrically insulating layer.

    [0078] Moreover, with knowledge of the targeted power Pin and the associated peak voltage Vpk, it is possible to derive, from the equation Vpk = |VGB - VFB|, the value of the potential difference VGB to be applied between the radiofrequency circuit and the semiconductor substrate.

    [0079] This potential difference may be applied in various ways. In general, it requires a voltage generator, advantageously coupled to a module for controlling the voltage, which module is configured to adjust the voltage of said generator depending on the operating power of the radiofrequency circuit. Said voltage generator is separate from the device for powering the radiofrequency circuit. Moreover, a contact has to be connected electrically to the semiconductor substrate, in order to apply a reference potential to said substrate.

    [0080] Figure 8A relates to an SOI comprising a silicon substrate with high resistivity, as in Figure 1A, whose reference signs are taken up by Figure 8A. In this case, a back gate layer 4, made of an electrically conductive material and situated on the back face of the substrate 1 (i.e. on the side opposite the dielectric layer 2) is grounded, as are the two lateral conductive lines. The central conductive line, for its part, is set to the potential VGB. As an alternative, the central conductive line could be grounded, and the other electrodes (lateral conductive lines and back gate layer) set to the potential -VGB.

    [0081] Figure 8B relates to a 'trap rich' SOI comprising a polycrystalline silicon layer under the electrically insulating layer, as in Figure 1B, whose reference signs are taken up by Figure 8B. In this case, an electrically conductive back gate layer 4 situated on the back face of the substrate 1 (i.e. on the side opposite the dielectric layer 2) is grounded, as are the two lateral conductive lines. The central conductive line, for its part, is set to the potential VGB. As an alternative, the central conductive line could be grounded, and the other electrodes (lateral conductive lines and back gate layer) set to the potential -VGB.

    [0082] Figure 8C relates to a 'trap rich double BOX' SOI comprising a polycrystalline silicon layer between two electrically insulating layers, as in Figure 1C, whose reference signs are taken up by Figure 8C. In this case, an electrically conductive back gate layer 4 situated on the back face of the substrate 1 (i.e. on the side opposite the dielectric layer 2b) is grounded, as are the two lateral conductive lines. The central conductive line, for its part, is set to the potential VGB. As an alternative, the central conductive line could be grounded, and the other electrodes (lateral conductive lines and back gate layer) set to the potential -VGB.

    [0083] It will be noted that it is not essential to provide a back gate layer on the back face of the semiconductor substrate in order to make it possible to apply the potential difference VGB. A reference potential may be set in the semiconductor substrate by any other means known to a person skilled in the art, such as a via extending from the front face through the electrically insulating layer as far as into the semiconductor substrate.

    REFERENCES



    [0084] Deng F, He Y, Li B, et al. Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips. Passaro VMN, ed. Sensors (Basle, Switzerland). 2015;15(5):11442-11453. doi:10.3390/s150511442


    Claims

    1. Method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit (L) formed on a semiconductor substrate (1) coated with an electrically insulating layer (2, 2b), wherein a curve representing said distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip),
    said method being characterized in that it comprises applying, between the radiofrequency circuit (L) and the semiconductor substrate (1), an electrical potential difference (VGB) chosen so as to move said trough towards a given operating power of the radiofrequency circuit.
     
    2. Method according to claim 1, wherein said electrical potential difference (VGB) is chosen so as to comply with the following equation: Vpk = |VGB - VFB|, where Vpk is the peak voltage of the radiofrequency signal and VFB is the flat band voltage.
     
    3. Method according to either of claims 1 and 2, wherein the semiconductor substrate (1) has an electrical resistivity of greater than 500 Ω.cm.
     
    4. Method according to claim 3, wherein a polycrystalline silicon layer (3) is arranged between the semiconductor substrate (1) and the electrically insulating layer (2, 2b).
     
    5. Method according to claim 4, wherein an additional electrically insulating layer (2a) is arranged between the semiconductor substrate (1) and the polycrystalline silicon layer (3).
     
    6. Method according to one of claims 1 to 5, wherein the semiconductor substrate (1) is made of silicon.
     
    7. Method according to one of claims 1 to 6, comprising adjusting the electrical potential difference (VGB) applied between the semiconductor substrate (1) and the radiofrequency circuit depending on the operating power of the radiofrequency circuit.
     
    8. Method according to one of claims 1 to 7, furthermore comprising measuring the temperature of the radiofrequency circuit, and adjusting the electrical potential difference (VGB) applied between the semiconductor substrate (1) and the radiofrequency circuit depending on the measured temperature.
     
    9. Method according to one of claims 1 to 8, wherein the curve representing the distortion of the signal is a curve of the level of generation of the second or of the third harmonic of the input signal or of the output signal as a function of the power of the input signal or of the fundamental component of the output signal.
     
    10. Radiofrequency device comprising:

    - a radiofrequency circuit (L) formed on a semiconductor substrate (1) coated with an electrically insulating layer (2, 2b),

    - a contact (4) electrically connected to the semiconductor substrate (1),

    - a means for applying a potential difference (VGB) between said contact and the radiofrequency circuit,

    characterized in that said application means is configured to apply said potential difference (VGB) chosen so as to move a trough around a given power (PDip) in a curve representing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in said circuit as a function of a power of the input or output signal towards a given operating power of said radiofrequency circuit.
     
    11. Device according to claim 10, wherein said means for applying the potential difference (VGB) comprises a voltage generator and a voltage control module configured to adjust the voltage of said generator depending on the operating power of the radiofrequency circuit.
     
    12. Device according to either of claims 10 and 11, wherein the semiconductor substrate has an electrical resistivity of greater than 500 Ω.cm.
     
    13. Device according to claim 12, wherein a polycrystalline silicon layer (3) is arranged between the semiconductor substrate (1) and the electrically insulating layer (2, 2b).
     
    14. Device according to claim 13, wherein an additional electrically insulating layer (2a) is arranged between the semiconductor substrate (1) and the polycrystalline silicon layer (3).
     
    15. Device according to one of claims 10 to 14, wherein the semiconductor substrate (1) is made of silicon.
     
    16. Device according to one of Claims 10 to 15, furthermore comprising a temperature sensor coupled to the means for applying the potential difference (VGB), said means being configured to adjust said potential difference depending on the temperature measured by said sensor.
     


    Ansprüche

    1. Verfahren zur Minimierung der Verzerrung von Oberschwingungen und/oder der Intermodulationsverzerrung eines Hochfrequenzsignals, das sich in einem Hochfrequenz-Schaltkreis (L) ausbreitet, der auf einem Halbleitersubstrat (1) ausgebildet ist, das mit einer elektrisch isolierenden Schicht (2, 2b) beschichtet ist, wobei eine Kurve, die die Verzerrung als Funktion einer Leistung des Eingangs- oder Ausgangssignals darstellt, um eine gegebene Leistung (PDip) herum ein Tal aufweist,
    wobei das Verfahren dadurch gekennzeichnet ist, dass es das Anlegen, zwischen dem Hochfrequenz-Schaltkreis (L) und dem Halbleitersubstrat (1), einer elektrischen Potenzialdifferenz (VGB) umfasst, die so gewählt wird, dass sie das Tal in Richtung einer gegebenen Betriebsleistung des Hochfrequenz-Schaltkreises bewegt.
     
    2. Verfahren nach Anspruch 1, wobei die elektrische Potentialdifferenz (VGB) so gewählt wird, dass die folgende Gleichung erfüllt wird: Vpk = |VGB-VFB|, wo Vpk die Spitzenspannung des Hochfrequenzsignals ist und VFB die Flachbandspannung ist.
     
    3. Verfahren nach einem der Ansprüche 1 und 2, wobei das Halbleitersubstrat (1) einen spezifischen elektrischen Widerstand von mehr als 500 Ohm.cm aufweist.
     
    4. Verfahren nach Anspruch 3, wobei eine polykristalline Siliziumschicht (3) zwischen dem Halbleitersubstrat (1) und der elektrisch isolierenden Schicht (2, 2b) angeordnet ist.
     
    5. Verfahren nach Anspruch 4, wobei eine zusätzliche, elektrisch isolierende Schicht (2a) zwischen dem Halbleitersubstrat (1) und der polykristallinen Siliziumschicht (3) angeordnet ist.
     
    6. Verfahren nach einem der Ansprüche 1 bis 5, wobei das Halbleitersubstrat (1) aus Silizium hergestellt ist.
     
    7. Verfahren nach einem der Ansprüche 1 bis 6, das das Einstellen der elektrischen Potenzialdifferenz (VGB), die zwischen dem Halbleitersubstrat (1) und dem Hochfrequenz-Schaltkreis angelegt wird, in Abhängigkeit von der Betriebsleistung des Hochfrequenz-Schaltkreises umfasst.
     
    8. Verfahren nach einem der Ansprüche 1 bis 7, das ferner das Messen der Temperatur des Hochfrequenz-Schaltkreises und das Einstellen der elektrischen Potenzialdifferenz (VGB), die zwischen dem Halbleitersubstrat (1) und dem Hochfrequenz-Schaltkreis angelegt wird, in Abhängigkeit von der gemessenen Temperatur umfasst.
     
    9. Verfahren nach einem des Anspruch 1 bis 8, wobei die Kurve, die die Verzerrung des Signals darstellt, eine Kurve des Grades der Erzeugung der zweiten oder der dritten Oberschwingung des Eingangssignals oder des Ausgangssignals als Funktion der Leistung des Eingangssignals oder der Grundkomponente des Ausgangssignals ist.
     
    10. Hochfrequenzvorrichtung umfassend:

    - einen Hochfrequenz-Schaltkreis (L), der auf einem Halbleitersubstrat (1) ausgebildet ist, welches mit einer elektrisch isolierenden Schicht (2, 2b) beschichtet ist,

    - einen Kontakt (4), der elektrisch mit dem Halbleitersubstrat (1) verbunden ist,

    - Mittel zum Anlegen einer Potenzialdifferenz (VGB) zwischen dem Kontakt und dem Hochfrequenz-Schaltkreis,

    dadurch gekennzeichnet, dass die Mittel zum Anlegen dafür konfiguriert sind, die gewählte Potenzialdifferenz (VGB) so anzulegen, dass sie ein Tal um eine gegebene Leistung (PDip) herum in einer Kurve, die die Verzerrung von Oberschwingungen und/oder die Intermodulationsverzerrung eines Hochfrequenzsignals, das sich in dem Schaltkreis ausbreitet, als Funktion einer Leistung des Eingangs- oder Ausgangssignals darstellt, in Richtung einer gegebenen Betriebsleistung des Hochfrequenz-Schaltkreises bewegt.
     
    11. Vorrichtung nach Anspruch 10, wobei die Mittel zum Anlegen der Potenzialdifferenz (VGB) einen Spannungsgenerator und ein Spannungssteuerungsmodul umfasst, das dafür konfiguriert ist, die Spannung des Generators in Abhängigkeit von der Betriebsleistung des Hochfrequenz-Schaltkreises einzustellen.
     
    12. Vorrichtung nach einem der Ansprüche 10 und 11, wobei das Halbleitersubstrat einen spezifischen elektrischen Widerstand von mehr als 500 Ohm.cm aufweist.
     
    13. Vorrichtung nach Anspruch 12, wobei eine polykristalline Siliziumschicht (3) zwischen dem Halbleitersubstrat (1) und der elektrisch isolierenden Schicht (2, 2b) angeordnet ist.
     
    14. Vorrichtung nach Anspruch 13, wobei eine zusätzliche, elektrisch isolierende Schicht (2a) zwischen dem Halbleitersubstrat (1) und der polykristallinen Siliziumschicht (3) angeordnet ist.
     
    15. Vorrichtung nach einem der Ansprüche 10 bis 14, wobei das Halbleitersubstrat (1) aus Silizium hergestellt ist.
     
    16. Vorrichtung nach einem der Ansprüche 10 bis 15, das ferner einen Temperaturmessfühler umfasst, der mit den Mitteln zum Anlegen der Potenzialdifferenz (VGB) gekoppelt ist, wobei diese Mittel dafür konfiguriert sind, die Potenzialdifferenz in Abhängigkeit von der durch den Messfühler gemessenen Temperatur einzustellen.
     


    Revendications

    1. Procédé pour minimiser une distorsion harmonique et/ou une distorsion d'intermodulation d'un signal radiofréquence se propageant dans un circuit radiofréquence (L) formé sur un substrat semi-conducteur (1) recouvert d'une couche électriquement isolante (2, 2b), dans lequel une courbe représentant ladite distorsion en fonction d'une puissance du signal d'entrée ou de sortie présente un creux autour d'une puissance déterminée (PDip),
    ledit procédé étant caractérisé en ce qu'il comprend l'application, entre le circuit radiofréquence (L) et le substrat semi-conducteur (1), d'une différence de potentiel électrique (VGB) choisie de sorte à déplacer ledit creux vers une puissance de fonctionnement déterminée du circuit radiofréquence.
     
    2. Procédé selon la revendication 1, dans lequel ladite différence de potentiel électrique (VGB) est choisie de sorte à respecter l'équation suivante : Vpk = |VGB-VFB|, où Vpk est la tension crête du signal radiofréquence et VFB est la tension de bande plate.
     
    3. Procédé selon l'une des revendications 1 et 2, dans lequel le substrat semi-conducteur (1) présente une résistivité électrique supérieure à 500 Ω.cm.
     
    4. Procédé selon la revendication 3, dans lequel une couche (3) de silicium polycristallin est agencée entre le substrat semi-conducteur (1) et la couche électriquement isolante (2, 2b).
     
    5. Procédé selon la revendication 4, dans lequel une couche électriquement isolante additionnelle (2a) est agencée entre le substrat semi-conducteur (1) et la couche (3) de silicium polycristallin.
     
    6. Procédé selon l'une des revendications 1 à 5, dans lequel le substrat semi-conducteur (1) est en silicium.
     
    7. Procédé selon l'une des revendications 1 à 6, comprenant l'ajustement de la différence de potentiel électrique (VGB) appliquée entre le substrat semi-conducteur (1) et le circuit radiofréquence en fonction de la puissance de fonctionnement du circuit radiofréquence.
     
    8. Procédé selon l'une des revendications 1 à 7, comprenant en outre une mesure de la température du circuit radiofréquence, et l'ajustement de la différence de potentiel électrique (VGB) appliquée entre le substrat semi-conducteur (1) et le circuit radiofréquence en fonction de la température mesurée.
     
    9. Procédé selon l'une des revendications 1 à 8, dans lequel la courbe représentant la distorsion du signal est une courbe du niveau de génération du deuxième ou du troisième harmonique du signal d'entrée ou du signal de sortie en fonction de la puissance du signal d'entrée ou de la composante fondamentale du signal de sortie.
     
    10. Dispositif radiofréquence comprenant :

    - un circuit radiofréquence (L) formé sur un substrat semi-conducteur (1) recouvert d'une couche électriquement isolante (2, 2b),

    - un contact (4) connecté électriquement au substrat semi-conducteur (1),

    - un moyen d'application d'une différence de potentiel (VGB) entre ledit contact et le circuit radiofréquence,

    caractérisé en ce que ledit moyen d'application est configuré pour appliquer ladite différence de potentiel (VGB) choisie de sorte à déplacer un creux autour d'une puissance déterminée (PDip) dans une courbe représentant une distorsion harmonique et/ou une distorsion d'intermodulation d'un signal radiofréquence se propageant dans ledit circuit en fonction d'une puissance du signal d'entrée ou de sortie vers une puissance de fonctionnement déterminée dudit circuit radiofréquence.
     
    11. Dispositif selon la revendication 10, dans lequel ledit moyen d'application de la différence de potentiel (VGB) comprend un générateur de tension et un module de contrôle de tension configuré pour ajuster la tension dudit générateur en fonction de la puissance de fonctionnement du circuit radiofréquence.
     
    12. Dispositif selon l'une des revendications 10 et 11, dans lequel le substrat semi-conducteur présente une résistivité électrique supérieure à 500 Ω.cm.
     
    13. Dispositif selon la revendication 12, dans lequel une couche (3) de silicium polycristallin est agencée entre le substrat semi-conducteur (1) et la couche électriquement isolante (2, 2b).
     
    14. Dispositif selon la revendication 13, dans lequel une couche électriquement isolante additionnelle (2a) est agencée entre le substrat semi-conducteur (1) et la couche (3) de silicium polycristallin.
     
    15. Dispositif selon l'une des revendications 10 à 14, dans lequel le substrat semi-conducteur (1) est en silicium.
     
    16. Dispositif selon l'une des revendications 10 à 15, comprenant en outre un capteur de température couplé au moyen d'application de la différence de potentiel (VGB), ledit moyen étant configuré pour ajuster ladite différence de potentiel en fonction de la température mesurée par ledit capteur.
     




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    Cited references

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    Patent documents cited in the description




    Non-patent literature cited in the description