SUPERCONDUCTING THROUGH-SILICON-VIAS AND THEIR METHOD OF FABRICATION

Description

TECHNICAL FIELD

[0001] The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to the structure and formation of superconducting metal through silicon vias (TSV).

BACKGROUND

[0002] Generally, integrated circuits (ICs) include semiconductor devices formed as a configuration of circuits on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered conductive networks, which can be formed using schemes, such as, for example, single or dual damascene wiring structures. Through-silicon-vias (TSV) are used as interconnects through bulk silicon wafers to reduce interconnect lengths and for 3D stacking. This concept has been around since the late 1950s. Metals used to fill the TSVs include tungsten and copper, which are deposited by chemical vapor deposition and electroplating, respectively. A TSV is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSVs are a high performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package, because the density of the vias is substantially higher, and because the length of the connections is shorter. Copper is electroplated by using a conductive seed layer (such as PVD copper) that is conformal inside the entire via and surface of the wafer. There are two approaches to electroplating copper with special copper plating solutions. Conformal plating deposits the copper at an equal rate over the whole surface, but has a high chance of voids forming in the via while bottom-up plating primarily deposits copper from the bottom of the via to form a void free fill. An alternate approach to bottom-up plating is to have the seed layer at the very bottom of the via only. A special copper plating solution is not necessary in this case and the copper only grows on the exposed seed layer. Though tungsten and copper have a low resistivity, neither are superconducting at a reasonable temperature (>1K) and a superconducting metal fill is desirable in technological application such as RSFQ circuitry. US Patent Publication number US 2014/0274725 A1 Abraham, D. et al ("Chip mode isolation and cross-talk reduction through buried metal layers and through-vias", 18 September 2014) discloses a method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate. US Patent Publication number US 2010/0240174A1 Yu, J. et al ("Via Using Zn or Zn Alloys and Its Making Method, 3D Chip Stack Packages Using Thereof, 23 September 2010) discloses a via, a method for formation of via using zinc and zinc alloys, and a process for fabrication of three-dimensional multiple chip stack packages by using the same. In lamination of three-dimensional chips, the chips with reduced defects are rapidly formed by the steps of: punching each of the chips to form a via hole used for a circuit wiring between the chips; depositing a seed layer on an inside of the via hole; forming a plated layer inside the via hole by using Zn and Zn alloys through an electroplating process; removing oxide film from surface of the plated layer; and heat treating the via hole at a temperature of more than melting point of the Zn and Zn alloys. Particularly, the chip having Zn via formed according to the present invention has an advantage of simultaneously overcoming problems in establishment of processing parameters caused by Cu via (e.g., plating mode, current density, influence of additives, pore formation, etc.), problems in successive processes caused by Sn (and other low melting point metals) via (e.g., soldering, chip stack, etc.) and difficulty in mechanical reliability of the process. Additionally, when stacking multiple chips with various functions in the three-dimensional chip stack package, the package can be simply fabricated by controlling contents of constitutional elements in Zn alloy via which has specific thermal properties (such as melting point, thermal expansion coefficient, etc.) suitable for processing temperature of each of the chips. US 2009/098731 A1 discloses a method of forming through-substrate vias in bonded substrates.

[0003] Therefore, there is a need in the art to address the aforementioned problem.

SUMMARY

[0004] According to the present invention there are provided a method and a semiconductor structure according to the independent claims.

[0005] A method of fabricating the semiconductor device according to the invention includes patterning a layer of a first superconducting metal on a base substrate to form a first pattern of the superconducting metal and patterning a layer of a second superconducting metal on a cap substrate to form a second pattern of the superconducting metal. The second pattern of the second superconducting metal and the cap substrate are etched to form vias, wherein a remaining portion of the second superconducting metal extends about a perimeter of the via on a top surface of the cap substrate. The cap substrate is inverted and bonded to the base substrate. A portion of the cap substrate is removed to expose and provide openings to the vias, wherein a bottom of the vias expose the first pattern of first superconducting metal. The vias are filled with a third superconducting metal to form a through-substrate-via. A method of fabricating a semiconductor device according to the invention includes patterning a layer of a first superconducting metal on a base substrate to form a first pattern of the superconducting metal. A layer of a second superconducting metal on a cap substrate is patterned to form a second pattern of the superconducting metal. The cap substrate is inverted and the first superconducting metal is bonded to the second superconducting metal. Vias are formed by etching the cap substrate to the bonded second superconducting metal, wherein a bottom of the vias exposes a surface of the second superconducting metal. The vias are filled with a third superconducting metal to form a through substrate via from the bottom up.

[0006] A semiconductor structure according to the invention is defined in claim 11

[0007] Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are recited in the dependent claims. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a top down view depicting a semiconductor device after a fabrication operation according to embodiments of the invention;

FIG. 2 is a sectional view depicting a semiconductor device after a fabrication operation according to embodiments of the invention;

FIG. 3 is a sectional view depicting a semiconductor device after a fabrication operation according to embodiments of the invention;

FIG. 4 is a sectional view depicting a semiconductor device after a fabrication operation according to embodiments of the invention;

FIG. 5 is a sectional view depicting a semiconductor device after a fabrication operation according to embodiments of the invention;

FIG. 6 is a sectional view depicting a semiconductor device after a fabrication operation according to an example outside the scope of the claims;

FIG. 7 is a sectional view depicting a semiconductor device after a fabrication operation according to an example outside the scope of the claims;

FIG. 8 is a sectional view depicting a semiconductor device after a fabrication operation according to an example outside the scope of the claims;

FIG. 9 is a sectional view depicting a semiconductor device after a fabrication operation according to an example outside the scope of the claims; and

FIG. 10 is a sectional view depicting a semiconductor device after a fabrication operation according to an example outside the scope of the claims.

DETAILED DESCRIPTION

[0009] TSVs are used as interconnects through bulk silicon wafers to reduce interconnect lengths and for three dimensional stacking. Metals previously used to fill the TSVs included tungsten and copper, which can be deposited by chemical vapor deposition and electroplating respectively. By way of example, copper can be electroplated using a conductive seed layer such as plasma vapor deposited (PVD) copper that is conformal to the via and the wafer surface.

[0010] There are generally two approaches to electroplating copper, both of which require special copper plating solutions. In one approach, conformal plating deposits copper at an equal rate over the entire whole surface but has an increased probability of void formation whereas, in another approach, a bottoms-up plating process deposits copper from the bottom of the via to form a void free fill. An alternative approach to bottoms up plating that does not require a special copper plating solution is to provide a seed layer at the bottom surface defining the via such that the copper selectively grows from the "bottom up" to fill the via.

[0011] Though tungsten and copper have low resistivity, neither metal is superconducting at a reasonable temperature, i.e., temperatures greater than 1°K. A superconducting metal can be desirable for some applications such as Rapid Single Flux Quantum (RSFQ) circuitry. RSFQ circuitry uses superconducting devices, namely Josephson junctions, to process digital signals. In RSFQ logic, information is stored in the form of magnetic flux quanta and transferred in the form of Single Flux Quantum (SFQ) voltage pulses. RSFQ is one family of superconducting or SFQ logic. Others include Reciprocal Quantum Logic (RQL), ERSFQ energy-efficient RSFQ version that does not use bias resistors, or the like. Josephson junctions are the active elements for RSFQ electronics, just as transistors are the active elements for semiconductor electronics. The present invention is generally directed to a bottoms-up electroplating process for depositing a superconducting metal in a TSV.

[0012] Conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

[0013] Spatially relative terms, e.g., "beneath," "below," "lower," "above," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] It is to be understood that the various layers and/or regions shown in the accompanying drawings are not drawn to scale, and that one or more layers and/or regions of a type commonly used in complementary metal-oxide semiconductor (CMOS), fin field-effect transistor (FinFET), metal-oxide-semiconductor field-effect transistor (MOSFET), and/or other semiconductor devices, may or may not be explicitly shown in a given drawing. This does not imply that the layers and/or regions not explicitly shown are omitted from the actual devices. In addition, certain elements could be left out of particular views for the sake of clarity and/or simplicity when explanations are not necessarily focused on the omitted elements. Moreover, the same or similar reference numbers used throughout the drawings are used to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings.

[0015] The semiconductor devices and methods for forming same in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention can include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.

[0016] The embodiments of the present invention can be used in connection with semiconductor devices that could require, for example, CMOSs, MOSFETs, and/or FinFETs. By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.

[0017] The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains" or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0018] As used herein, the articles "a" and "an" preceding an element or component are intended to be nonrestrictive regarding the number of instances (i.e. occurrences) of the element or component. Therefore, "a" or "an" should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular.

[0019] As used herein, the term "about" modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term "about" means within 10% of the reported numerical value. In another aspect, the term "about" means within 5% of the reported numerical value. Yet, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

[0020] It will also be understood that when an element, such as a layer, region, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present, and the element is in contact with another element.

[0021] Exemplary embodiments of the invention will now be discussed in further detail with regard to semiconductor devices and methods of manufacturing the same and, in particular, to a bottom-up electroplating process for depositing a superconducting metal in a through-substrate-via (TSV) to provide a superconducting void-free interconnect. The TSV superconducting structures are suitable for RFSQ circuitry, for example.

[0022] Turning now to FIGS. 1-5, there is shown a process in accordance with one or more embodiments of forming a bottom-up superconducting TSV. In FIG. 1, there is depicted a base substrate 12, e.g., a silicon wafer. In one or more embodiments, a thin layer of a superconducting metal 14 is blanket deposited at a thickness of about 10 nanometers (nm) to about 5 microns (µm) onto the base substrate 12. In one or more other embodiments, the superconducting metal is deposited at a thickness of about 10 nm to about 1000 nm, and in still other embodiments, the superconducting metal is deposited at a thickness of about 20 nm to about 500 nm. The superconducting metal can be aluminum, gallium, indium, lanthanum, molybdenum, niobium, rhenium, ruthenium, tin, tantalum, titanium, zinc, zirconium, alloys thereof, and the like. The superconducting metal generally in addition to being superconducting, functions in a manner similar to a seed layer typically used in copper electroplating processes as will be discussed in greater detail below.

[0023] The thin layer of superconducting metal 14 can be deposited onto the base substrate 12 without previous treatment by evaporation, sputtering or by electroplating. In some cases the substrate can be cleaned prior to deposition of superconducting metal 14, and in addition a relatively thin adhesion layer (e.g., a thickness of 2 nm to 20 nm) such as titanium or tantalum can be deposited prior to layer 14. The layer of superconducting metal 14 is then lithographically patterned, which can include forming a photoresist (e.g., organic, inorganic or hybrid) atop the layer of the superconducting metal 14. The photoresist can be formed utilizing a deposition process such as, for example, CVD, PECVD, spin-on coating or the like. Following formation of the photoresist, the photoresist is exposed to a desired pattern of radiation. Next, the exposed photoresist is developed utilizing a conventional resist development process. After the development step, a selective etching step can be performed to transfer the pattern from the patterned photoresist into at the layer of superconducting metal 14 stopping at the silicon layer. The etching step used in forming the patterned superconducting metal 14 can include a dry etching process (including, for example, reactive ion etching, ion beam etching, plasma etching or laser ablation), a wet chemical etching process or any combination thereof.

[0024] In FIG. 2, there is depicted a cap substrate 18. A layer of superconducting metal layer 16 is deposited onto a cap substrate 18. The superconducting metal 16 can be the same as the superconducting metal 14 formed on the base substrate 12. For example, the layers of superconducting metals 14, 16 can be formed of aluminum. The cap substrate 18 can be of the same material as the base substrate 12, e.g., a silicon wafer.

[0025] The superconducting metal 16 can be deposited at the same or different thickness as superconducting layer 14. Generally, superconducting metal 16 can be blanket deposited onto the cap substrate 18 at a thickness of about 10 nanometers (nm) to about 5 microns (µm). In one or more other embodiments, the superconducting metal is deposited at a thickness of about 10 nm to about 1000 nm, and in still other embodiments, the superconducting metal is deposited at a thickness of about 20 nm to about 500 nm. The superconducting metals 14, 16 can be dissimilar or similar depending on the desired application.

[0026] The layer of superconducting metal 16 is then lithographically patterned in the manner described above. Vias 20 are then formed in the cap substrate 18 by lithographically patterning and anisotropically etching the silicon substrate. As will be apparent, the vias 20 will be utilized to define the TSVs and extend partly through the cap substrate 18. For example, the vias can extend to a depth of about 10 microns (µm) to as much as about 350 µm depending on the initial thickness into the silicon substrate, which typically have a thickness generally depending on diameter of about 275 µm to about 775 µm. In other embodiments, the via depth into the cap substrate 18 is about 10 µm to about 250 µm, and in still other embodiments, the via depth into the cap substrate 18 is at about 20 µm to about 150 µm. By way of example, the silicon substrate can be subjected to wet or dry etching to form the vias.

[0027] The resulting pattern of the superconducting metal 16 and vias 20 in the cap substrate 18 are such that a portion of the superconducting material 16 surrounds a perimeter top surface about the via 20.

[0028] In FIG. 3, the cap substrate 18 including the patterned superconducting metal 16 and vias 20 thereon is then inverted and bonded to the base substrate 12 such as by thermocompression bonding, also referred to as diffusion bonding. The surrounding portions of the superconducting metal 16 in the cap substrate are mated to the corresponding patterned superconducting metal 14 on the base substrate 12. That is, the portion of the superconducting material 16 surrounding the perimeter top surface of the vias 20 contacts the corresponding patterned superconducting metal 14 on the base substrate 12. In this manner, the superconducting metals 14, 16 on each substrate 12, 18 can be brought together into atomic contact by applying force and heat simultaneously to bond the cap substrate 18 to the base substrate 12 as shown. The resulting structure includes the surrounding portion of superconducting metal 16 about the perimeter from the cap substrate 18 is bonded to a corresponding portion of the superconducting metal 14 in the base substrate 12 whereas the inverted vias 20 include a superconducting metal layer (from the base substrate 12) at the bottom 22 of each via 20.

[0029] As an example of thermocompression bonding, aluminum on one substrate can be bonded to aluminum on another substrate by subjecting the substrates to a bonding temperature from about 400 °C to about 450 °C with an applied force above 70 kN for 20 to 45 min, although higher or lower temperatures and forces can be used for different superconducting metals.

[0030] In FIG. 4, the cap substrate 18 is subjected to a wafer backgrinding process to remove a portion of the cap substrate so as to expose and open the vias 20. The backgrinding process generally includes application of a slurry of coarse particles to coarsely grind the wafer and remove a bulk of the wafer thickness. A finer grit is then used to polish the wafer. The coarse grinding can be used to remove about 90 percent of the substrate.

[0031] The superconducting metal surface 22 at the bottom of the vias 20 is cleaned to remove any oxide thereon. Cleaning can include applying an etchant configured to selectively remove the oxide and any residual slurry contaminants from the backgrinding process. Depending on the choice of superconducting metal utilized to form the superconducting layer 14 on the base substrate 12, the superconducting metal surface at the via bottom 22 can be prepped for filling by an optional electroless plating. For example, a superconducting metal such as zinc or tin can be electrolessly plated onto an aluminum layer, which can promote adhesion of the fill material during a subsequent electroplating process. Aluminum, by itself, is a very difficult substrate to directly plate thereon.

[0032] In FIG. 5, the vias 20 are filled with a superconducting metal or metal alloy to form the TSV 24 by subjecting the substrate to an electroplating process by making electrical contact to the backside of the base substrate 14 and immersing the substrate into an electrolyte bath. The superconducting metal or metal alloy grows from the bottom up until the TSV is fully filled with the superconducting metal and ready for further processing. As such, the previously deposited superconducting metals of layers 14, 16 function as a bottom electrode during the electroplating process

[0033] The electrolyte bath can be made up of electrolyte solvent and one or more salts including a source of metal or metals to be electroplated. Often salts can also be present to improve conductivity and efficiency of the process. The solvent can be aprotic or at least very weakly acidic. In addition, the solvent should be such as to dissolve reasonable amounts of metal salts (sources of the metal being plated) and other salts to increase electrolyte conductivity. In addition, the solvent should be stable not only to the substrate material being electroplated but under the condition of electroplating the metal.

[0034] A large variety of solvents can be used in the practice of the invention. Typically, the non-aqueous solvent is chosen from various stable organic liquids such as nitriles, carbonates, amides, ketones, alcohols, glycols, ethers, and the like. Typical solvents are acetonitrile, benzonitrile, diglyme (diethylene glycol dimethyl ether), triglyme (triethylene glycol dimethyl ether), tetraglyme (tetraethylene glycol dimethyl ether), ethylene glycol, dimethyl formamide, acetamide, acetone, methyl isobutyl ketone, tetrahydrofuran, dimethylsulfoxide, propylene and ethylene carbonates. In one or more embodiments, the solvent can be acetonitrile, propylene carbonate or methanol. Mixtures of the above solvents can be used as well as other substances that are stable, suitable for use in an electroplating process and not reactive to the material being electroplated. More acidic solvents can be used (even water) provided that the potential required to plate the metal protects the material being electroplated from reaction with water.

[0035] A large variety of superconducting metals and alloys can be plated using the inventive procedure. For example, the superconducting metals can be tin, lead, zinc, cadmium, indium, alloys thereof, and combinations of these metals. In one or more embodiments, metals such as indium, tin, lead and tin-lead alloys are utilized because of ease of plating, availability, high electrical and thermal conductivity. Throughout this application the word metal should be understood to include various superconducting alloys (e.g., tin-lead alloy) and mixtures of metals as well as pure elemental metal.

[0036] The metals are introduced into the electroplating bath usually in the form of a salt, preferably a salt soluble in the electrolyte solvent and with an anion which is stable under conditions of the electroplating process. Typical anions are nitrate, perchlorate, halide (especially chloride, bromide and iodide), tetrafluoroborate, hexafluoroarsenate. Typically, perchlorates and nitrates are used because of availability and solubility in nonaqueous solvents.

[0037] Generally, concentrations vary from about 0.001 Molar to saturation. Too low a concentration requires too much time to electroplate and too much replenishment during processing. Typically, concentrations are adjusted to maximize conductivity when combined with certain ionic (conducting) salts.

[0038] The bath is typically made up of non-aqueous solvent described above, an electrochemically stable metal salt of the metal being plated (e.g., nitrate, perchlorate) and optionally a stable salt to increase ionic conductivity. A wide concentration range can be used including from trace amounts (0.001 Molar) to saturation. In one or more embodiments, concentrations are usually close to saturation, for example from about 1/10 the concentration of a saturated solution to the concentration of a saturated solution. By way of example, concentrations from 0.1 of saturated solutions to the concentration of the saturated solution can be used.

[0039] In addition to non-aqueous solvent described above and metal salt described above, the bath can contain conducting salts to increase the conductivity of the bath. These conducting salts are typically alkali-metal salts with stable anions with good solubility in the non-aqueous solvents. Typical anions are the same as for the metal salts given above (nitrate, perchlorate, halides, tetrafluoroborate (e.g. sodium tetrafluoroborate) and hexafluoroaresenate (e.g., lithium hexafluroarsenate). Also useful are the tetra alkylammonium salts such as tetrabutylammonium halides and tetraethyl ammonium halides. Concentrations of the conducting salts can vary from 0.001 molar to saturation and are usually determined so as to maximize conductivity of the bath. Generally, concentrations near saturation (within 0.1 of saturation to saturation) are preferred.

[0040] The electroplating process is carried out in a conventional manner with a conventional anode and the material to be plated made the cathode of an electroplating apparatus.

[0041] In one or more other examples, the process for forming the superconducting TSVs is shown in FIGS. 6-10. In FIG. 6, a base substrate 112 is provided, e.g., a silicon wafer. A thin layer of a superconducting metal 114 is blanket deposited at a thickness of about 10 nanometers (nm) to about 5 microns (µm). In one or more other examples, the superconducting metal is deposited at a thickness of about 10 nm to about 1000 nm, and in still other embodiments, the superconducting metal is deposited at a thickness of about 20 nm to about 500 nm. The superconducting metal can be a metal as previously described. The layer of superconducting metal 114 is then lithographically patterned to form a patterned superconducting metal as shown.

[0042] In FIG. 7, a cap substrate 118 is provided and thin layer of a superconducting metal 120 is blanket deposited at a thickness of about 10 nanometers (nm) to about 5 microns (µm). In one or more other embodiments, the superconducting metal is deposited at a thickness of about 10 nm to about 1000 nm, and in still other embodiments, the superconducting metal is deposited at a thickness of about 20 nm to about 500 nm. The superconducting metal can be a metal as previously described. The layer of superconducting metal 120 is then lithographically patterned to form a patterned superconducting metal similar to that provided in FIG. 6.

[0043] In FIG. 8, the cap substrate 118 is inverted and the patterned superconductor layer 120 is aligned with the corresponding patterned superconducting metal 114 on the base substrate 112 and subjected to thermocompression bonding to bond the cap substrate 118 to the base substrate 112.

[0044] In FIG. 9, the cap substrate 118 is subjected to backgrinding process as described above to remove a portion of the cap substrate. The remaining thickness of the cap substrate 118 will be used to define the length of the TSV. The cap substrate 118 is then lithographically patterned and etched to form vias 122 therein, which are configured to land on the thermocompression bonded and patterned superconducting metals 114/120. The topmost exposed superconducting metal 120 is then cleaned and prepped if needed by electrolessly prepped as previously described using a superconductor such as zinc or tin to promote adhesion during the fill process

[0045] In FIG. 10, electrical contact is made to the backside of the base substrate 112 and the substrate is immersed in an electroplating bath to fill the so-formed vias, thereby forming the TSVs 124 filled with a superconducting metal or metal alloys. The superconducting metal or metal alloys is formed from the bottom of the via up.

[0046] As previously noted herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a semiconductor device according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.

[0047] In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.

[0048] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the appended claims. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

patterning a layer of a first superconducting metal (14) on a base substrate (12) to form a first pattern of the superconducting metal;

patterning a layer of a second superconducting metal (16) on a cap substrate (18) to form a second pattern of the superconducting metal;

etching the second pattern of the second superconducting metal and the cap substrate to form vias (20), wherein a remaining portion of the second superconducting metal extends about a perimeter of the via on a top surface of the cap substrate;

inverting the cap substrate and bonding the cap substrate to the base substrate;

removing a portion of the cap substrate to expose and provide openings to the vias,

wherein a bottom of the vias expose the first pattern of first superconducting metal; and filling the vias with a third superconducting metal (24) to form a throughsub stratevia.

2. The method of claim 1, wherein bonding the cap substrate (18) to the base substrate (12) comprises aligning and thermocompressively contacting the portion of the second superconducting metal (16) on the cap substrate to the first superconducting metal (14) on the base substrate.

3. The method of either of the preceding claims, wherein filling the vias (20) with the third superconducting metal (24) comprises electroplating.

4. The method of any of the preceding claims, wherein filling the vias (20) with the third superconducting metal (24) comprises cleaning the exposed first pattern of first superconducting metal (14) at the bottom (22) of the vias to remove oxides and contaminants thereon followed by electroplating.

5. The method of either of claims 1 or 2, wherein filling the vias (20) with the third superconducting metal (24) comprises cleaning the exposed first pattern of the first superconducting metal (14) at the bottom of the via to remove oxides and contaminants thereon; electrolessly depositing a fourth superconducting metal onto exposed first pattern of the first superconducting metal at the bottom of the via; and electroplating the third superconducting metal therein to fill the vias from the bottom up.

6. The method of any of the preceding claims, wherein the base substrate (12) and the cap substrate (18) comprise silicon wafers.

7. The method of any of the preceding claims, wherein removing the portion of the cap substrate provides the vias with a depth of about 10 µm to about 250 µm.

8. The method of any of the preceding claims, wherein removing the portion of the cap substrate (18) to expose and provide the openings to the vias (20) comprises a backgrinding process.

9. The method of any of the preceding claims, wherein the first (14) and second superconducting metals (16) are the same.

10. The method of any of the preceding claims, wherein the third superconducting metal (24) is different from the first and second superconducting metals.

11. A semiconductor structure comprising:

a bonded superconducting metal layer sandwiched between a first silicon substrate (12) and a second silicon substrate (18), wherein the second substrate comprises a plurality of through-silicon-vias (20) to the bonded superconducting metal layer; and

a superconducting metal (24) filling the through-silicon-vias, and characterized by: wherein the superconducting metal is different from the bonded superconducting metal layer (14, 16),

wherein the bonded superconducting metal layer sandwiched between the first silicon substrate and the second silicon substrate comprises a first superconducting metal layer (14) and a second superconducting metal layer (16), wherein the first and second superconducting metals are different, and wherein the superconducting metal layer surrounds each of the through-substrate vias, and wherein the through-substrate vias form a plurality of recesses in the second superconducting layer and a bottom surface of the through-substrate-vias abut the first superconducting metal layer.

Ansprüche

1. Verfahren zum Herstellen einer Halbleiter-Vorrichtung, wobei das Verfahren umfasst:

Strukturieren einer Schicht eines ersten supraleitenden Metalls (14) auf einem Basissubstrat (12), um eine erste Struktur des supraleitenden Metalls zu bilden;

Strukturieren einer Schicht eines zweiten supraleitenden Metalls (16) auf einem Kappensubstrat (18), um eine zweite Struktur des supraleitenden Metalls zu bilden;

Ätzen der zweiten Struktur des zweiten supraleitenden Metalls und des Kappensubstrats, um Durchkontaktierungen (20) zu bilden, wobei sich ein verbleibender Abschnitt des zweiten supraleitenden Metalls um einen Umfang der Durchkontaktierung auf einer oberen Oberfläche des Kappensubstrats erstreckt;

Invertieren des Kappensubstrats und Bonden des Kappensubstrats mit dem Basissubstrat;

Entfernen eines Abschnitts des Kappensubstrats, um Öffnungen für die Durchkontaktierungen freizulegen und bereitzustellen,
wobei ein Boden der Durchkontaktierungen die erste Struktur des ersten supraleitenden Metalls freilegt; und

Füllen der Durchkontaktierungen mit einem dritten supraleitenden Metall (24), um eine substratdurchquerende Durchkontaktierung zu bilden.

2. Verfahren nach Anspruch 1, wobei das Bonden des Kappensubstrats (18) mit dem Basissubstrat (12) das Ausrichten und thermokompressive Kontaktieren des Abschnitts des zweiten supraleitenden Metalls (16) auf dem Kappensubstrat mit dem ersten supraleitenden Metall (14) auf dem Basissubstrat umfasst.

3. Verfahren nach einem der vorstehenden Ansprüche, wobei das Füllen der Durchkontaktierungen (20) mit dem dritten supraleitenden Metall (24) ein galvanisches Beschichten umfasst.

4. Verfahren nach einem der vorstehenden Ansprüche, wobei das Füllen der Durchkontaktierungen (20) mit dem dritten supraleitenden Metall (24) ein Reinigen der freiliegenden ersten Struktur des ersten supraleitenden Metalls (14) am Boden (22) der Durchkontaktierungen umfasst, um darauf befindliche Oxide und Verunreinigungen zu entfernen, gefolgt von galvanischem Beschichten.

5. Verfahren nach einem der Ansprüche 1 oder 2, wobei das Füllen der Durchkontaktierungen (20) mit dem dritten supraleitenden Metall (24) ein Reinigen der freiliegenden ersten Struktur des ersten supraleitenden Metalls (14) am Boden der Durchkontaktierung zum Entfernen von Oxiden und Verunreinigungen darauf; stromloses Abscheiden eines vierten supraleitenden Metalls auf der freiliegenden ersten Struktur des ersten supraleitenden Metalls am Boden der Durchkontaktierung; und galvanisches Beschichten des dritten supraleitenden Metalls darin zum Füllen der Durchkontaktierungen von unten nach oben umfasst.

6. Verfahren nach einem der vorstehenden Ansprüche, wobei das Basissubstrat (12) und das Kappensubstrat (18) Siliziumwafer umfassen.

7. Verfahren nach einem der vorstehenden Ansprüche, wobei das Entfernen des Abschnitts des Kappensubstrats die Durchkontaktierungen mit einer Tiefe von etwa 10 µm bis etwa 250 µm bereitstellt.

8. Verfahren nach einem der vorstehenden Ansprüche, wobei das Entfernen des Abschnitts des Kappensubstrats (18) zum Freilegen und Bereitstellen der Öffnungen für die Durchkontaktierungen (20) einen Rückschleifprozess umfasst.

9. Verfahren nach einem der vorstehenden Ansprüche, wobei das erste (14) und das zweite supraleitende Metall (16) das gleiche sind.

10. Verfahren nach einem der vorstehenden Ansprüche, wobei das dritte supraleitende Metall (24) von dem ersten und zweiten supraleitenden Metall verschieden ist.

11. Halbleiterstruktur, umfassend:

eine gebondete supraleitende Metallschicht, die zwischen einem ersten Siliziumsubstrat (12) und einem zweiten Siliziumsubstrat (18) eingefügt ist, wobei das zweite Substrat eine Vielzahl von siliziumdurchquerenden Durchkontaktierungen (20) zu der gebondeten supraleitenden Metallschicht umfasst; und

ein supraleitendes Metall (24), das die siliziumdurchquerenden Durchkontaktierungen füllt, und gekennzeichnet durch:

wobei das supraleitende Metall von der gebondeten supraleitenden Metallschicht (14, 16) verschieden ist,

wobei die zwischen dem ersten Siliziumsubstrat und dem zweiten Siliziumsubstrat eingefügte gebondete supraleitende Metallschicht eine erste supraleitende Metallschicht (14) und eine zweite supraleitende Metallschicht (16) umfasst, wobei das erste und das zweite supraleitende Metall verschieden sind, und wobei die supraleitende Metallschicht jede der substratdurchquerenden Durchkontaktierungen umgibt, und wobei die substratdurchquerenden Durchkontaktierungen eine Vielzahl von Vertiefungen in der zweiten supraleitenden Schicht bilden und eine Bodenfläche der substratdurchquerenden Durchkontaktierungen an die erste supraleitende Metallschicht anstößt.

Revendications

1. Procédé de fabrication d'un dispositif semi-conducteur, le procédé comprenant :

le modelage d'une couche d'un premier métal supraconducteur (14) sur un substrat de base (12) pour former un premier motif du métal supraconducteur ;

le modelage d'une couche d'un deuxième métal supraconducteur (16) sur un substrat de coiffe (18) pour former un second motif du métal supraconducteur ;

la gravure du second motif du deuxième métal supraconducteur et du substrat de coiffe pour former des trous d'interconnexion (20), dans lequel une partie restante du deuxième métal supraconducteur s'étend autour d'un périmètre du trou d'interconnexion sur une surface supérieure du substrat de coiffe ;

le retournement du substrat de coiffe et la liaison du substrat de coiffe au substrat de base ;

le retrait d'une partie du substrat de coiffe pour exposer et fournir des ouvertures aux trous d'interconnexion,

dans lequel un fond des trous d'interconnexion expose le premier motif de premier métal supraconducteur ; et
le remplissage des trous d'interconnexion avec un troisième métal supraconducteur (24) pour former un trou d'interconnexion traversant le substrat.

2. Procédé selon la revendication 1, dans lequel la liaison du substrat de coiffe (18) au substrat de base (12) comprend l'alignement et la mise en contact par thermocompression de la partie du deuxième métal supraconducteur (16) se trouvant sur le substrat de coiffe sur le premier métal supraconducteur (14) se trouvant sur le substrat de base.

3. Procédé selon l'une ou l'autre des revendications précédentes, dans lequel le remplissage des trous d'interconnexion (20) avec le troisième métal supraconducteur (24) comprend une électrodéposition.

4. Procédé selon l'une quelconque des revendications précédentes, dans lequel le remplissage des trous d'interconnexion (20) avec le troisième métal supraconducteur (24) comprend le nettoyage du premier motif exposé du premier métal supraconducteur (14) au fond (22) des trous d'interconnexion pour éliminer les oxydes et les contaminants se trouvant sur celui-ci, suivi d'une électrodéposition.

5. Procédé selon l'une ou l'autre de la revendication 1 ou la revendication 2, dans lequel le remplissage des trous d'interconnexion (20) avec le troisième métal supraconducteur (24) comprend le nettoyage du premier motif exposé du premier métal supraconducteur (14) au fond du trou d'interconnexion pour éliminer les oxydes et les contaminants se trouvant sur celui-ci ; la déposition autocatalytique d'un quatrième métal supraconducteur sur le premier motif exposé du premier métal supraconducteur au fond du trou d'interconnexion ; et l'électrodéposition du troisième métal supraconducteur à l'intérieur pour remplir les trous d'interconnexion du bas vers le haut.

6. Procédé selon l'une quelconque des revendications précédentes, dans lequel le substrat de base (12) et le substrat de coiffe (18) comprennent des tranches de silicium.

7. Procédé selon l'une quelconque des revendications précédentes, dans lequel le retrait de la partie du substrat de coiffe donne aux trous d'interconnexion une profondeur d'environ 10 µm à environ 250 µm.

8. Procédé selon l'une quelconque des revendications précédentes, dans lequel le retrait de la partie du substrat de coiffe (18) pour exposer et fournir les ouvertures aux trous d'interconnexion (20) comprend une rectification de face arrière.

9. Procédé selon l'une quelconque des revendications précédentes, dans lequel le premier métal supraconducteur (14) et le deuxième métal supraconducteur (16) sont identiques.

10. Procédé selon l'une quelconque des revendications précédentes, dans lequel le troisième métal supraconducteur (24) est différent des premier et deuxième métaux supraconducteurs.

11. Structure semi-conductrice comprenant :

une couche de métal supraconducteur liée prise en sandwich entre un premier substrat de silicium (12) et un second substrat de silicium (18), dans laquelle le second substrat comprend une pluralité de trous d'interconnexion (20) traversant le silicium vers la couche de métal supraconducteur liée ; et

un métal supraconducteur (24) remplissant les trous d'interconnexion traversant le silicium, et caractérisée par : dans laquelle le métal supraconducteur est différent de la couche de métal supraconducteur (14, 16) liée,

dans laquelle la couche de métal supraconducteur liée prise en sandwich entre le premier substrat de silicium et le second substrat de silicium comprend une première couche de métal supraconducteur (14) et une seconde couche de métal supraconducteur (16), dans laquelle les premier et deuxième métaux supraconducteurs sont différents, et dans laquelle la couche de métal supraconducteur entoure chacun des trous d'interconnexion traversant le substrat, et dans laquelle les trous d'interconnexion traversant le substrat forment une pluralité d'évidements dans la seconde couche supraconductrice et une surface inférieure des trous d'interconnexion traversant le substrat vient en butée contre la première couche de métal supraconducteur.

Drawing