(19)
(11)EP 3 640 994 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
16.09.2020 Bulletin 2020/38

(43)Date of publication A2:
22.04.2020 Bulletin 2020/17

(21)Application number: 19183098.3

(22)Date of filing:  28.06.2019
(51)Int. Cl.: 
H01L 29/45  (2006.01)
H01L 29/786  (2006.01)
H01L 29/66  (2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 26.09.2018 US 201816142045

(71)Applicant: INTEL Corporation
Santa Clara, CA 95054 (US)

(72)Inventors:
  • Weber, Cory
    Hillsboro OR 97124 (US)
  • Ma, Sean
    Portland OR 97221 (US)
  • Le, Van
    Beaverton OR 97007 (US)
  • Sharma, Abhishek
    Hillsboro OR 97124 (US)

(74)Representative: HGF 
1 City Walk
Leeds LS11 9DX
Leeds LS11 9DX (GB)

  


(54)CHANNEL STRUCTURES FOR THIN-FILM TRANSISTORS


(57) Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.