(19)
(11)EP 3 648 349 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.10.2021 Bulletin 2021/40

(21)Application number: 19203837.0

(22)Date of filing:  17.10.2019
(51)International Patent Classification (IPC): 
H03K 7/08(2006.01)
H02M 1/00(2006.01)
H02M 3/157(2006.01)
(52)Cooperative Patent Classification (CPC):
H02M 1/0003; H02M 3/157; H03K 7/08

(54)

A METHOD OF OPERATING A CONTROLLER, CORRESPONDING CIRCUIT AND DEVICE

VERFAHREN ZUM BETRIEB EINES STEUERGERÄTS, ZUGEHÖRIGE SCHALTUNG UND VORRICHTUNG

PROCÉDÉ DE FONCTIONNEMENT D'UN ORGANE DE COMMANDE, CIRCUIT ET DISPOSITIF CORRESPONDANTS


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 31.10.2018 IT 201800009991

(43)Date of publication of application:
06.05.2020 Bulletin 2020/19

(73)Proprietor: STMicroelectronics S.r.l.
20864 Agrate Brianza (MB) (IT)

(72)Inventors:
  • POLETTO, Vanni
    I-20151 Milano (IT)
  • ALAGNA, Diego
    I-20133 Milano (IT)
  • ERRICO, Nicola
    I-20017 Rho (Milano) (IT)
  • CIGNOLI, Marco
    I-27100 Pavia (IT)
  • DE AGOSTINI, Gian Battista
    I-24050 Bariano (Bergamo) (IT)

(74)Representative: Bosotti, Luciano 
Buzzi, Notaro & Antonielli d'Oulx S.p.A. Corso Vittorio Emanuele ll, 6
10123 Torino
10123 Torino (IT)


(56)References cited: : 
DE-A1-102007 057 502
US-A1- 2011 204 988
US-A1- 2009 015 231
US-B2- 8 589 016
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Technical field



    [0001] The description relates to controller circuits such as, for instance, PID (Proportional-Integral-Derivative) controllers.

    [0002] One or more embodiments may be applied to controlling generators of signals to which Pulse-Width-Modulation, briefly PWM, is applied.

    Technological background



    [0003] Generators of PWM-modulated signals (PWM signals) are widely used in various areas or technology, for instance for controlling currents flowing through electrical loads. Automotive applications such as braking and transmission are exemplary of such possible areas of application of PWM signal generators.

    [0004] PWM signal generators may be used, for instance, for driving inductive loads such as solenoids with a resulting ripple in the current driven through the load. A closed-loop control circuit may be used to facilitate achieving an average load current corresponding to a desired set point. A Proportional-Integral-Derivative (briefly - PID) controller may be exemplary of such a control circuit.

    [0005] Conventional arrangements may provide for the current ripple to be averaged out after measurement and before subtraction from the set point. Such averaging may result in a delay in the closed-loop control which may adversely affect performance during a transient response, for instance.

    [0006] More specifically, the invention relates to a method according to the preamble of claim 1, which is known, for instance, from US 8 589 016 B2. A substantially similar disclosure is provided in DE 10 2007 057502 A1.

    Object and summary



    [0007] Despite the extensive activity in that area, improved solutions overcoming such a limitation would be desirable.

    [0008] An object of one or more embodiments is to contribute in providing such an improved solution.

    [0009] According to the invention, that object is achieved by means of a method having the features set forth in claim 1. A further aspect of the invention is defined as set forth in claim 7.

    [0010] One or more embodiments may relate to a corresponding device as per claim 8. A device including an inductive load such as a solenoid driven by means of a PWM signal generator may be exemplary of such a device.

    [0011] The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

    [0012] One or more embodiments may provide a closed-loop controller circuit (e.g. a PID controller circuit) which may facilitate driving an electrical load an average target set point by controlling the duty cycle (that is. the ratio of the "on" time to the sum of the "on" time and the "off" times) of a PWM signal.

    [0013] One or more embodiments may be based on the recognition that permitting propagation of the PWM ripple through the control-loop, by refraining from averaging it out, may facilitate improved, faster transient response, with a higher stability and accuracy without ripple propagation being appreciably detrimental to control loop-operation.

    [0014] One or more embodiments may facilitate achieving satisfactory operation via a judicious selection of the frequency at which the controller parameters are updated in relationship to the frequency of the PWM signal.

    Brief description of the Figures



    [0015] One or more embodiments will now be described, by way of example only, with reference to the annexed figures wherein:
    • Figure 1 is a block diagram of a feedback-loop control arrangement of a PWM signal generator,
    • Figure 2 is a circuit diagram of an exemplary implementation, with possible variations, of the arrangement of the Figure 1,
    • Figure 3 is a block diagram of a feedback-loop control arrangement of a PWM signal generator as per the present disclosure,
    • Figure 4 is a circuit diagram of an exemplary implementation, with possible variations, of a possible implementation of the arrangement of the Figure 3,
    • Figures 5A, 5B and 6 are time diagrams exemplary of possible operation of embodiments.

    Detailed description of exemplary embodiments



    [0016] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

    [0017] Reference to "an embodiment" or "one embodiment" in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

    [0018] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

    [0019] In Figures 1 and 2, reference numeral 10 indicates as a whole a circuit arrangement which implements a closed-loop control strategy in a PWM driver arrangement of a load L, such as an inductive load.

    [0020] A solenoid (for use, e.g. in a braking or transmission system in a vehicle, not visible in the figures as a whole) may be exemplary of such a load L, which may be represented as the series connection of an inductor Ls and a resistor Rs.

    [0021] It will be otherwise appreciated that reference to a load L comprising a solenoid and/or to a possible application in the automotive field is merely for exemplary purposes and is not to be construed, even indirectly, in a limiting sense of the embodiments.

    [0022] In an arrangement as exemplified herein, the load L is driven via a power driver circuit D receiving a supply voltage VS.

    [0023] As exemplified in Figure 1, the load L may be coupled between the supply voltage VS and the output of the power driver circuit D and be traversed by a current IS.

    [0024] As exemplified in Figure 2, the load L may be coupled between the output of the power driver circuit D at a voltage VLOAD and ground GND and be traversed by a current ILOAD.

    [0025] In arrangements as exemplified in Figures 1 and 2, the driver stage D is in turn driven via a Pulse-Width Modulated signal PWM as generated by a PWM signal generator 12 associated with a controller circuit 14.

    [0026] As exemplified in Figure 2, the controller 14 may comprise a Proportional-Integral-Derivative (PID) controller in turn comprising, in a manner known to those of skill in the art:
    • a proportional branch 141 with an associated (proportional) gain KP,
    • an integral branch 142, with an associated (integral) gain KI and including an integrator circuit block 142A, and
    • a derivative branch 143, with an associated (derivative) gain KD and including a derivative circuit block 143A.


    [0027] The outputs from the branches 141, 142 and 143 are summed at a summation node 144 and applied as a control signal PID to one input of the PWM signal generator 12.

    [0028] Again in a manner known to those of skill in the art the PWM signal generator 12 may essentially comprise a comparator circuit whose other input is supplied with a ramp signal Ramp by a ramp generator 16 which generates a triangular (saw-tooth) signal with a period TPWM. The period of the ramp signal defines the period of the PWM signal generated by the generator 12 with a frequency fPWM (fPWM = 1/TPWM).

    [0029] Reference 18 indicates a summation node which receives at a first input (with a first sign, for instance positive) a set point signal SP indicative of a desired (average) value for the current through the load L.

    [0030] Reference 20 denotes a sensing arrangement which may include a current sense amplifier (CSA) 20a coupled to the output from the driver D. The sensing arrangement 20 may thus be sensitive to the value of the current through the load L, that is, IS (Figure 1) or ILOAD (Figure 2) .

    [0031] As exemplified in Figure 1, the sensing arrangement 20 may include a current sense amplifier 20a which senses - in any manner known to those of skill in the art - the current through the load L (for instance IS, in the case of Figure 1) and generates therefrom a scaled-down version IX of IS (for instance IX = IS/2560) which is supplied to an analog-to-digital converter (ADC) 20b.

    [0032] An essentially similar arrangement can be adopted in the solution exemplified in Figure 2 to generate IX as a scaled-down version of ILOAD.

    [0033] In arrangements as exemplified in Figures 1 and 2, the sensing current IX (however generated), possibly converted to a digital format at 20b, can be supplied to an averaging circuit 22 to generate a corresponding average signal.

    [0034] For instance, as exemplified in Figure 2, the averaging circuit can comprise a (digital) integrator 22a operated at a frequency fCK and providing an average (integrated) value of N subsequent samples of the signal from the analog-to-digital converter 20b, such a value possibly down-sampled at a frequency fPWM corresponding to the frequency of the PWM signal from the generator 12 at a down-sampling circuit block 22b.

    [0035] As exemplified in Figures 1 and 2, the average signal thus obtained is supplied to the summation node 18 where the feedback signal is combined (with an opposed sign, e.g. negative, and thus subtracted) from the set point signal SP with the combined (difference) from the node 18 input to the (e.g. PID) controller 14.

    [0036] The signal PID from the controller 14 is applied to the (first) input of the comparator 12 to vary the duty cycle of the PWM signal from the PWM generator 12 so that the value of the duty cycle is controlled in a closed loop arrangement using the set point signal SP as a target so that the (average) value of the load current (IS or ILOAD) can be set to a desired value as expressed by the signal SP (from a respective source such as a system microcontroller, not visible in the figures).

    [0037] Figures 1 and 2 are thus exemplary of a closed-loop control arrangements 10 comprising:
    • an analogue portion 10A (right side of the figures) which facilitates generating a signal (IX, for instance) indicative of the current IS, ILOAD through the load L,
    • a digital portion (left side of the figures) where such a signal indicative of the current in the load, converted to digital in 20b, is supplied to the averaging circuit 22 and then forwarded as a feedback signal towards the summation node 18 and the (e.g. PID) controller 14 with the associated PWM signal generator.


    [0038] The feedback loop thus provided facilitates closed-loop control of the load current IS, ILOAD with a target given by the set point value SP.

    [0039] It will be otherwise appreciated that arrangements as exemplified in Figures 1 and 2 are substantially conventional in the art, which makes it unnecessary to provide a more detailed description herein.

    [0040] In arrangements as exemplified in Figures 1 and 2 both the averaging stage 22 and the integral and derivative branches of the PID controller 14 (namely 142 and 143) are intended to be clocked (essentially, updated) at the same frequency of the PWM signal, fPWM= 1/TPWM.

    [0041] In arrangements as exemplified in Figures 1 and 2 the internal signals and the output signal PID from the controller 14 are updated (only) once at each cycle of the PWM signal of duration TPWM.

    [0042] Stated otherwise, in arrangements as exemplified in Figures 1 and 2, the internal, input and output signals of the controller 14 are practically constant within each interval corresponding to the period TPWM of the PWM signal.

    [0043] It is noted that computation of the average value in the circuit block 22 (in the integrator 22a of Figure 2, for instance) involves a delay or latency in the feedback control loop equal to one cycle TPWM of the PWM signal.

    [0044] It is observed that such a delay or latency may penalize the response speed of the control-loop.

    [0045] Correspondingly low values for the coefficients KP, KI and KD are thus adopted in the controller 14 in order to facilitate frequency stability. For instance, it is observed that selecting for the coefficients KP, KI, KD values which facilitate keeping overshoot (undershoot) under 10% with respect to a typical specification value may result in a delay of 15 mS in the response to a (positive or negative) step in the set point SP before the controlled entity (that is the average value of the current through the load) returns within a range of e.g. 1% of the desired value.

    [0046] Similarly one may observe that in an arrangement as exemplified in Figures 1 and 2 a positive/negative step from 10V to 15V (or from 15V to 10V) in the supply voltage VS may result in a transient current of +35% (-23%) over a time interval of 6mS (10mS).

    [0047] In one or more embodiments, those issues may be addressed by resorting to an arrangement as exemplified in Figures 3 and 4.

    [0048] In Figures 3 and 4 parts or elements like parts or elements already discussed in connection with Figures 1 and 2 are indicated by like references, so that a corresponding detailed description will not be repeated here for brevity.

    [0049] This applies, for instance (but not exclusively) to operation of the PWM signal generator 12 and control of the duty cycle of the PWM signal from the signal generator as a function of the signal PID from the controller 14.

    [0050] Also,
    • as exemplified in Figure 3, the load L may be coupled between the supply voltage VS and the output of the power driver circuit D and be traversed by a current IS;
    • as exemplified in Figure 4, the load L may be coupled between the output of the power driver circuit D at a voltage VLOAD and ground GND and be traversed by a current ILOAD.


    [0051] In one or more embodiments as exemplified in Figures 3 and 4 the averaging circuit 22 is "removed" from the control-loop so that the output signal from the sensing arrangement 20 (for instance the digital signal from the analog-to-digital converter 20b) is supplied to the (negative sign) input of the summation node 18 without being subjected to averaging.

    [0052] For the sake of completeness, Figure 4 exemplifies certain embodiments where, while "removed" from the feedback loop, the averaging circuit 22 (e.g. 22a, 22b) is retained arranged (outside) the control-loop to provide an averaged version of the signal from the sensing arrangement 20 (20a, 20b) as possibly desirable for other purposes (which per se may not be related to embodiments).

    [0053] Still in connection with the representation of Figures 3 and 4, it will be appreciated that the load L (with the driver stage D associated therewith) may represent a distinct element from embodiments.

    [0054] In brief, in an arrangement as exemplified in Figures 3 and 4, the internal signals as well as the output signal PID from the controller 14 may be updated "continuously", that is within each cycle of the PWM signal with a frequency fCK (1MHz, for instance) which may be substantially higher than the frequency fPWM of the PWM signal (1 KHz, for instance).

    [0055] The values indicated (which, of course, are in no way mandatory) are exemplary of a possible selection of a frequency fCK which is significantly higher than the frequency fPWM. For instance, as exemplified herein, the frequency fCK can be selected at a value which is at least one order and optionally (about) three orders of magnitude higher than the frequency fPWM (that is fCK/fPWM = 103).

    [0056] This may be regarded as a sort of oversampling applied to the internal signals, the input signal and the output signal of the PID control arrangement so that these signals may vary (extensively) within each period TPWM of the PWM signal.

    [0057] Removing the averaging arrangement 22 (22a, 22b) from the control loop (by possibly locating it outside the control loop as exemplified in Figure 4) and consequently updating the signals in the PID control arrangement with a frequency (possibly much) higher than the frequency of the PWM signal dispenses with the delay or latency (equal to one cycle of the PWM signal) exhibited in arrangement as exemplified in Figures 1 and 2.

    [0058] This facilitates selecting for the coefficients KP, KI and KD fairly high values without detriment to frequency stability. This in turn facilitates a faster response to transients in the set point signal (SP) and improved rejection to undesired variations in the supply signal (VS).

    [0059] For instance, in one or more embodiments as exemplified herein, selecting for the coefficients KP, KI, KD values which facilitate keeping overshoot (undershoot) under ±10% with respect to a typical specification value, may result in a delay of 4 mS in the response to a (positive or negative) step in the average value of the current through the load) returns within a range of e.g. 1% of the desired value. This response to an input step is approximately three times faster that the corresponding performance observed in an arrangement as shown in Figures 1 and 2.

    [0060] Similarly, one may observe that in one or more embodiments as exemplified in Figures 3 and 4 a positive/negative step from 10V to 15V (or from 15V to 10V) applied to the supply voltage VS may result in a transient current of +3% (-4%) over a time interval of 3mS (2mS).

    [0061] Possible performance of embodiments are exemplified herein is presented in Figures 5A, 5B and 6 which show over time abscissa scales in ms:
    • a possible time behavior of a load current ILOAD (Figure 4) and its average value IAVERAGE (OS = overshoot) in the presence of a normalized upward step in the set point value SP (Figure 5A);
    • a corresponding behavior of the PID current from the controller 14 and the ramp signal Ramp to the PWM generator 12 (Figure 5B);
    • a possible time behavior of a load current IS (Figure 3) in the presence of a square wave variation between 0.5 and 1 in the set point value SP showing overshoot/undershoot confined within ±10% (Figure 6).


    [0062] One or more embodiments as exemplified in Figures 3 and 4 thus facilitate improving performance in respect of perturbations (on VS) with a sensitivity ten times lower over time durations three times shorter in comparison with conventional arrangements.

    [0063] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the extent of protection.

    [0064] The extent of protection is determined by the annexed claims.


    Claims

    1. A method of controlling a PWM signal generator (12) configured (D) to provide a supply current (IS; ILOAD) to an electrical load (L), the PWM signal generator (12) generating PWM signals at a first frequency (fPWM), the PWM signals having a duty cycle, the method comprising:

    - receiving a set point signal (SP) indicative of a target value for said supply current (IS; ILOAD),

    - sensing (20; 20a, 20b) a sensing signal (IX) indicative of a current value for said supply current ((IS; ILOAD),

    - performing a closed-loop control of said supply current (IS; ILOAD) targeting said target value (SP) for said supply current via a controller (14; 141, 142, 143, 144) controlling (PID) the duty cycle of the PWM signals generated by the PWM signal generator (12) as a function of the offset (18) of the sensing signal (IX) with respect to the set point signal (SP), wherein

    the controller circuit (14; 141, 142, 143) comprises at least one signal processing branch (142, 143) operating on discrete-time signals which are updated at a second frequency (fCLK), characterized in that
    the method comprises selecting said second frequency (fCLK) as a multiple of said first frequency (fPWM) at least one order of magnitude higher than said first frequency (fPWM).
     
    2. The method of claim 1, comprising selecting said second frequency (fCLK) about three orders of magnitude higher than said first frequency (fPWM).
     
    3. The method of claim 1 or claim 2, comprising forwarding (18) the sensing signal (IX) to said controller (14; 141, 142, 143) in the absence of averaging processing applied to said sensing signal (Ix) .
     
    4. The method of any of claims 1 to 3, comprising generating (20b) a discrete-time version of the sensing signal (IX) and controlling (14; 141, 142, 143) the duty cycle of the PWM signals generated by the PWM signal generator (12) as a function of the offset (18) of said discrete-time version of the sensing signal (IX) with respect to the set point signal (SP).
     
    5. The method of claim 1, wherein the controller (14; 141, 142, 143) comprises a PID controller including a integral branch (142; KI, 142a) and a derivative branch (143; KD, 143a) operating on discrete-time signals.
     
    6. The method of any of the previous claims, wherein the controller (14; 141, 142, 143) is a digital controller and the method comprises forwarding (18) to said controller (14; 141, 142, 143) said sensing signal (IX) in digital form (20b).
     
    7. A circuit, comprising:

    - a PWM signal generator (12) configured (D) to provide a supply current (IS; ILOAD) to an electrical load (L), the PWM signal generator (12) generating PWM signals with a first frequency (fPWM), the PWM signals having a duty cycle,

    a controller (14; 141, 142, 143) configured to receive an offset signal (18) indicative of the offset of a sensing signal (IX) indicative of a current value for said supply current (IS; ILOAD) with respect to a set point signal (SP) indicative of a target value for said supply current (ILOAD),
    the controller (14; 141, 142, 143) configured to perform a closed-loop control of said supply current (ILOAD) targeting said target value (SP) for said supply current (IS; ILOAD) by controlling (PID) said PWM signal generator (12) such that the duty cycle of the PWM signals generated by the PWM signal generator (12) is controlled as a function of said offset signal (18) with the method of any of claims 1 to 6.
     
    8. A device (10, D, L) comprising:

    - a circuit (10) according to claim 7, and

    - an electrical load (L) coupled (D) to said PWM signal generator (12) to receive said supply current (Is; ILOAD) .


     


    Ansprüche

    1. Verfahren zum Steuern eines PWM-Signalgenerators (12), der konfiguriert (D) ist, um einen Versorgungsstrom (Is; ILOAD) für eine elektrische Last (L) bereitzustellen, wobei der PWM-Signalgenerator (12) PWM-Signale mit einer ersten Frequenz (fPWM) generiert, wobei die PWM Signale einen Arbeitszyklus aufweisen, wobei das Verfahren umfasst:

    - Empfangen eines Sollwertsignals (SP), das auf einen Zielwert für den Versorgungsstrom (IS; ILOAD) hinweist,

    - Erfassen (20; 20a, 20b) eines Erfassungssignals (Ix), das auf einen Stromwert für den Versorgungsstrom ((IS; ILOAD) hinweist,

    - Durchführen einer Regelung des Versorgungsstroms (Is; ILOAD), die auf den Zielwert (SP) für den Versorgungsstrom abzielt, über eine Steuerung (14; 141, 142, 143, 144), die den Arbeitszyklus der PWM Signale, die von dem PWM-Signalgenerator (12) generiert werden, in Abhängigkeit von dem Versatz (18) des Erfassungssignals (Ix) in Bezug auf das Sollwertsignal (SP) steuert (PID),

    wobei die Steuerungsschaltung (14; 141, 142, 143) mindestens einen Signalverarbeitungszweig (142, 143) umfasst, der auf zeitdiskreten Signalen betrieben wird, die auf einer zweiten Frequenz (fCLK) aktualisiert werden, dadurch gekennzeichnet, dass
    das Verfahren das Auswählen der zweiten Frequenz (fCLK) als Vielfaches der ersten Frequenz (fPWM) mindestens eine Größenordnung über der ersten Frequenz (fPWM) umfasst.
     
    2. Verfahren nach Anspruch 1, das Auswähle der zweiten Frequenz (fCLK) etwa drei Größenordnungen über der ersten Frequenz (fPWM) umfassend.
     
    3. Verfahren nach Anspruch 1 oder Anspruch 2, umfassend das Weiterleiten (18) des Erfassungssignals (Ix) zu der Steuerung (14; 141, 142, 143), in Abwesenheit einer Mittelungsverarbeitung, die auf das Erfassungssignal (Ix) angewandt wird.
     
    4. Verfahren nach einem der Ansprüche 1 bis 3, umfassend das Generieren (20b) einer zeitdiskreten Version des Erfassungssignals (IX) und Steuern (14; 141, 142, 143) des Arbeitszyklus der PWM Signale, die von dem PWM-Signalgenerator (12) generiert werden, in Abhängigkeit von dem Versatz (18) der zeitdiskreten Version des Erfassungssignals (IX) in Bezug auf das Sollwertsignal (SP).
     
    5. Verfahren nach Anspruch 1, wobei die Steuerung (14; 141, 142, 143) eine PID-Steuerung umfasst, die einen Integralzweig (142; KI, 142a) und einen Ableitungszweig (143; KD, 143a) umfasst, der auf zeitdiskreten Signalen betrieben wird.
     
    6. Verfahren nach einem der vorstehenden Ansprüche, wobei die Steuerung (14; 141, 142, 143) eine digitale Steuerung ist und das Verfahren Weiterleiten (18) des Erfassungssignals (IX) in digitaler Form (20b) zu der Steuerung (14; 141, 142, 143) umfasst.
     
    7. Schaltung, umfassend:

    - einen PWM-Signalgenerator (12), der konfiguriert (D) ist, um einen Versorgungsstrom (Is; ILOAD) für eine elektrische Last (L) bereitzustellen, wobei der PWM-Signalgenerator (12) PWM-Signale mit einer ersten Frequenz (fPWM) generiert, wobei die PWM Signale einen Arbeitszyklus aufweisen,

    - eine Steuerung (14; 141, 142, 143), die konfiguriert ist, um ein Versatzsignal (18) zu empfangen, das auf den Versatz eines Erfassungssignals (Ix) hinweist, das auf einen Stromwert für den Versorgungsstrom (IS; ILOAD) in Bezug auf ein Sollwertsignal (SP) hinweist, das auf einen Zielwert für den Versorgungsstrom (ILOAD) hinweist,

    - die Steuerung (14; 141, 142, 143), die konfiguriert ist, um eine Regelung des Versorgungsstroms (ILOAD) durchzuführen, die auf den Zielwert (SP) für den Versorgungsstrom (IS; ILOAD) abzielt, durch Steuern (PID) des PWM-Signalgenerators (12), sodass der Arbeitszyklus der PWM Signale, die von dem PWM-Signalgenerator (12) generiert werden, in Abhängigkeit von dem Versatzsignal (18) mit dem Verfahren nach einem der Ansprüche 1 bis 6 gesteuert wird.


     
    8. Vorrichtung (10, D, L), umfassend:

    - eine Schaltung (10) nach Anspruch 7, und

    - eine elektrische Last (L), die mit dem PWM-Signalgenerator (12) gekoppelt (D) ist, um den Versorgungsstrom (IS; ILOAD) zu empfangen.


     


    Revendications

    1. Procédé de commande d'un générateur de signaux MID (12) configuré (D) pour fournir un courant d'alimentation (Is ; ILOAD) à une charge électrique (L), le générateur de signaux MID (12) générant des signaux MID à une première fréquence (fPWM), les signaux MID ayant un rapport cyclique, le procédé comprenant les étapes suivantes :

    - recevoir un signal de point de consigne (SP) indiquant une valeur cible pour ledit courant d'alimentation (IS ; ILOAD),

    - détecter (20 ; 20a, 20b) un signal de mesure (Ix) indiquant une valeur d'intensité pour ledit courant d'alimentation (IS ; ILOAD),

    - réaliser un asservissement dudit courant d'alimentation (IS ; ILOAD) en visant ladite valeur cible (SP) pour ledit courant d'alimentation au moyen d'un contrôleur (14 ; 141, 142, 143, 144) qui commande (PID) le rapport cyclique des signaux MID générés par le générateur de signaux MID (12) en fonction de l'écart (18) du signal de mesure (Ix) par rapport au signal de point de consigne (SP),

    dans lequel le circuit de contrôleur (14 ; 141, 142, 143) comprend au moins une branche de traitement du signal (142, 143) agissant sur des signaux de temps discrets qui sont actualisés à une deuxième fréquence (fCLK),
    caractérisé en ce que le procédé comprend la sélection de ladite deuxième fréquence (FCLK) sous la forme d'un multiple de ladite première fréquence (fPWM) au moins un ordre de grandeur plus grand que ladite première fréquence (fPWM).
     
    2. Procédé selon la revendication 1, comprenant la sélection d'une deuxième fréquence (fCLK) environ trois ordres de grandeur plus grande que ladite première fréquence (fPWM).
     
    3. Procédé selon la revendication 1 ou 2, comprenant le fait de transmettre (18) le signal de mesure (Ix) audit contrôleur (14 ; 141, 142, 143) en l'absence d'un traitement de calcul de moyenne appliqué audit signal de mesure (Ix).
     
    4. Procédé selon l'une quelconque des revendications 1 à 3, comprenant le fait de générer (20b) une version temporelle discrète du signal de mesure (Ix) et de commander (14 ; 141, 142, 143) le rapport cyclique des signaux MID générés par le générateur de signaux MID (12) en fonction de l'écart (18) de ladite version temporelle discrète du signal de mesure (Ix) par rapport au signal de point de consigne (SP).
     
    5. Procédé selon la revendication 1, dans lequel le contrôleur (14 ; 141, 142, 143) comprend un contrôleur PID comprenant une branche intégrale (142 ; KI, 142a) et une branche dérivée (143 ; KD, 143a) agissant sur des signaux temporels discrets.
     
    6. Procédé selon l'une quelconque des revendications précédentes, dans lequel le contrôleur (14 ; 141, 142, 143) est un contrôleur numérique et le procédé comprend le fait de transmettre (18) audit contrôleur (14 ; 141, 142, 143) ledit signal de mesure (Ix) sous forme numérique (20b).
     
    7. Circuit comprenant :

    - un générateur de signaux MID (12) configuré (D) pour fournir un courant d'alimentation (Is ; ILOAD) à une charge électrique (L), le générateur de signaux MID (12) générant des signaux MID à une première fréquence (fPWM), les signaux MID ayant un rapport cyclique,

    un contrôleur (14 ; 141, 142, 143) configuré pour recevoir un signal d'écart (18) représentant le décalage d'un signal de mesure (Ix) indiquant une valeur d'intensité pour ledit courant d'alimentation (IS ; ILOAD) par rapport à un signal de point de consigne (SP) indiquant une valeur cible pour ledit courant d'alimentation (ILOAD),
    le contrôleur (14 ; 141, 142, 143) étant configuré pour réaliser un asservissement dudit courant d'alimentation (ILOAD) en visant ladite valeur cible (SP) pour ledit courant d'alimentation (Is ; ILOAD) en commandant (PID) ledit générateur de signaux MID (12) de telle manière que le rapport cyclique des signaux MID générés par le générateur de signaux MID (12) est commandé en fonction dudit signal d'écart (18) avec le procédé de l'une quelconque des revendications 1 à 6.
     
    8. Dispositif (10, D, L) comprenant :

    - un circuit (10) selon la revendication 7, et

    - une charge électrique (L) couplée (D) audit générateur de signaux MID (12) de manière à recevoir ledit courant d'alimentation (IS ; ILOAD).


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description