TECHNICAL FIELD
[0001] The present invention relates to a device for self-adjusting an electrical threshold for detecting a power failure as well as to a method for determining the electrical threshold for detecting a power failure.
STATE OF THE ART
[0002] In the automotive electronic device, it is known to supervise the power consumption of an electric charge. In order to supervise a power excess or a power failure of the electric charge, it is known to control the product of the supply voltage of the charge by the current consumption of the charge in order to evaluate the power consumption. The power consumption of the charge thus calculated is then compared with a maximum power threshold beyond which an electric charge failure can be diagnosed, and/or also with a minimum power threshold below which an electric charge failure can also be diagnosed.
[0003] The existing devices require computing power as well as reaction times penalizing the consumption and responsiveness of the existing devices.
[0004] It is therefore important to propose a new solution solving this problem.
SUMMARY OF THE INVENTION
[0005] According to the invention, a device for self-adjusting an electrical threshold for detecting an electric power consumption failure of an electric charge, preferably of the charge of a motor vehicle, comprises a plurality of reference signals of increasing values according to a geometric sequence for which the product of two terms of equidistant order at both ends of the sequence equals a maximum reference power (Pref), the plurality of reference signals being representative of the variation of a supply signal of the electric charge; the device further comprises a setpoint signal representative of the supply signal of the electric charge; a framing unit including a plurality of successive intervals of reference signals sequentially bounded by the terms of the geometric sequence of the plurality of reference signals, the device further comprises a measurement signal including the setpoint signal, a plurality of output signals, logic signal processing means configured to assign to a first output signal of the plurality of output signals a binary state of belonging of the setpoint signal to a first interval of reference signals including a first term of the geometric sequence, and at least one electrical switch configured to be controlled by the first output signal and configured to provide a reference signal of the plurality of reference signals of a value of a second term of the geometric sequence, such that the first term and the second term are of equidistant order at both ends of the geometric sequence, the second term being representative of the electrical threshold for detecting an electric power consumption failure of the electric charge.
[0006] The logic signal processing means may be configured to assign to the other binary output signals of the plurality of binary output signals a binary state of non-belonging of the setpoint signal to the other intervals of reference signals.
[0007] The plurality of reference signals may comprise successive electrical connection nodes of a resistor network in series.
[0008] The logic signal processing means may include a plurality of comparators ordered from 1 to N each comprising respectively a reference signal ordered from 1 to N of the plurality of reference signals, each comparator also comprising the setpoint signal, so as to be able to compare the setpoint signal with each reference signal; a plurality of logic devices ordered from 1 to N-1 comprising a plurality of 'inverter'-type logic gates ordered from 1 to N-1, each input of each 'inverter'-type logic gate of order 1 to N-1 being respectively electrically connected to the output of each comparator of order 2 to N; and also comprising a plurality of two-input 'AND'-type logic gates ordered from 1 to N-1, each first input of each two-input 'AND'-type logic gate ordered from 1 to N-1 being respectively electrically connected to each output of each 'inverter'-type logic gate ordered from 1 to N-1, each second input of each two-input 'AND'-type logic gate ordered from 1 to N-1 being respectively electrically connected to each ordered output of each comparator of order 1 to N-1; the plurality of 'AND'-type logic gates of order 1 to N-1 including respectively the plurality of output signals ordered from 1 to N-1 of the framing unit.
[0009] According to the invention, a method for determining an electrical threshold for detecting a failure of electric power consumed by an electric charge, preferably an electric charge of a motor vehicle, comprises the steps of:
determining a maximum reference power (Pref) representative of the maximum allowable power of the electric charge;
providing a plurality of reference signals of increasing values according to a geometric sequence for which the product of two terms of equidistant order at both ends of the sequence equals the maximum reference power (Pref); the plurality of reference signals being representative of the variation of a supply signal of the electric charge;
defining a plurality of successive intervals of reference signals successively bounded by the terms of the geometric sequence of the plurality of reference signals;
providing a setpoint signal representative of the supply signal of the electric charge;
allocating to the setpoint signal a first term of the geometric sequence of an interval of reference signals framing as close as possible the value of the setpoint signal;
allocating to the electrical threshold for detecting a failure of electric power consumed by the electric charge a second term of the geometric sequence of reference signals such that the first term and the second term are of equidistant order at both ends of the sequence.
[0010] Other objects and advantages of the present invention will become apparent in light of the following description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Other characteristics, objects and advantages of the invention will become apparent upon reading the following detailed description, and in light of the appended drawings given by way of non-limiting example and in which:
[Fig. 1] represents a block diagram of the device for self-adjusting an electrical threshold for detecting a power failure according to a first embodiment of the invention.
[Fig. 2] represents a block diagram of the self-adjusting device according to a second embodiment of the invention.
[Fig. 3] represents a block diagram of the self-adjusting device according to a third embodiment of the invention.
[Fig. 4] represents a flowchart of a method for determining an electrical detection threshold according to a first embodiment of the method.
DETAILED DESCRIPTION
[0012] According to Figure 1, a device for self-adjusting 10 an electrical threshold for detecting Sth an electric power failure of an electric charge is represented. Preferably, said threshold is a comparison threshold provided to be able to detect an electric power consumption failure of a charge of a motor vehicle.
[0013] The self-adjusting device 10 is configured to provide a self-adjusting electrical threshold for detecting an electric power failure based on the variations of a supply signal of the electric charge.
[0014] The self-adjusting device 10 comprises a plurality of reference signals SR
_{1}, SR
_{N} of increasing values according to a geometric sequence for which the result of the product of any two terms of equidistant order at both ends of the sequence is generally constant. The result of the product of the any two terms of equidistant order at both ends is also equivalent to the product of the ends of the geometric sequence. The particularity of the invention lies in the exploitation of this property specific to the geometric suites. According to the invention, although the terms of the geometric sequence representative of the plurality of reference signals SR
_{1}, SR
_{N} are of the same nature, namely representative of an electric current or of an electric voltage, the absolute value of each of two equidistant terms from the ends of the sequence is an image for one of the two terms of the value of a supply voltage of the electric charge, the other term being the image of a supply current of the electric charge, so that the product of the value of the two terms represent an image of a maximum reference power (Pref) representative of the maximum power allowable by the electric charge. The plurality of reference signals SR
_{1}, SR
_{N} is therefore an image of the possible variation of a supply signal of the electric charge.
[0015] The power supply of an electric charge of a motor vehicle may, for example, in a non-limiting manner, in some cases, vary between 0 Volt, during a power cutoff, up to 18 volts depending on the conditions of use of the vehicle battery. The plurality of reference signals SR
_{1}, SR
_{N} is generally an indirect representation of the variations of the battery voltage; in other words, the plurality of reference signals SR
_{1}, SR
_{N} comprises reference signals (SR
_{1}, SR
_{N}) of values proportional to the values of voltages of the vehicle battery.
[0016] In order to supervise the electric power consumed by the electric charge, the self-adjusting device 10 comprises a setpoint signal Sc representative of the supply signal of the electric charge. The setpoint signal Sc can be directly the supply signal of the electric charge, such as the voltage of the vehicle battery or the electric current consumed by the charge on the battery, or an image of the supply signal of the electric charge, such as a reduced value of the voltage of the battery or a reduced value of the electric current consumed by the charge on the battery.
[0017] According to Figure 1, the self-adjusting device 10 comprises a framing unit 12 including as input signals a plurality of successive intervals I
_{1}, I
_{2}, I
_{N-1} of the type [SR
_{1}, SR
_{2}[, [SR
_{2}, SR
_{3}[, [SR
_{N-1}, SR
_{N}[ successively bounded by the terms of the geometric sequence of the plurality of reference signals SR
_{1}, SR
_{N} and also a measurement signal including the setpoint signal Sc. The framing unit 12 is configured to determine an interval I
_{2} bounded by two successive terms of the geometric sequence, that is to say by two values of the successive reference signals of the type [SR
_{2}, SR
_{3}[, for framing the value of the setpoint signal Sc.
[0018] The framing unit 12 also comprises a plurality of binary output signals SS
_{1}, SS
_{N-1} and logic signal processing means 14 configured to assign to a first binary output signal SS
_{2} of the plurality of binary output signals SS
_{1}, SS
_{N-1} a binary state of belonging of the setpoint signal Sc to a first interval I
_{2} of the type [SR
_{2}, SR
_{3}[ including a first term of the geometric sequence of a value of the reference signal SR
_{2} of lower bound of the first interval I
_{2}. A belonging binary state may be a 'high' logic level, i.e. a binary value of '1'.
[0019] The logic signal processing means 14 are also configured to assign to the other binary output signals SS
_{1}, SS
_{3}, SS
_{N-1} of the plurality of binary output signals SS
_{1}, SS
_{N-1} a binary state of non-belonging of the setpoint signal Sc to the other intervals I
_{1}, I
_{3}, I
_{N-1} of the type [SR
_{1}, SR
_{2}[, [SR
_{3}, SR
_{4}[, [SR
_{N-1}, SR
_{N}[. A non-belonging binary state may be a 'low' logic level, i.e. a binary value of '0'.
[0020] In other words, each interval I
_{1}, I
_{N-1} of the type [SR
_{1}, SR
_{2}[, [SR
_{N-1}, SR
_{N}[ cooperates with a determined binary output signal SS
_{1}, SS
_{N-1} of the framing unit 12 so that the binary state of each binary output SS
_{1}, SS
_{N-1} indicates the belonging or non-belonging of the value of the setpoint signal Sc to a single determined interval I
_{2} of the type [SR
_{2}, SR
_{3}[. The value of the setpoint signal Sc is representative of the amplitude of the supply signal of the charge.
[0021] According to Figure 1, the self-adjusting device 10 includes a switching unit 16 comprising a plurality of electrical switches EC
_{1}, EC
_{N-1} each able to switch a single reference signal SR
_{N} of the plurality of reference signals SR
_{1}, SR
_{N}, each reference signal SR
_{1}, SR
_{N} being each able to be switched by a single electrical switch EC
_{2}. Each electrical switch EC
_{1}, EC
_{N-1} is an element with an input S
_{EEC1}, S
_{EECN-1}, an output S
_{SEC1}, S
_{SECN-1} and a control signal S
_{cd1}, S
_{cdN-1} allowing the switching of the input signal S
_{EEC1} of the switch on its output S
_{SEC1}.
[0022] According to the embodiment of Figure 1, one of the electrical switches EC
_{2} is configured to be controlled by the first binary output signal SS
_{2} and is configured to provide a reference signal SR
_{N-1} of the plurality of reference signals SR
_{1}, SR
_{N} of a value of a second term of the geometric sequence of a second interval I
_{N-1} of the type [SR
_{N-1}, SR
_{N}[, such that the first term and the second term are of equidistant order at both ends of the geometric sequence, the second term being representative of the electrical threshold for detecting Sth a power failure provided to be able to detect a electric power consumption failure of the electric charge.
[0023] In other words, when the first binary output signal SS
_{2} is in a binary state of the type '1', said first binary output signal SS
_{2} allows the closure of a single electrical switch EC
_{2} for switching the second term of the geometric sequence of the second interval I
_{N-1} of the type [SR
_{N-1}, SR
_{N}[, such that the result of the product of the first term with the second term represents the maximum reference power representative of the maximum power allowable by the electric charge. The output signal S
_{SEC2} of the single electrical switch EC
_{2} subjected to closure control therefore represents the electrical threshold for detecting Sth a power failure.
[0024] The other electrical switches EC
_{1}, EC
_{3}, EC
_{N-1} are configured to be controlled by the other binary output signals SS
_{1}, SS
_{3}, SS
_{N-1} so that, when these are all in a binary state of non-belonging of the setpoint signal SC to the other intervals I
_{1}, I
_{3}, I
_{N-1} of the type [SR
_{1}, SR
_{2}[, [SR
_{3}, SR
_{4}[, [SR
_{N-1}, SR
_{N}[, the other electrical switches EC
_{1}, EC
_{3}, EC
_{N-1} remain open so that no other reference signal SR
_{N}, SR
_{N-2}, SR
_{2} is switched by the other electrical switches EC
_{1}, EC
_{3}, EC
_{N-1}.
[0025] The advantage of this solution is to be able to monitor a power without needing a voltage/current multiplier in order to compare the calculated power with a predetermined maximum power threshold. The device allows overcoming the complexity of existing solutions by proposing a device that automatically provides an electrical threshold for detecting Sth a power failure representative of the maximum voltage or maximum current that the charge must not exceed based respectively on the supply voltage or current of the charge.
[0026] According to one embodiment of the self-adjusting device 10 represented in Figure 2, the plurality of reference signals SR
_{3}, SR
_{N} is a plurality of N reference voltages V
_{1}, V
_{N} ordered from 1 to N obtained at each electrical connection node of a network of electrical resistors 18 connected in series. The electrical resistor network 18 is connected at one of its ends to a stabilized voltage V
_{s} for supplying the electrical resistor network 18 and at its other end to an electrical ground 20 of the self-adjusting device 10.
[0027] In order to obtain a plurality of N reference voltages V
_{1}, V
_{N} of increasing values according to a geometric sequence with determined common ratio, the resistor network 18 comprises a plurality of N resistors R
_{1}, R
_{N} ordered from 1 to N, for which the resistor values R
_{2}, R
_{N} of order 2 to N increase successively at a constant ratio, the resistor R
_{N} of order N being connected to the stabilized voltage Vs for supplying the electrical resistor network 18 in series. The value of the resistor R
_{1} of order 1 connected to the electrical ground 20 is adjusted so that each reference voltage V
_{1}, V
_{N}, excluding zero voltage of the electrical ground, also increases according to the same constant ratio as the plurality of resistors R
_{2}, R
_{N} of order 2 to N.
[0028] The plurality of N reference voltages V
_{1}, V
_{N} of increasing values defines the plurality of successive intervals I
_{1}, I
_{N-1} of the type [V
_{1}, V
_{2}[, [V
_{2}, V
_{3}[, [V
_{N-1}, V
_{N}[ successively bounded by the values of reference voltages V
_{1}, V
_{N} at the successive electrical connection nodes. The successive intervals I
_{1}, I
_{N-1} are ordered from 1 to N-1.
[0029] According to this embodiment, there will be considered the N reference voltages V
_{1}, V
_{N} of increasing successive values ranging from V
_{1} to V
_{N} as well as the sequence of successive intervals I
_{1}, I
_{N-1} of the type semi-open on the right, that is say of the type [V
_{1}, V
_{2}[, [V
_{2}, V
_{3}[ ... and so on up to the interval of order N-1 of the type [V
_{N-1}, V
_{N}[.
[0030] According to the embodiment represented in Figure 2, the logic signal processing means 14 include a plurality of N-1 comparators C
_{1}, C
_{N-1} ordered from 1 to N-1, each comparator C
_{1}, C
_{N-1} including a single reference voltage V
_{1}, V
_{N-1} from the plurality of reference voltages V
_{1}, V
_{N}, each of the reference voltages V
_{1}, V
_{N-1} being connected to a single comparator C
_{1}. Each reference voltage V
_{1}, V
_{N-1} of order 1 to N-1 is connected respectively to the negative bound of each comparator C
_{1}, C
_{N-1} of order 1 to N-1. In other words, the reference voltage V
_{1} of order 1 is connected to the negative bound of the comparator C
_{1} of order 1, the reference voltage V
_{2} of order 2 is connected to the negative bound of the comparator C
_{2} of order 2, and so on up to the reference voltage V
_{N-1} of order N-1 connected to the comparator C
_{N-1} of order N-1.
[0031] According to the embodiment of Figure 2, the setpoint signal Sc is a setpoint voltage Vc representative of the supply voltage of the electric charge. Each comparator C
_{1}, C
_{N-1} is configured to compare the setpoint voltage Vc with its respective reference voltage V
_{1}, V
_{N-1} so that only the comparators C
_{1}, C
_{N-1} having as reference voltage V
_{1}, V
_{N-1} a voltage of amplitude lower than the amplitude of the setpoint voltage Vc can provide at the output of the comparator a 'high' logic level, i.e. a binary value of '1'. In this case, the other comparators provide at the output of the comparator a 'low' logic level, i.e. a binary value of '0.
[0032] In other words, when the amplitude of the setpoint voltage Vc is greater than a reference voltage V
_{M} of any order M from 1 to N-1, the comparators C
_{1}, C
_{M} of order 1 to M provide at the output of the comparator a 'high' logic level, i.e. a binary value of '1', the comparators C
_{M+1}, C
_{N-1} of order M+1 to N-1 provide at the output of the comparator a 'low' logic level, i.e. a binary value of '0'.
[0033] According to the embodiment represented in Figure 2, the logic signal processing means 14 include a plurality N-2 of logic devices DL
_{1}, DL
_{N-2} ordered from 1 to N-2. Each logic device DL
_{1}, DL
_{N-2} of order 1 to N-2 provides a plurality N-2 of binary output signals SS
_{1}, SS
_{N-2} of belonging or non-belonging of the setpoint voltage Vc to an interval I
_{1}, I
_{N-2} of order 1 to N-2 of the type [V
_{1}, V
_{2}[, [V
_{N-2}, V
_{N-1} [.
[0034] The output of the comparator C
_{N-1} of order N-1 directly provides a binary output signal SS
_{N-1} of order N-1 of belonging or non-belonging of the setpoint voltage to the interval I
_{N-1} of order N-1 of the type [V
_{N-1}, V
_{N}[.
[0035] It is obvious that the setpoint voltage Vc cannot belong to more than one reference voltage interval I
_{1}. In other words, the setpoint voltage Vc cannot be framed by more than one reference voltage interval I
_{1}.
[0036] For this purpose, each logic device DL
_{1}, DL
_{N-2} includes an inverter-type logic gate INV
_{1}, INV
_{N-2} whose input is electrically connected to the output of the comparator C
_{2}, C
_{N-1} of higher order. In other words, the input of the 'inverter'-type logic gate INV
_{M-1} of order M-1 is electrically connected to the output of the comparator C
_{M} of order M.
[0037] In addition, each logic device DL
_{1}, DL
_{N-2} includes a two-input 'AND'-type logic gate AND
_{1}, AND
_{N-2}. Each 'AND'-type logic gate AND
_{1}, AND
_{N-2} includes a first input electrically connected to the output of the 'inverter'-type logic gate INV
_{1}, INV
_{N-2} of the same order, the other input of the 'AND'-type logic gate AND
_{1}, AND
_{N-2} being electrically connected to the output of the comparator C
_{1}, C
_{N-2} of the same order. In other words, the first input of the 'AND'-type logic gate AND
_{M-1} of order M-1 is electrically connected to the output of the 'inverter'-type logic gate INV
_{M-1} of order M-1, the other input of the 'AND'-type logic gate AND
_{M-1} of order M-1 is electrically connected to the comparator C
_{M-1} of order M-1.
[0038] According to the arrangement of the plurality of logic devices DL
_{1}, DL
_{N-2} of the embodiment of Figure 2, when the comparators C
_{1}, C
_{M} of order 1 to M each provide a comparator output of 'high' logic level, the binary outputs SS
_{1}, SS
_{M-1} of belonging or non-belonging of the setpoint voltage Vc to an interval I
_{1}, I
_{M-1} of order 1 to M-1 of reference signals are then in a 'low' logic state, meaning the non-belonging of the setpoint voltage Vc to the successive intervals I
_{1}, I
_{M-1} of order 1 to M-1. Indeed, the 'inverter'-type logic gates INV
_{1}, INV
_{M-1} of order 1 to M-1 set a 'low' logic state to the first input of each 'AND'-type logic gate AND
_{1}, AND
_{M-1} of order 1 to M-1.
[0039] In this case, the comparator C
_{M+1} of order M+1 provides a low logic level at the input of the 'inverter'-type logic gate INV
_{M} of order M, so that the first input of the 'AND'-type logic gate AND
_{M} of order M is in a 'high' logic state.
[0040] In this case, only the binary output SS
_{M} of order M of belonging or non-belonging of the setpoint voltage Vc to an interval I
_{M} of order M of reference voltages is in a 'high' state, meaning the belonging of the setpoint voltage Vc to the single interval I
_{M} of order M.
[0041] According to the embodiment represented in Figure 2, the self-adjusting device 10 includes a plurality N-1 of electrical switches SW
_{1}, SW
_{N-1} ordered from 1 to N-1. Each electrical switch SW
_{1}, SW
_{N-1} of order 1 to N-1 is respectively controlled by a binary output signal SS
_{1}, SS
_{N-1} of belonging or non-belonging of the setpoint voltage Vc to an interval I
_{1}, I
_{N-1} of order 1 to N-1 of reference signals. Each electrical switch SW
_{1}, SW
_{N-1} is in a closed or on state when its control signal is in a 'high' logic state. In other words, an electrical switch SW
_{M} of any order M is configured to switch an electrical signal present on its input toward its output when its control signal is a binary output SS
_{M} of a logic device DL
_{M} of order M indicating the belonging of the setpoint voltage to an interval I
_{M} of order M of reference signals.
[0042] Conversely, each electrical switch SW
_{1}, SW
_{N-1} is in an open or off state when its control signal is in a 'low' logic state so that a signal present on the input of the electrical switch SW
_{1}, SW
_{N-1} is not switched at the output of the electrical switch SW
_{1}, SW
_{N-1}.
[0043] According to the description of the plurality of logic devices DL
_{1}, DL
_{N-2}, not more than one electrical switch SW
_{1} can be subjected to closure control since a single binary output SS
_{1} of belonging or non-belonging of the setpoint voltage Vc to an interval I
_{1} of reference signals can be in a 'high' state, meaning the belonging of the setpoint voltage Vc to a single reference voltage interval I
_{1}.
[0044] According to the embodiment of Figure 2, all the outputs of the plurality of electrical switches SW
_{1}, SW
_{N-1} are electrically connected together so as to form the electrical threshold for detecting Sth the electric power failure consumed by the electric charge. For this purpose, the electrical threshold for detecting Sth the electric power failure is therefore the input signal of the electrical switch SW
_{1} subjected to closure control.
[0045] Indeed, according to the embodiment of Figure 2, each input of each electrical switch SW
_{1}, SW
_{N-1} of order 1 to N-1 is electrically connected respectively to a reference voltage of order N to 2; each electrical switch SW
_{1}, SW
_{N-1} of order 1 to N-1 being respectively controlled by a binary output SS
_{1}, SS
_{N-1} of order 1 to N-1, of belonging or non-belonging of the setpoint voltage Vc to an interval I
_{1}, I
_{N-1} of order 1 to N-1.
[0046] In other words, the input signal of the electrical switch SW
_{N-1} of order N-1 is electrically connected to the reference voltage V2 of order 2; the input signal of the electrical switch SW
_{N-2} of order N-2 is electrically connected to the reference voltage V
_{3} of order 3, and so on up to the input signal of the electrical switch of order 2 electrically connected to the reference voltage V
_{n-1} of order N-1, and finally up to the input signal of the electrical switch SW
_{1} of order 1 electrically connected to the reference voltage V
_{N} of order N .
[0047] According to this arrangement, by virtue of the mathematical properties of the geometric sequence formed by the plurality N of the reference voltages V
_{1}, V
_{N}, the product of the value of the signal switched by the electrical switch SW
_{1} controlled by the binary output signal SS
_{1} of the logic device DL
_{1} indicating the belonging of the setpoint voltage Vc to a reference voltage interval I
_{1} by the value of the lower bound of said interval I
_{1} is representative of the maximum reference power representative of the maximum power allowable by the electric charge.
[0048] In other words, the threshold for detecting Sth a power failure provided by the self-adjusting device 10 is the value of the reference voltage V
_{N-1} of a first term of the geometric sequence of the plurality of reference voltages V
_{1}, V
_{N} such that this first term and the second term of the geometric sequence representative of the lower bound of the interval I
_{2} of belonging of the setpoint voltage V
_{c} are terms equidistant from the ends of the geometric sequence of the plurality of reference voltages V
_{1}, V
_{N}.
[0049] According to the particular embodiment of Figure 3, the resistor network 18 may comprise 24 resistors R
_{1}, R
_{24} for which the theoretical value of the resistor R2 of order 2 is equal to 123.74 Ohm, and for which the constant ratio between two resistors R2, R3 of successive order of 2 to 24 is equal to 1.1 so that the value of the resistor R
_{24} of order 24 is equal to 1000 Ohm. The theoretical value of the resistor R
_{1} of order 1 can be adjusted to 1242 Ohm so that the stabilized supply voltage Vs at the voltage node of order 24 decreases according to the ratio of constant order 1.1 successively up to the node of order 1, that is to say the electrical connection node between the resistor R
_{1} of order 1 and the resistor R
_{2} of order 2. The advantage of this particular embodiment lies in the fact that the values of the resistors R2, R24 of order 2 to 24 can generally correspond in practice to the successive standardized values of the resistors of the series E24, the value of the resistor R
_{1} of order 1 can also generally correspond to a standardized value of a resistor of the series E24.
[0050] For this particular non-limiting example, by having for example a stabilized voltage Vs for supplying the resistor network of 3 volts, the reference voltage V
_{24} of order 24 will be 3 volts, the reference voltage V
_{23} of order 23 will be equal to 2.73 volts and so on, the reference voltage V
_{2} of order 2 will be equal to 0.37 Volt and finally the reference voltage V
_{1} of order 1 will be equal to 0.34 volt.
[0051] According to this example, it is possible to deduce the 23 successive intervals I
_{1}, I
_{23} of reference voltages, such as for example, the two first intervals: I
_{1}[0.34 Volt, 0.37 Volt[ and I
_{2}[0.37 Volt, 0.41 Volt [and the last interval I
_{23}[2.73 Volts, 3 Volts [.
[0052] According to this example, the result of the product of two equidistant order terms at both ends of the geometric sequence formed by the reference voltages, that is to say for example, the product of the reference voltage V
_{24} of order 24 with the reference voltage V
_{1} of order 1, as well as the product of the reference voltage V
_{23} of order 23 with the reference voltage V
_{2} of order 2, or the product of the reference voltage V
_{13} of order 13 with the reference voltage V
_{12} of order 12, is of order 1.
[0053] According to this example, the plurality of the reference voltages V
_{1}, V
_{24} is therefore dimensioned so that the self-adjusting device 10 allows monitoring at least one electrical device, such as a vehicle electric charge, that must not consume a maximum power greater than 1 Watt, the maximum power being the reference power defined by the self-adjusting device 10.
[0054] According to Figure 3, the setpoint voltage Vc is an electric voltage that can vary from 0 Volt to 3 Volts. This setpoint voltage Vc can be an image of the battery voltage. According to this example, a device for reducing a factor 6 of the battery voltage allows the self-adjusting device 10 to have a reduced voltage of the battery as a setpoint voltage Vc.
[0055] According to this example, the self-adjusting device 10 comprises 24 comparators C
_{1}, C
_{24} ordered from 1 to 24. Each comparator C
_{1}, C
_{24} comprises respectively on its negative input bound a reference voltage V
_{1}, V
_{24} of order 1 to 24. In other words, the comparator C
_{1} of order 1 comprises a reference voltage V
_{1} on its negative bound of 0.34 Volt, the comparator C
_{2} of order 2 comprises a reference voltage V
_{2} on its negative bound of 0.37 Volt, and so on up to the comparator C
_{23} of order 23 comprising a reference voltage V
_{23} of 2.73 volts, the comparator C
_{24} of order 24 comprising as reference voltage V
_{24} the stabilized voltage Vs for supplying the resistor network 18 namely 3 volts.
[0056] The comparator C
_{24} of order 24, not present in the embodiment of Figure 2, is an option for managing the overvoltage situations beyond the maximum estimated voltage of the battery voltage. This comparator does not question the operation of the self-adjusting device 10 as described according to Figure 2.
[0057] According to Figure 3, in the case of a setpoint voltage Vc of 1.0 Volt, all the comparators C
_{1}, C
_{12} having a reference voltage V
_{1}, V
_{12} less than 1.0 Volt provide at the output of the comparator C
_{1}, C
_{12} a 'high' logic level, i.e. a binary value of '1', the comparators C
_{13}, C
_{24} having a reference voltage greater than 1.0 Volt provide at the output of the comparator C
_{13}, C
_{24} a 'low' logic level, i.e. a binary value of '0'. According to this example, the comparators C
_{1}, C
_{12} of order 1 to 12 provide at the output of the comparator C
_{1}, C
_{12} a high logic level, the comparators C
_{13}, C
_{24} of order 17 to 24 provide at the output of the comparator a low logic level.
[0058] According to Figure 3, the self-adjusting device 10 comprises 23 logic devices ordered from 1 to 23.
[0059] Each of the 23 logic devices includes an 'inverter'-type logic gate INV
_{1}, INV
_{23} ordered from 1 to 23. According to a setpoint voltage Vc of 1.0 Volt, the input signal of each 'inverter'-type logic gate INV
_{12}, INV
_{23} of order 12 to 23 is a 'low' logic level, i.e. a binary value of '0' provided respectively by the comparators C
_{13}, C
_{24} of order 13 to 24. A contrario, the input of each 'inverter'-type logic gate INV
_{1}, INV
_{11} of order 1 to 11 is a 'high' logic level, i.e. a binary value of '1' provided respectively by the comparators C
_{2}, C
_{12} of order 2 to 12.
[0060] Each of the 23 logic devices includes an 'AND'-type logic gate AND
_{1}, AND
_{23} ordered from 1 to 23. Each of the 'AND'-type logic gates AND
_{1}, AND
_{23} of order 1 to 23 comprises a first input electrically connected respectively to the output of each of the 'inverter'-type logic gates INV
_{1}, INV
_{23} of order 1 to 23. Each of the 'AND'-type logic gates AND
_{1}, AND
_{23} of order 1 to 23 comprises a second input electrically connected respectively to the output of each of the comparators C
_{1}, C
_{23} of order 1 to 23.
[0061] According to the setpoint voltage Vc of 1.0 Volt, each of the 'AND'-type logic gates AND
_{13}, AND
_{23} of order 13 to 23 provides a binary output SS
_{13}, SS
_{23} of non-belonging of the setpoint voltage Vc to the intervals I
_{13}, I
_{23} of order 13 to 23, i.e. a binary output SS
_{13}, SS
_{23} of 'low' logic level, i.e. a binary value of '0'. Indeed, the setpoint voltage Vc of 1.0 Volt being lower than the reference voltage V
_{13} of order 13, namely a voltage value of 1.06 Volt, the logic outputs of the comparators C
_{13}, C
_{23} of order 13 to 23 provide respectively to each 'AND'-type logic gate AND
_{13}, AND
_{23} of order 13 to 23, their second input signal of 'low' logic level, i.e. a binary value of '0'.
[0062] According to the setpoint voltage Vc of 1.0 Volt, the 'AND'-type logic gate AND
_{12} of order 12 provides a binary output SS
_{12} of belonging of the setpoint voltage Vc to the interval I
_{12} of order 12, i.e. a binary output SS
_{12} of 'high' logic level of binary value equal to '1' since the value of the setpoint voltage Vc of 1.0 Volt is framed by the interval I
_{12} of order 12 bounded by the reference voltage V
_{12} of order 12 and the reference voltage V
_{12} of order 13 namely the interval semi-open on the right [0.96 Volt, 1.6 Volt[.
[0063] Indeed, since the setpoint voltage Vc of 1.0 Volt is greater than the low reference voltage V
_{12} of the interval I
_{12} of order 12, namely a voltage value of 0.96 Volt, the comparator C
_{12} of order 12 provides to the second input of the 'AND'-type logic gate AND
_{12} of order 12 a 'high' logic level, i.e. a binary value of '1'. Since the first input of the 'AND'-type logic gate AND
_{12} of order 12 is connected to the output of the 'inverter'-type logic gate INV
_{12} of order 12, since said 'inverter'-type logic gate INV
_{12} of order 12 has as input signal the output of the comparator C
_{13} of order 13, i.e. a 'low' logic level, because the setpoint voltage Vc has a value lower than the reference voltage V
_{13} of the comparator of order 13, then the first input of the 'AND'-type logic gate AND
_{12} of order 12 has a 'high' logic level, i.e. a binary value of '1'.
[0064] The two inputs of the 'AND'-type logic gate AND
_{12} of order 12 having a 'high' logic level, i.e. a binary value of '1', said 'AND'-type logic gate AND
_{12} of order 12 provides to the self-adjusting device 10 a binary output SS
_{12} of order 12 of belonging of the setpoint voltage Vc to the interval I
_{12} of order 12, i.e. a binary output SS
_{12} of 'high' logic level, i.e. a binary value of '1'.
[0065] According to the setpoint signal of 1.0 Volt, each 'AND'-type logic gate AND
_{1}, AND
_{11} of order 1 to 11 provides a binary output SS
_{1}, SS
_{11} of non-belonging of the setpoint voltage Vc to the intervals I
_{1}, I
_{11} of order 1 to 11, i.e. a binary output SS
_{1}, SS
_{11} of 'low' logic level, i.e. a binary value of '0', since the setpoint signal of 1.0 Volt is not framed by any interval I
_{1}, I
_{11} of order 1 to 11; namely the first interval I
_{1} of the type semi-open on the right [0.34 Volt, 0.37 Volt], the second consecutive interval I
_{2} [0.37 Volt, 0.41 Volt[ and so on up to the eleventh interval I
_{11} bounded by the reference voltage V
_{11} of order 11 and the reference voltage V
_{12} of order 12, namely the interval semi-open on the right [0.87 Volt, 0.96 Volt[.
[0066] Indeed, each comparator C
_{2}, C
_{12} of order 2 to 12, respectively provides to each 'inverter'-type logic gate INV
_{1}, INV
_{11} of order 1 to 11, an input signal of 'high' logic level, i.e. a binary value of '1'. Indeed, the value of the reference voltage V
_{2}, V
_{12} of each comparator of order 2 to 12 is less than the value of the setpoint voltage Vc. For example, the reference voltage V
_{12} of the comparator C
_{12} of order 12 is equal to 0.96 Volt. As a result, each first input of each 'AND'-type logic gate AND
_{1}, AND
_{11} of order 1 to 11 has a 'low' logic level, i.e. a binary value of '0'. As a result, each 'AND'-type logic gate AND
_{1}, AND
_{11} of order 1 to 11 provides a binary output SS
_{1}, SS
_{11} of non-belonging of the setpoint voltage Vc of a value equal to 1.0 Volt to the intervals I
_{1}, I
_{11} of order 1 to 11.
[0067] According to the setpoint voltage of a value equal to 1.0 Volt, only the binary output signal SS
_{12} of order 12 of the logic signal processing means 14 provides a signal of belonging of the setpoint voltage Vc to an interval I
_{12} of reference voltages, namely the belonging of the setpoint voltage Vc of 1.0 Volt to the interval I
_{12} of order 12, namely the interval I
_{12} semi-open on the right [0.96 Volt, 1.06 Volt[.
[0068] According to Figure 3, the self-adjusting device 10 of the electrical detection threshold Sth includes 24 electrical switches SW
_{1}, SW
_{24} ordered from 1 to 24. Each electrical switch SW
_{1}, SW
_{23} of order 1 to 23 is respectively controlled by the binary output SS
_{1}, SS
_{23} of belonging or non-belonging of the setpoint voltage Vc to a determined interval I
_{1}, I
_{23}, the binary outputs SS
_{1}, SS
_{23} being respectively the outputs of the 'AND'-type logic gate AND
_{1}, AND
_{23} of order 1 to 23. The electrical switch SW
_{24} of order 24 is controlled directly by the output of the comparator C
_{24} of order 24.
[0069] The outputs of the electrical switches SW
_{1}, SW
_{24} of order 1 to 24 are connected together and provide the electrical threshold for detecting Sth an electric power failure. For this purpose, each of the 24 electrical switches SW
_{1}, SW
_{24} is subjected to closure control when its control signal is in a 'high' logic state. In this case no more than a single electrical switch SW
_{12} is subjected to closure control since no more than a single binary output SS
_{12} of belonging or non-belonging of the setpoint voltage Vc to an interval I
_{12} of reference voltages can assume a belonging state, i.e. a 'high' logic state.
[0070] According to the setpoint voltage Vc of a value equal to 1.0 Volt, only the binary output signal SS
_{12} of order 12 of the logic signal processing means 14 provides a signal of belonging of the setpoint voltage Vc to the interval I
_{12} of order 12. As a result, only the electrical switch SW
_{12} of order 12 is switched on or closed, so that the input signal of the electrical switch SW
_{12} of order 12 is switched on the output of the electrical switch SW
_{12} of order 12.
[0071] According to the embodiment of Figure 3, each input of each electrical switch SW
_{1}, SW
_{24} of order 1 to 24 is electrically connected respectively to a reference voltage V
_{24}, V
_{1} of opposite order 24 to 1. In other words, the input of the electrical switch of order 1 is connected to the reference voltage of order 24, the input of the electrical switch SW
_{1} of order 1 is connected to the reference voltage V
_{24} of order 24, and so on up to the input of the electrical switch SW
_{24} of order 24 connected to the reference voltage of order 1, so that the product of the reference voltage of each comparator C
_{1}, C
_{24} of order 1 to 24 by respectively each reference voltage V
_{24}, V
_{1} of the input signal of each electrical switch SW
_{1}, SW
_{24} of order 1 to 24 is constant and representative of the maximum reference power (Pref), namely 1 Watt.
[0072] According to Figure 3, the setpoint voltage of a value equal to 1.0 Volt belongs to the interval I
_{12} of reference voltage of order 12 bounded by the reference voltage V
_{12} of order 12 of a value equal to 0.96 Volt and by the reference voltage V
_{13} of order 13 of a value equal to 1.06 Volt. The lower bound of the interval I
_{12} of order 12 is the reference voltage V
_{12} of the comparator C
_{12} of order 12. The input signal of the electrical switch SW
_{12} of order 12 is therefore connected to the reference voltage V
_{13} of order 13. The order of the reference voltage V
_{13} of the input signal of the switch SW
_{12} of order 12 and the order of the reference voltage V
_{12} of the comparator C
_{12} of order 12 are two terms of the geometric sequence of the plurality of reference voltages equidistant from the ends of the sequence of order 24. Indeed, the reference voltage V
_{12} of order 12 is at a distance of 12 from the reference voltage V
_{24} of order 24, the reference voltage V
_{24} of order 24 representing the upper end of the geometric sequence, the reference voltage V
_{13} of order 13 being at a distance of 12 from the reference voltage V
_{1} of order 1, the reference voltage V
_{1} of order 1 representing the low end of the geometric sequence.
[0073] Consequently, according to the setpoint voltage of a value equal to 1.0 Volt, the electrical switch SW
_{12} of order 12 provides an electrical threshold for detecting Sth an electric power failure of absolute value equivalent to the reference voltage V
_{13} of order 13, namely 1.06. The product of the reference voltage V
_{12} of order 12, corresponding to a first term of the geometric sequence, by the reference voltage V
_{13} of order 13 representing a second term of the geometric sequence is therefore 0.96 x 1.06, namely a value equal to 1.0 comparable to the predetermined maximum reference power of 1 W.
[0074] According to the embodiments of Figures 1, 2 and 3, the invention also comprises a method for determining 100 an electrical threshold for detecting Sth an electric power failure consumed by an electric charge, preferably an electric charge of a motor vehicle. The method 100 comprises a first step of determining 110 the maximum reference power (Pref) representative of the allowable maximum power of the electric charge. The step of determining 110 the maximum reference power allows dimensioning the geometric sequence of reference signals such that the product of two terms equidistant from the ends of the geometric sequence is equivalent to the reference power.
[0075] A second step 120 of the method 100 consists in providing a plurality of reference signals SR
_{1}, SR
_{N} of increasing values according to a geometric sequence for which the product of two equidistant order terms at both ends of the sequence equals the maximum reference power (Pref); the plurality of reference signals SR
_{1}, SR
_{N} being representative of the variation of a supply signal of the electric charge.
[0076] The plurality of reference signals SR
_{1}, SR
_{N} allows among others framing a setpoint signal Sc representative of the power supply of the electric charge by two successive values of reference signals SR
_{1}, SR
_{2} so as to be able to approximate the setpoint signal Sc to a reference signal SR
_{1}.
[0077] As a result, the method comprises a third step of defining 130 a plurality of successive intervals I
_{1}, I
_{N-1} successively bounded by the terms of the geometric sequence of the plurality of reference signals SR
_{1}, SR
_{N} and also a fourth step of providing 140 the setpoint signal Sc representative of the supply signal of the electric charge.
[0078] To frame the setpoint signal, the method comprises a fifth step of allocating 150 to the setpoint signal Sc a first term of the geometric sequence of an interval I
_{1} of reference signals framing as close as possible the value of the setpoint signal Sc.
[0079] Finally, in order to be able to provide the electrical threshold for detecting an electric power failure, the method comprises a sixth step of allocating 160 to the electrical threshold for detecting Sth a failure of electric power consumed by the electric charge a second term of the geometric sequence of reference signals such that the first term and the second term are of equidistant order at both ends of the sequence.