(19)
(11)EP 3 671 435 A1

(12)EUROPEAN PATENT APPLICATION

(43)Date of publication:
24.06.2020 Bulletin 2020/26

(21)Application number: 18306756.0

(22)Date of filing:  20.12.2018
(51)International Patent Classification (IPC): 
G06F 7/58(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(71)Applicant: Secure-IC SAS
35510 Cesson-Sévigné (FR)

(72)Inventor:
  • DAFALI, Rachid
    35131 CHARTRES-DE-BRETAGNE (FR)

(74)Representative: Hnich-Gasri, Naïma 
Marks & Clerk France Immeuble Visium 22, avenue Aristide Briand
94117 Arcueil Cedex
94117 Arcueil Cedex (FR)

  


(54)METHODS AND DEVICES FOR RANDOM NUMBER GENERATION


(57) A bit generator (11) for generating random bits in a True Random Number Generator, the bit generator (11) comprising one or more RS-latch circuits (40), each RS-latch circuit (40) being configured to generate random bits, each RS-latch circuit (40) comprising a first NAND gate (401), a second NAND gate (402), a first input buffer (403), a second input buffer (404), a first output buffer (405), and a second output buffer (406), the first NAND gate (401) being connected to the first input buffer (403) via a first input wire (407) and being connected to the first output buffer (405) via a first output wire (411), an output of the first NAND gate (401) providing the generated random bits and being fed back to the second NAND gate (402) via a first feedback wire, an output of the second NAND gate (402) being fed back to the first NAND gate (401) via a second feedback wire. The first feedback wire comprises a first vertical wire (409) routed vertically on a second metallic layer and a first horizontal wire (410), routed horizontally on a third metallic layer. The second feedback wire comprises a second vertical wire (412) routed vertically on the second metallic layer and a second horizontal wire (411) routed horizontally on the third metallic layer.




Description

TECHNICAL FIELD



[0001] The invention generally relates to true random number generators.

BACKGROUND



[0002] Random Number Generators are widely used generate a set of random numbers which are needed by a system or device in various application fields such as for example to perform system validation by Monte Carlo simulations, to emulate channels for digital communications, or in security/cryptographic protocols, functions or algorithms which require randomness.

[0003] Specifically, in the field of cryptography, random numbers are used to generate secret keys and/or other parameters needed by symmetric-key/public-key cryptographic protocols or algorithms such as the Advanced Encryption Standard (AES) and the Elliptic Curve Digital Signature Algorithm (ECDSA). Such cryptographic protocols and algorithms are implemented in different types of systems or devices (e.g. embedded devices, smart-cards, smart-phones, Internet of Thing devices, etc.) in order to protect data, to secure communications, and/or to ensure users identification or authentication.

[0004] A random number generator forms a major component in hardware cryptography since it generates the cryptographic secret keys and nonce used by countermeasures and protections. The security of cryptographic key-based systems and devices depends strongly on the quality of the random number generator. High-quality random number generators are required to provide unpredictable randomness with high entropy and to generate high-quality random numbers regardless of environmental changes (e.g. temperature, voltage, etc) that can be intentionally exploited by attackers to produce bias or faults on the generated random numbers.

[0005] As defined in "NIST, Special Publication 800-22, A statistical test suite for random and pseudorandom number generators for cryptographic applications, 2010":
  • randomness refers to the property according to which all the elements of a sequence of random numbers are generated independently of each other, and the value of the next element in the sequence cannot be predicted, and
  • unpredictability refers to the property according to which each element of a random numbers sequence should appear to be the outcome of an independent random event.


[0006] Random numbers having a low randomness will generate weak secret keys, which, makes specific ciphers behave in some undesirable way. Predictable random numbers can be guessed by attackers and eavesdroppers using models, which affects the security of the cryptographic systems/devices implementing random number generators for cryptographic key generation.

[0007] Random number generators comprise random number generators of a first type which are non-deterministic and output a sequence of binary vectors which are statistically independent and unbiased, such as:
  • True Random Number Generators (TRNGs),
  • Non-Deterministic Random Bit Generators (NRBGs),
  • Physical True Random Number Generators (PTRNGs), and
  • Non-Physical True Random Number Generators (NPTRNGs).


[0008] Random number generators comprise random number generators of a second type which are deterministic and produce random numbers based on a seed generated by a TRNG and the internal current state, such as:
  • Pseudo Random Number Generators (PRNGs),
  • Deterministic Random Number Generators (DRNGs), and
  • Deterministic Random Bit Generators (DRBGs).


[0009] TRNGs generate unpredictable random numbers by exploiting a physical source of randomness, also known as 'entropy source', which is based on an unpredictable physical phenomenon. DRNGs generate random sequences by using one or more inputs known as 'random seeds' and a deterministic algorithm.

[0010] Figure 1 is a block diagram representing a structure of a TRNG 1 according to the prior art. A conventional TRNG 1 comprises three main blocks:
  • an entropy source 11 (also referred to as a 'bit generator') which can be a component, a device, or an event that generates an unpredictable, statistically independent, and uniformly distributed bit-stream (raw),
  • a conditioning unit 13 configured to reduce the bias of the raw bits produced by the entropy source 11, and
  • a failures test unit 15 configured to, continuously, check the failures of the entropy source and output an alarm signal when a failure is detected.


[0011] The entropy source is an element that provides, after a digitization process, a bit-stream (Raw) which must be unpredictable, statistically independent and informally distributed. The entropy sources are often based on microscopic physical phenomena such as quantum mechanics and thermal noise. The entropy source is based on the use of electronic noise in semiconductors. The output of an integrated CMOS gate is affected by different noise components as thermal noise and shot noise which are intrinsic.

[0012] Thermal noise is caused by random motion of electrons in any resistive element due to thermal agitation as disclosed in "John Bertrand Johnson, Thermal agitation of electricity in conductors, Physical review, Volume 32, Issue 1, page 97, 1928". The thermal noise is chaotic and non deterministic.

[0013] A shot noise refers to the random fluctuations in the electrical current due to the electron discreteness and the stochastic nature of its flowing through the conductor, as disclosed in "W. Schottky, About spontaneous current variations in different electricity conductors, Annals of physics, Volume 362, pages 541-567, 1918". It is fundamentally non-deterministic and it occurs when charge carriers pass through a potential barrier such as a diode junction in MOS transistors.

[0014] The majority of the digital TRNG uses jittered oscillator sampling as an entropy source as disclosed for example in "RC Fairfield, RL Mortenson, KB Coulthart, An LSI Random Number Generator (RNG), in Proceedings of CRYPTO 84 on Advances in Cryptology, pages 203-230, 1985" and in "V Fischer, M Drutarovsk, True Random Number Generator Embedded in Reconfigurable Hardware, in Cryptographic Hardware and Embedded Systems-CHES, Volume 2523, pages 415-430, 2002". The jittered oscillator TRNGs use the jitter of a clock oscillator or the jitter of a ring oscillator as an entropy source. Using the former approach, random numbers are produced by sampling a high-frequency clock with a low-frequency clock by using a D-type flip-flip (DFF). Using the later approach, random numbers are produced by applying an exclusive-OR (XOR) operation to the outputs of multiple ring oscillators.

[0015] The jittered oscillator TRNG are not protected from external influences. An attacker can thus manipulate the randomness by injecting suitable electromagnetic waves to influence the frequency of the oscillators.

[0016] The metastable-based TRNGs exploit the metastability phenomenon, i.e. the voltage drift phenomenon around the half of the voltage level, to generate random bits. One approach uses the metastability of latches that occurs when the clock signal changes within a narrow window. The metastability window can vary with changes in the device voltage, the device temperature, and the fluctuations of the electrical noise.

[0017] Figure 2 is a schematic representation of a set-reset latch (also referred to as 'RS-latch' or 'SR-latch') constructed using a pair of cross-coupled NAND logic gates. The RS-latch accordingly comprises two NAND gates 24 and 25 and buffer gates 20, 22, 26, and 27. The RS-latch receives a clock signal that is input to the NAND gate 24 and the NAND gate 25, and generates one bit of information labeled Q. The NAND gates are wired, using feedback wires 28 and 29, such that the output of the NAND gate 24 feeds back the input of the NAND gate 25 via the feedback wire 28 and the output of the NAND gate 25 feeds back the input of the NAND gate 24 via the feedback wire 29. When the clock signal is low, i.e. the logic input value is equal to '0', the RS latch is stable with output value Q='1'. When the clock signal is high, i.e. the logic input value changes from '0' to '1', the latch enters a metastable state which will resume in a random stable rate. By placing the latch on a metastable state, random numbers can be obtained from the output value Q by giving input clock signals, the final stable sate '0' or '1' obtained according to the value of the noise voltage introduced during the metastable state producing the random values.

[0018] Each wire in the latch design has a resistance and a capacitance. The routing rules for routing the signals and data carried by the wires depend on the resistance and capacitance of the wires. In particular, parasitic effects such as parasitic capacitance and parasitic resistance due to the proximity of the wires and/or the gates can cause crosstalk and extra signal propagation delay.

[0019] Several designs of RS-latches have been proposed using ideal RS-latches and automatic RS-latches. An exemplary implementation of metastability-based TRNGs on a Field Programmable Gate Array (FPGA) is disclosed in "H. Hata and S. Ichikawa, FPGA Implementation of Metastability-Based True Random Number Generator, IEICE Transactions on Information Systems, E95-D, Issue 2, pages 426-436, 2012".

[0020] Ideal RS-latches do not include the resistance-capacitance parasitic extracted from the wires especially for the feedback wires. Automatic RS-latches are located and routed automatically and never reach the metastability zone. Further, due to the difference in wiring delay between the gates and the difference of drive capability between the NAND gates, the output values are biased and the RS-latch generally generates only '0's or only '1's. In order to reduce the bias introduced by the routing of the feedback wires, a delay is added between the input signals s_i and r_i respectively input to the NAND gate 24 and the NAND gate 25. Such a design is referred to as a delay chain-based RS-latch. The introduced delay chain enable resolving the bias. However, it is very complicated to design and to calibrate and is sensitive to the environmental changes.

[0021] Metastability-based TRNGs produce high-quality random numbers, consume low power, and require a small scale. However, the design of such random number generators still face difficulties for placing latches on a metastable state and defining how many latches are required to reach a target source entropy.

[0022] There is accordingly a need for improved TNRGs forming secure sources of entropy that are independent, protected from external influence (such as physical and hardware attacks), and efficient in terms of providing high-quality random numbers.

SUMMARY



[0023] In order to address these and other problems, there is provided a bit generator for generating random bits in a True Random Number Generator, the bit generator comprising one or more RS-latch circuits, each RS-latch circuit being configured to generate random bits, each RS-latch circuit comprising a first NAND gate, a second NAND gate, a first input buffer, a second input buffer, a first output buffer, and a second output buffer, the first NAND gate being connected to the first input buffer via a first input wire and being connected to the first output buffer via a first output wire, an output of the first NAND gate providing the generated random bits and being fed back to the second NAND gate via a first feedback wire, an output of the second NAND gate being fed back to the first NAND gate via a second feedback wire. The first feedback wire may comprise a first vertical wire routed vertically on a second metallic layer and a first horizontal wire, routed horizontally on a third metallic layer. The second feedback wire may comprise a second vertical wire routed vertically on the second metallic layer and a second horizontal wire routed horizontally on the third metallic layer.

[0024] According to some embodiments, the first NAND gate may be positioned at a given position within the latch circuit and the second NAND gate may be positioned at a second position, the second position being determined from the position of the first NAND gate, the second NAND gate being rotated using a 180 degree counterclockwise rotation around a fixed rotation axis.

[0025] According to some embodiments, the first input buffer may be positioned at the right of the first NAND gate, the first input buffer and the first NAND gate being arranged side-by-side. The second input buffer may be positioned at the right of the first NAND gate and rotated using a 180 degree counterclockwise rotation around the rotation axis, the second input buffer and the first NAND gate being arranged side-by-side.

[0026] According to some embodiments, the first output buffer may be arranged at the left side of the latch circuit face to the first NAND gate, with a predetermined space between the first output buffer and the first NAND gate.

[0027] According to some embodiments, the first output wire may connect an output port of the first NAND gate to an input port of the first output buffer, the input port of the first output buffer being positioned face to the output port of the first NAND gate, the routing of the first and the second feedback wires being arranged in the predetermined space between the first output buffer and the first NAND gate, the predetermined space being dependent on the length of the first vertical wire and of the length of the first horizontal wire.

[0028] According to some embodiments, the second output buffer may be arranged at a distance of the first output buffer and rotated using a 180 degree counterclockwise rotation around the rotation axis.

[0029] According to some embodiments, the second NAND gate may be connected to the second input buffer via a second input wire and to the second output buffer via a second output wire.

[0030] According to some embodiments, the first input wire and the second input wire may have a same wire length and may be routed using a wire of a first metallic layer.

[0031] According to some embodiments, the wire length of the first input wire and of the second input wire may be determined depending on the wire resistance parasitics and wire capacitance parasitics associated with the first input wire and the second input wire.

[0032] According to some embodiments, the first input wire may connect an output port of the first input buffer to an input port of the first NAND gate, the output port of the first input buffer being arranged close to the input port of the first NAND gate so as to minimize of the length of the first input wire.

[0033] According to some embodiments, the first feedback wire and the second feedback wire may be identical, the first vertical wire and the second vertical wire having a same length, and the first horizontal wire and the second horizontal wire having a same length.

[0034] According to some embodiments, the number of latches may be previously determined according to a target source entropy.

[0035] According to some embodiments, the first input buffer and the second input buffer may be configured to simultaneously receive a clock signal.

[0036] According to some embodiments, the one or more RS-latch circuits may be configured to receive a clock signal at the same time, the first input buffer and the second input buffer of each of the one or more RS-latch circuits being configured to simultaneously receive the clock signal.

[0037] There is also provided a cryptographic system for generating one or more cryptographic keys, the cryptographic system comprising a bit generator of a true number generator for generating random bits according to any preceding feature, the cryptographic system comprising a key generator for generating one or more cryptographic keys using the generated random bits.

[0038] The embodiments of the invention provide high-quality and high performing TRNGs capable of producing unbiased random numbers that are compliant with statistical tests.

[0039] Advantageously, the TRNGs according to the embodiments of the invention are resilient to hardware attacks such as EM injection attacks.

[0040] Further, the arrangement and routing rules according to the embodiments of the invention provide efficient sources of entropy for TRNGs based on RS-latches capable of producing random numbers for a target, desired or specified entropy. The arrangement and routing rules enable further reducing the parasitic resistance and capacitance between the components/elements of the RS-latch and the wires connecting these components, thus reducing the power consumption.

[0041] Advantageously, the design of RS-latches according to the embodiments of the invention is independent from the delay chain and the environmental changes or variations including the device temperature variation, the changes on the clock frequency, and/or the load feeding the TRNG. The output of the proposed RS-latches then depends only on the intrinsic noise.

[0042] The design of TRNGs according to the embodiments of the invention is easy to implement and does not require the validation of the test-chip. Such designs enable further reducing the number of defective TRNG circuits.

[0043] It is another advantage of the TRNGs according to the embodiments of the invention to reduce the latency of circuit startup. The entropy source does not need to accumulate the randomness trough a long time and the first generated bits can be used.

[0044] Advantageously, the various embodiments of the invention provide efficient techniques for reinforcing the security and protection of cryptographic devices by increasing the difficulty of reverse-engineering aiming at extracting cryptographic keys.

[0045] Further advantages of the present invention will become clear to the skilled person upon examination of the drawings and the detailed description, provided for illustration purposes only.

BRIEF DESCRIPTION OF THE DRAWINGS



[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention, together with the general description of the invention given above and the detailed description of the embodiments given below.

Figure 1 is a block diagram illustrating the structure of a True Random Number Generator of the prior art;

Figure 2 represents an RS-latch of the prior art;

Figure 3 is a block diagram illustrating an exemplary application of a TRNG, according to some embodiments of the invention;

Figure 4 is a circuit layout illustrating an RS-latch-based source of entropy of a TRNG, according to some embodiments of the invention;

Figure 5 is a circuit layout illustrating a source of entropy based on a plurality of RS-latches;

Figure 6 is a flowchart illustrating a method for generating random values, according to some embodiments of the invention using one or more routed and placed RS-latch circuits.


DETAILED DESCRIPTION



[0047] Embodiments of the invention provide devices and methods for efficient, secure, and high-quality generation of random numbers in True Random Number Generators. More specifically, the devices and methods according to the various embodiments of the invention provide improved arrangement and wires routing rules for the design of RS-latches based sources of entropy, the arrangement and routing providing sources of entropy that are resilient to physical attacks and environmental changes and are capable of producing random bits according to a target source entropy.

[0048] The sources of entropy provided according to the embodiments of the invention may be implemented in any True Random Number Generator for generating random values. A True Random Number Generator according to the embodiments of the invention may be used in many types of applications such as:
  • in simulation and modeling of complex phenomena: e.g. in Monte Carlo integration used in finance and in engineering fields;
  • in random sampling for the selection of random samples from larger data sets;
  • in games, lottery, and gambling systems for users authentication and signing, encryption, digital signature of documents and transactions, authenticity of contents, database encryption to ensure a secure storage of users, accounts, and transactions data;
  • in Information Technology security applications and cryptographic protocols and algorithms for generating secret/private/shared data encryption keys used in symmetric and public-key crypto-systems, generating initialization vectors, padding, seeding messages and passwords, and in internet encryption protocols such as secure socket layer (SSL);
  • in chip manufacturing and seeding of device-specific keys, e.g. for Near Field Communication or device IDs;
  • In machine learning and statistical learning, true random number generators may be used to obtain samples from random distributions (e.g. Gamma, Beta).


[0049] In cryptographic applications, True Random Numbers Generators according to the various embodiments of the invention may be implemented in cryptographic devices and/or systems that implement cryptographic functions based on one or more cryptographic keys to ensure data and/or signals security, authentication, protection, and privacy. Exemplary cryptographic devices comprise:
  • smart cards, tokens to store keys such as wallets, smart cards readers such as Automated Teller Machines (ATM) used for example in financial transactions, restricted accesses, telecommunications, military applications, secure communication equipments, and TV set-top boxes;
  • electrical and digital electronic devices such as RFID tags and electronic keys;
  • embedded secure elements;
  • computers (e.g. desktop computers and laptops), tablets;
  • routers, switches, printers;
  • mobile phones such as smart-phones, base stations, relay stations, satellites;
  • Internet of Thing (loT) devices, robots, drones; and
  • recorders, multimedia players, mobile storage devices (e.g. memory cards and hard discs) with logon access monitored by cryptographic mechanisms.


[0050] Exemplary cryptographic systems comprise:
  • communication systems (e.g. digital wired, wireless, cellular/radio, optical, satellite, acoustic, and molecular communication and transmission systems) in which key-based cryptographic functions are used for ensuring a secure transfer of data over unsecure transmission channels and are used in user equipments such as in mobile phones and smart-phones to authenticate the control and access to batteries and accessories;
  • computing networks/systems in which secret keys may be used for securing data center interconnections;
  • digital data storage (e.g. cloud computing applications and cloud servers);
  • recording systems (e.g. magnetic and optical recording);
  • data processing systems(e.g. databases, online sale systems, financial systems);
  • positioning systems;
  • digital television and video broadcasting systems;
  • identity systems (e.g. electronic passports, cryptographic identity documents);
  • transportation and automotive devices (e.g. autonomous cars, connected cars, inertial guidance systems, GPS receivers, motor controllers, electric and hybrid vehicles to ensure anti-theft protection);
  • service provider systems to provide restricted and authorized accesses;
  • banking systems to secure banking accounts and financial transactions;
  • medical device to secure medical data and medical devices such as implantable medical devices which can be implanted within the body to treat a medical condition or to monitor the state of the functioning of some body parts (e.g. pacemakers, defibrillators to monitor and treat cardiac conditions, brain monitoring or stimulation devices such as neuro-stimulators for deep brain stimulation in cases such as epilepsy or Parkinson, drug delivery systems, biosensors); or
  • in digital electronic systems for securing hardware modules and electronic components embedded for example in smart-cards or electrical vehicles.


[0051] Referring to figure 3, there is shown an exemplary implementation of a True Random Number Generator 303 in a device 30 implemented in a system 300.

[0052] The system 300 may be for example a communication system (e.g. digital, wired, wireless, cellular, optical, satellite, acoustic, and molecular communication system), a data processing system (e.g., online sale systems, financial systems, electronic passport systems, banking), a data storage system (e.g. databases), a recording system (e.g. magnetic and optical recording), a positioning system, etc.

[0053] The device 30 may be any integrated circuit device, computer, computing machine, or embedded system, programmed and/or programmable (e.g. a Field Programmable Gate Array circuit, an Application Specific Integrated Circuit, a system on chip, a Very-Large Scale Integration integrated circuit) to implement a True Random Number Generator for generating random values/numbers. The device 30 may be a system on chip that integrates on a single integrated circuit all the components of a computing machine or computer including a central processing unit, memory means, and input/output peripherals/ports.

[0054] In an application of the invention to a communication system, the device 30 may be fixed or mobile, configured to operate in a wired, wireless, or optical fiber-based communication network. The device 30 may be a standalone device or may be connected to external devices, machines or systems. The device 300 may be implemented for example in a computer networking system (using for example one or more small or large area wired or wireless access networks).

[0055] The True Random Number Generator 303 may be any physical component/device or integrated circuit configured to generate random numbers. The True Random Number Generator 303 may further generate alarm signals in case of failures of the source of entropy detected by a failures test unit implemented in the TRNG 303 (the failures test unit is not shown in figure 1).

[0056] As shown in figure 3, the device 30 may comprise a TRNG control unit 301 configured to generate clock signals and to send out the clock signals on a regular basis to the True Random Number Generator 303 and all other components of the device 30. The TRNG control unit 301 may be configured to stop the clock signal input to the TRNG 303 for saving power consumption when random numbers generation is not required.

[0057] The TRNG control unit 301 may be further configured to set or to store the failures test(s) to be performed by the failures test unit to test the output sequence of the TRNG 303 online, i.e. during the operation of the TRNG 303. The TRNG control unit 301 may be configured to send one or more failures tests to the TRNG 303 at the TRNG reset and then continuously, periodically at specified regular time intervals, or permanently.

[0058] The failures tests may be statistical tests performed to measure the entropy per bit of the TRNG 303 and to check if the output of the TRNG 303 is stuck outputting periodically the same numbers or long sequences of zero-value bits ('0') or one-value bits ('1'). The failures tests may be previously fixed/determined/selected according to the level of security required (for example from certification standards or depending on the application).

[0059] The TRNG control unit 301 may be further configured to receive the alarm signals generated by the TRNG 303 in order to perform one or more control actions depending on the alarm signals.

[0060] The random numbers generated by the TRNG 303 may be sent to a data processing unit 305 (e.g. a processor) for a further use for example for generating cryptographic keys. The random numbers may be stored inside a security module e.g. a Hardware Security Module prior to their usage.

[0061] The embodiments of the invention are related to metastability-based True Random Number Generators in which the source of entropy takes advantage of the metastability behavior of RS-latches in order to generate random bits. More specifically, the embodiments of the invention provide an arrangement of RS-latches used in a source of entropy. In such arrangement, the components of RS-latch circuits are arranged and interconnected via wires according to specific routing rules that enable advantageously reducing the resistance and capacitance parasitic and achieving a target source entropy rate.

[0062] Referring to figure 4, there is shown an entropy source for producing random bits in a True Random Number Generator 303. The entropy source comprises one or more RS-latch circuits 40. Each RS-latch circuit 40 is configured to receive the clock signal sent from the TRNG control unit 301 to the True Random Number Generator 303 and to generate random bits. Each RS-latch circuit 40 may comprise:
  • a first NAND gate 401;
  • a second NAND gate 402;
  • a first input buffer 403;
  • a second input buffer 404;
  • a first output buffer 405; and
  • a second output buffer 406.


[0063] The first input buffer 403 and the second input buffer 404 are configured to simultaneously receive the clock signal sent from the TRNG control unit 301 to the True Random Number Generator 303.

[0064] The first NAND gate 401 is connected to the first input buffer 403 via a first input wire 407 and is connected to the first output buffer 405 via a first output wire 411. The output of the first NAND gate 401 produces random bits stored bit-by-bit in the first output buffer 405 and fed back to the second NAND gate 402 via a first feedback wire 412.

[0065] The second NAND gate 402 is connected to the second input buffer 404 via a second input wire 408 and is connected to the second output buffer 406 via a second output wire 410. The output of the second NAND gate 402 is fed back to the first NAND gate 401 via a second feedback wire 409.

[0066] According to the embodiments of the invention, the arrangement of the different gates and buffers and the routing of the interconnect wires connecting the gates and the buffers are performed such that, in each RS-latch circuit 40, the first NAND gate 401 is positioned at a given position within the RS-latch circuit 40. Then, the second NAND gate 402 is positioned at a second position, the second position being determined by arranging the second NAND gate 402 at the given position of the first NAND gate 401 and then rotating the second NAND gate 402 using a 180 degree counterclockwise rotation around a fixed rotation axis represented by the origin 400 such that the first NAND gate 401 and the second NAND gate 402 are in axial symmetry around the fixed rotation axis.

[0067] After arranging the first and second NAND gates, the first input buffer 403 is positioned at the right of the first NAND gate 401, the first input buffer 403 and the first NAND gate 401 being arranged side-by-side. The second input buffer 404 is positioned at the right of the first NAND gate 401 and then rotated using a 180 degree counterclockwise rotation around said rotation axis such that the first input buffer 403 and the second input buffer 404 are in axial symmetry around the fixed rotation axis and the second input buffer 404 and the first NAND gate are arranged side-by-side.

[0068] Then, the first output buffer 405 and the second output buffer 406 are arranged. The first output buffer 405 is arranged at the left side of the RS-latch circuit 40 face to the first NAND gate 401 with a predetermined between the first output buffer 405 and the first NAND gate 401. The second output buffer 406 is then arranged at the position of the first output buffer 405 and rotated using a 180 degree counterclockwise rotation around the fixed rotation axis such that the first output buffer 405 and the second output buffer 406 are in axial symmetry around the fixed rotation axis.

[0069] The interconnection of the NAND gates and the buffers is realized using different wires routed on three different metallic layers. More specifically:
  • the first input wire 407 and the second input wire 408 are routed using a wire of a first metallic layer and they have a same predefined first wire length;
  • the first feedback wire is routed using a first vertical wire 409 routed vertically on a second metallic layer and a first horizontal wire 410 routed horizontally on a third metallic layer; and
  • the second feedback wire is routed using a second vertical wire 412 routed vertically on the second metallic layer and a second horizontal wire 411 routed horizontally on the third metallic layer.


[0070] Advantageously, routing the first input wire 407 and the second output wire 408 using a first metallic layer enables reducing the resistance/capacitance parasitics.

[0071] As shown in figure 4, each NAND gate and each buffer has one or more input ports labeled 'I' or 'I1' or '12' and an input port labeled 'O'. More specifically, the first input wire 407 connects the output port of the first input buffer 403 to the input port 'I1' of the first NAND gate 401. The arrangement of the first input buffer 403 may be advantageously performed such that the output port of the first input buffer 403 is arranged close to the input port of the first NAND gate 401 in a way that the routing wire, i.e. the first input wire 407, connecting them has a minimum length, i.e. so as to minimize length of the first input wire 407.

[0072] Further, the first output wire 411 connects the output port 'O' of the first NAND gate 401 to the input port 'I' of the first output buffer 405. In some embodiments, the input port 'I' of the first output buffer 405 may be arranged facing the output port 'O' of the first NAND gate 401 such that the predetermined space between the first output buffer 405 and the first NAND gate 401 is used to route the first feedback wire and the second feedback wire, the predetermined space being previously determined depending on the lengths of the first vertical wire 409 and the length of the first horizontal wire 410, both used to route the first feedback wire.

[0073] According to some embodiments, the first feedback wires 411 and 412 and the second feedback wires 409 and 410 must be identical to get a metastable state, i.e. to arrange the RS-latch circuit 40 in a metastable state. Identical wires means that the first feedback wire and the second feedback wire are required to have: 1) same points of connections with the input/output ports, 2) same lengths of the first vertical wire 409 and the second vertical wire 412 used at the routing on the second layer, and 3) same lengths of the first horizontal wire 410 and the second horizontal wire 411 used at the routing on the third layer.

[0074] According to some embodiments, the predefined first wire length of the first input wire 407 and the second input wire 408 may be previously determined according to the reduction of wire resistance parasitics and wire capacitance parasitics associated with the first input wire 407 and the second input wire 408.

[0075] According to some embodiments in which the entropy source implements one or more RS-latch circuits 40, the number of the one or more RS-latch circuits 40 may be previously determined according to a target source entropy rate such that the entropy source using the determined number of RS-latch circuits 40 achieves the target source entropy rate.

[0076] Referring to figure 5, there is shown an entropy source comprising a plurality (two or more) of RS-latch circuits 51-n with n = 1, ...., N and N ≥ 2 designating the number of RS-latch circuits used. In such embodiments, the entropy source may further comprise a random numbers combination unit 53 configured to combine the random bits generated by each of the two or more RS-latch circuits 51-n by applying an exclusive OR operation, which provides the random bits to be generated by the True Random Number Generator 303.

[0077] According to some embodiments in which the entropy source comprises two more RS-latch circuits 40, the RS-latch circuits may be configured to receive the clock signal at the same time, i.e. each first input buffer 403 and second input buffer 404 of each of the two or more RS-latch circuits 40 simultaneously receive the clock signal.

[0078] According to some embodiments, the random bits generated by the source entropy may be used to generate one or more cryptographic keys to be used for example for data and/or signal encryption and/or decryption, for message authentication, in digital signatures, or for ensuring data and/or signals security and privacy. The one or more cryptographic keys may be used in key-based encryption algorithms comprising symmetric encryption algorithms (e.g. DES (Data Encryption Standard), 3DES, AES (Advanced Encryption Standard), and RC4 (Rivest Cipher 4)) and asymmetric encryption algorithms (e.g. RSA (Rivest-Shamir-Adleman) and ECDSA (Elliptic Curve Digital Signature Algorithm)). The random bits may be alternatively used to determine one or more secret values such as passwords to be stored in the device 30 and/or shared between the device 30 and one or more external devices/machines/users connected to the system 300.

[0079] Referring to figure 6, there is also provided a method for producing random bits in an entropy source of a True Random Number Generator, the entropy source exploiting the metastability behavior of one or more RS-latch circuits to generate random bits. Each RS-latch circuit is configured to generate random bits and comprises a first NAND gate, a second NAND gate, a first input buffer, a second input buffer, a first output buffer, and a second output buffer, the first NAND gate being connected to the first input buffer via a first input wire and being connected to the first output buffer via a first output wire. The output of the first NAND gate produces random bits and the produced random bits are fed, a bit per clock signal, back to the second NAND gate via a first feedback wire. The second NAND gate is connected to the second input buffer via a second input wire and is connected to the second output buffer via a second output wire. The output of the second NAND gate is fed back to the first NAND gate via a second feedback wire. The method provides arrangement of the NAND gates and the input and output buffers as well as a routing of the wires interconnecting the different NAND gates and the input/output buffers in a way that the random bits are generated with a high randomness level, satisfying a target source entropy rate, while being secured and protected against any external attacks (hardware attacks) and any environmental changes (e.g. temperature, voltage).

[0080] At step 601, the first NAND gate may be arranged at a given position within an RS-latch circuit.

[0081] At step 603, the second NAND gate may be arranged at a second position, the second position being determined by arranging the second NAND gate at the given position on which is arranged the first NAND gate and rotating the second NAND gate using a 180 degree counterclockwise rotation around a fixed rotation axis.

[0082] At step 605, the first input buffer may be arranged side-by-side on the right of the first NAND gate.

[0083] At step 607, the second input buffer may be arranged side-by-side on the right of the first NAND gate then rotated using a 180 degree counterclockwise rotation around the fixed rotation axis.

[0084] At step 609, the first output buffer may be arranged on the left side of the RS- latch circuit facing the first NAND gate, a predefined space being left between the first output buffer and the first NAND gate.

[0085] At step 611, the second output buffer may be arranged at the position of the first output buffer then rotated using a 180 degree counterclockwise rotation around the fixed rotation axis.

[0086] At step 613, the first input wire and the second input wire may be routed using wires of a first metallic layer, the first input wire and the second input wire having a same predefined first wire length.

[0087] At step 615, the first feedback wire may be routed using a first vertical wire routed vertically on a second metallic layer and a first horizontal wire routed horizontally on a third metallic layer.

[0088] At step 617, the second feedback wire may be routed using a second vertical wire routed vertically on the second metallic layer and a second horizontal wire routed horizontally on the third metallic layer.

[0089] While embodiments of the invention have been illustrated by a description of various examples, and while these embodiments have been described in considerable details, it is not the intent of the applicant to restrict or in any way limit the scope of the appended claims to such embodiments. Some of those embodiments may be advantageously combined, when appropriate. Additional advantages and modifications will readily appear to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative methods, and illustrative examples shown and described.


Claims

1. A bit generator (11) for generating random bits in a True Random Number Generator, the bit generator (11) comprising one or more RS-latch circuits (40), each RS-latch circuit (40) being configured to generate random bits, each RS-latch circuit (40) comprising a first NAND gate (401), a second NAND gate (402), a first input buffer (403), a second input buffer (404), a first output buffer (405), and a second output buffer (406), the first NAND gate (401) being connected to the first input buffer (403) via a first input wire (407) and being connected to the first output buffer (405) via a first output wire (411), an output of the first NAND gate (401) providing said generated random bits and being fed back to the second NAND gate (402) via a first feedback wire, an output of the second NAND gate (402) being fed back to the first NAND gate (401) via a second feedback wire, wherein:

- the first feedback wire comprising a first vertical wire (409) routed vertically on a second metallic layer and a first horizontal wire (410), routed horizontally on a third metallic layer, and

- the second feedback wire comprises a second vertical wire (412) routed vertically on said second metallic layer and a second horizontal wire (411) routed horizontally on said third metallic layer.


 
2. The bit generator (11) of claim 1, wherein the first NAND gate (401) is positioned at a given position within said latch circuit (40) and the second NAND gate (402) is positioned at a second position, said second position being determined from the position of the first NAND gate (402), the second NAND gate (402) being rotated using a 180 degree counterclockwise rotation around a fixed rotation axis.
 
3. The bit generator (11) of any preceding claim 1 and 2, wherein the first input buffer (403) is positioned at the right of the first NAND gate (401), the first input buffer (403) and the first NAND gate (401) being arranged side-by-side, and wherein the second input buffer (404) is positioned at the right of the first NAND gate (401) and rotated using a 180 degree counterclockwise rotation around said rotation axis, the second input buffer (404) and the first NAND gate (401) being arranged side-by-side.
 
4. The bit generator (11) of claim 1, wherein the first output buffer (405) is arranged at the left side of the latch circuit (40) face to the first NAND gate (401), with a predetermined space between the first output buffer (405) and the first NAND gate (401).
 
5. The bit generator (11) of claim 4, wherein the first output wire (411) connects an output port of the first NAND gate (401) to an input port of the first output buffer (405), the input port of the first output buffer (405) being positioned face to the output port of the first NAND gate (401), the routing of the first and the second feedback wires being arranged in said predetermined space between the first output buffer (405) and the first NAND gate (401), said predetermined space being dependent on the length of said first vertical wire (409) and of the length of said first horizontal wire (410).
 
6. The bit generator (11) of any preceding claim 4 and 5, wherein the second output buffer (406) is arranged at a distance of said first output buffer (405) and rotated using a 180 degree counterclockwise rotation around said rotation axis.
 
7. The bit generator (11) of any preceding claim, wherein the second NAND gate (402) is connected to the second input buffer (404) via a second input wire (408) and to the second output buffer (406) via a second output wire (410).
 
8. The bit generator (11) of claim 7, wherein the first input wire (407) and the second input wire (408) have a same wire length and are routed using a wire of a first metallic layer.
 
9. The bit generator (11) of claim 8, wherein the wire length of the first input wire (407) and of the second input wire (408) is determined depending on the wire resistance parasitics and wire capacitance parasitics associated with said first input wire (407) and said second input wire (408).
 
10. The bit generator (11) of any preceding claim, wherein the first input wire (407) connects an output port of the first input buffer (403) to an input port of the first NAND gate (401), the output port of the first input buffer (403) being arranged close to the input port of the first NAND gate (401) so as to minimize of the length of the first input wire (407).
 
11. The bit generator (11) of any preceding claim, wherein said first feedback wire and said second feedback wire are identical, the first vertical wire (409) and the second vertical wire (412) having a same length, and the first horizontal wire (410) and the second horizontal wire (411) having a same length.
 
12. The bit generator (11) of any preceding claim, wherein the number of latches is previously determined according to a target source entropy.
 
13. The bit generator (11) of any preceding claim, wherein the first input buffer (403) and the second input buffer (404) are configured to simultaneously receive a clock signal.
 
14. The bit generator (11) of any preceding claim, wherein the one or more RS-latch circuits (40) are configured to receive a clock signal at the same time, the first input buffer (403) and the second input buffer (404) of each of the one or more RS-latch circuits (40) being configured to simultaneously receive said clock signal.
 
15. A cryptographic system for generating one or more cryptographic keys, wherein the cryptographic system comprises a bit generator (11) of a true number generator for generating random bits according to any preceding claim 1 to 14, the cryptographic system comprising a key generator for generating one or more cryptographic keys using said generated random bits.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Non-patent literature cited in the description