(19)
(11)EP 3 687 064 A1

(12)EUROPEAN PATENT APPLICATION

(43)Date of publication:
29.07.2020 Bulletin 2020/31

(21)Application number: 19153196.1

(22)Date of filing:  23.01.2019
(51)International Patent Classification (IPC): 
H03C 3/40(2006.01)
H03C 5/00(2006.01)
H04L 27/36(2006.01)
G06F 1/025(2006.01)
H03G 3/30(2006.01)
H03G 3/00(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(71)Applicant: National Chung-Shan Institute of Science and Technology
325 Taoyuan City (TW)

(72)Inventors:
  • Wang, Tao
    325 Taoyuan City (TW)
  • Chou, Hung-Ting
    242 New Taipei City (TW)
  • Yu, Chien-Te
    320 Taoyuan City (TW)
  • Chien, Ching-I
    813 Kaohsiung City (TW)

(74)Representative: Straus, Alexander et al
2K Patent- und Rechtsanwälte - München Keltenring 9
82041 Oberhaching
82041 Oberhaching (DE)

 
Remarks:
Amended claims in accordance with Rule 137(2) EPC.
 


(54)DIGITAL-CONTROLLED VECTOR SIGNAL MODULATOR


(57) A vector modulator includes a quadrature component generator (12), configured to generate an input in-phase signal (Ii) and an input quadrature signal (Qi) according to an input radio frequency (RF) signal (RFin); a switching circuit (14), receiving a plurality of bits (B1,...,BN), comprising a plurality of switches controlled by the plurality of bits, configured to generate an output in-phase signal (Io) and an output quadrature signal (Qo) according to the plurality of bits (B1,...,BN), where the output in-phase signal (Io) and the output quadrature signal (Qo) are related to input in-phase signal (Ii) and the input quadrature signal (Qi); and a combining module (16), configured to generate an output RF signal (RFout) according to the output in-phase signal (Io) and the output quadrature signal (Qo).




Description

Field of the Invention



[0001] The present invention relates to a digital-controlled vector signal modulator, and more particularly, to a vector signal modulator directly controlled by digital signal without digital-to-analog signal conversion.

Background of the Invention



[0002] Electronic systems, such as communication systems and test instruments, use vector signal modulators to generate vector signals that meet the amplitude and phase requirement. In a vector signal modulator, a signal is separated to two signals with different phase degree, i.e., the in-phase (I) and quadrature (Q) signals, first. After then, the amplitudes of the in-phase (I) and quadrature (Q) are modulated, respectively, and finally combined together to generate a vector signal which amplitude and phase both meet requirement. For instance, when the I and Q channels (i.e. signal paths) of the modulator are calibrated to be equal in gain responses, a 45° degree vector signal is generated.

[0003] Conventional vector modulators utilize variable gain amplifiers (VGAs) to adjust the in-phase and the quadrature signals. However, these VGAs use analog signals to control the gain of the VGAs, and therefore digital-to-analog converters (DACs) are required. The need of DAC complicates the design of the vector signal modulator and increases production cost.

Summary of the Invention



[0004] This in mind, the application aims at providing a vector modulator with low complexity, to reduce over disadvantages of the prior art.

[0005] This is achieved by a vector modulator according to claim 1. The dependent claims pertain to corresponding further developments and improvements.

[0006] As will be seen more clearly from the detailed description following below, an embodiment of the present invention discloses a vector modulator comprising a quadrature component generator, configured to generate an input in-phase signal and an input quadrature signal according to an input radio frequency (RF) signal; a switching circuit, receiving a plurality of bits, comprising a plurality of switches controlled by the plurality of bits, configured to generate an output in-phase signal and an output quadrature signal according to the plurality of bits, where the output in-phase signal and the output quadrature signal are related to input in-phase signal and the input quadrature signal; and a combining module, configured to generate an output RF signal according to the output in-phase signal and the output quadrature signal.

Brief Description of the Drawings



[0007] 

FIG. 1 is a schematic diagram of a vector modulator according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a switching circuit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a conduction status of the switching circuit of FIG. 2.

FIG. 4 is a schematic diagram of a switching circuit according to an embodiment of the present invention.


Detailed Description



[0008] The present invention proposes to realize a vector signal modulator directly from the digital control signal without DACs, saving time and the cost the device considerably.

[0009] FIG. 1 is a schematic diagram of a vector modulator 10 according to an embodiment of the present invention. The vector modulator 10 comprises a quadrature component generator 12, an in-phase amplifier I-Amp, a quadrature amplifier Q-Amp, a switching circuit 14 and a combining module 16. Note that, the vector modulator 10 does not include any digital-to-analog converter (DAC). Specifically, the quadrature component generator 12 receives an input radio frequency (RF) signal RFin and generates an input in-phase signal Ii and an input quadrature signal Qi according to the RF signal RFin. The input in-phase signal Ii and the input quadrature signal Qi have 90° phase difference. The in-phase amplifier I-Amp receives the input in-phase signal Ii and generates an intermediate in-phase signal Im; the quadrature amplifier Q-Amp receives the input quadrature signal Qi and generates the intermediate quadrature signal Qm. The switching circuit 14 comprises a plurality of switches (which will be illustrated later on) and receives a plurality of bits B1,...,BN, where the bits B1,...,BN are configured to control an ON-OFF status of the plurality of switches. The switching circuit 14 is configured to adjust the input in-phase signal Ii to generate an output in-phase signal Io, and to adjust the input quadrature signal Qi to generate an output quadrature signal Qo, according to the bits B1,...,BN. The combining module 16 is configured to combine the output in-phase signal Io and the output quadrature signal Qo to generate an output RF signal RFout.

[0010] The signals RFin, Ii, Qi, Im, Qm, Io, Qo and RFout may be voltage signals or current signals. In an embodiment, the signals RFin, Ii, Qi, Im, Qm, Io, Qo and RFout are all differential signals, but not limited thereto. For example, as illustrated in FIG. 1, the RF signal RFin/RFout comprises a positive input/output RF signal RFin+/RFout+ and a negative input/output RF signal RFin-/RFout-, the input/intermediate/output in-phase signal Ii/Im/Io comprises a positive input/intermediate/output in-phase signal Ii+/Im+/Io+ and a negative input/intermediate/output in-phase signal Ii-/Im-/Io-, and the input/intermediate/output quadrature signal Qi/Qm/Qo comprises a positive input/intermediate/output quadrature signal Qi+/Qm+/Qo+ and a negative input/intermediate/output quadrature signal Qi-/Qm-/Qo-.

[0011] The in-phase amplifier I-Amp and the quadrature amplifier Q-Amp are full differential amplifiers. The in-phase amplifier I-Amp comprises a positive in-phase output terminal OI+ and a negative in-phase output terminal OI-. The quadrature amplifier Q-Amp comprises a positive quadrature output terminal OQ+ and a negative quadrature output terminal OQ-.

[0012] In this regard, the combining module 16 may comprise a first combining element CE+ and a second combining element CE-. The first combining element CE+ is configured to generate the positive output RF signal RFout+ by combining the positive output in-phase signal Io+ and the positive output quadrature signal Qo+. The positive output RF signal RFout+ may be expressed as RFout+ = Io+ + j* Qo+. The second combining element CE- is configured to generate the negative output RF signal RFout+ by combining the negative output in-phase signal Io- and the negative output quadrature signal Qo-. The negative output RF signal RFout- may be expressed as RFout- = Io- + j* Qo-.

[0013] FIG. 2 is a schematic diagram of a switching circuit 24 according to an embodiment of the present invention. The switching circuit 24 is an embodiment of the switching circuit 14. The switching circuit 24 comprises a first in-phase switching sub-circuit SWI+ and a first quadrature switching sub-circuit SWQ+. The in-phase switching sub-circuit SWI+ and the quadrature switching sub-circuit SWQ+ have similar circuit structure.

[0014] The first in-phase switching sub-circuit SWI+ comprises a first in-phase switching input terminal NIin+, a second in-phase switching input terminal NIin-, a first in-phase switching output terminal NIout+, a second in-phase switching output terminal NIout-, in-phase conducting switches SI1+, SI0+, SI0-, SI1- and in-phase diverting switches SI1+', SI0+', SI1-', SI0-'. The first in-phase switching input terminal NIin+ of the in-phase switching sub-circuit SWI+ is coupled to the positive in-phase output terminal OI+. The second in-phase switching input terminal NIin- of the in-phase switching sub-circuit SWI+ is coupled to the negative in-phase output terminal OI-. The in-phase conducting switches SI1+, SI0+, controlled by in-phase conducting bits BI0, BI1, are coupled between the first in-phase switching input terminal NIin+ and the first in-phase switching output terminal NIout+. The in-phase conducting switches SI0-, SI1-, also controlled by the in-phase conducting bits BI0, BI1, are coupled between the second in-phase switching input terminal NIin- and the second in-phase switching output terminal NIout-. The in-phase diverting switches SI1+', SI0+', controlled by in-phase diverting bits BI0', BI1', have one terminal coupled to the first in-phase switching input terminal NIin+ and have another terminal to receive a voltage VDD. The in-phase diverting switches SI1-', SI0-', also controlled by the in-phase diverting bits BI0', BI1', have one terminal coupled to the second in-phase switching input terminal NIin- and have another terminal to receive the voltage VDD. The in-phase diverting bits BI0', BI1' are complements of the in-phase conducting bits BI0, BI1.

[0015] The first quadrature switching sub-circuit SWQ+ comprises a first quadrature switching input terminal NQin+, a second quadrature switching input terminal NQin-, a first quadrature switching output terminal NQout+, a second quadrature switching output terminal NQout-, quadrature conducting switches SQ1+, SQ0+, SQ0-, SQ1- and quadrature diverting switches SQ1+', SQ0+', SQ1-', SQ0-'. The first quadrature switching input terminal NQin+ of the quadrature switching sub-circuit SWQ+ is coupled to the positive quadrature output terminal OQ+. The second quadrature switching input terminal NQin- of the quadrature switching sub-circuit SWQ+ is coupled to the negative quadrature output terminal OQ-. The quadrature conducting switches SQ1+, SQ0+, controlled by quadrature conducting bits BQ0, BQ1, are coupled between the first quadrature switching input terminal NQin+ and the first quadrature switching output terminal NQout+. The quadrature conducting switches SQ0-, SQ1-, also controlled by the quadrature conducting bits BQ0, BQ1, are coupled between the second quadrature switching input terminal NQin- and the second quadrature switching output terminal NQout-. The quadrature diverting switches SQ1+', SQ0+', controlled by quadrature diverting bits BQ0', BQ1', have one terminal coupled to the first quadrature switching input terminal NQin+ and have another terminal to receive the voltage VDD. The quadrature diverting switches SQ1-', SQ0-', also controlled by the quadrature diverting bits BQ0', BQ1', have one terminal coupled to the second quadrature switching input terminal NQin- and have another terminal to receive the voltage VDD.

[0016] The conducting bits BI0, BI1, BQ0, BQ1 (or the diverting bits BI0', BI1', BQ0', BQ1') of the switching circuit 24 may be regarded as the bits B1,...,Bn of the switching circuit 14. The diverting bits BI0', BI1', BQ0', BQ1' are complements of the conducting bits BI0, BI1, BQ0, BQ1. That is, BI0' = 0 when BI0 = 1 and BI0' = 1 when BI0 = 0, for instance.

[0017] Operations of the switching circuit 24 are described as follows. FIG. 3 is a schematic diagram of a conduction status of the switching circuit 24. Suppose that (BI0, BI1, BQ0, BQ1) is (1, 0, 1, 1), which means that the switches SI0+, SI0-, SI1+', SI1-', SQ1+, SQ0+, SQ0-, SQ1- are conducted (ON) and the switches SI1+, SI1-, SI0+', SI0-', SQ1+', SQ0+', SQ1-', SQ0-' are cutoff (OFF). Suppose that an output current of the in-phase amplifier I-Amp is denoted as II and an output current of the quadrature amplifier Q-Amp is denoted as IQ. Within the in-phase switching sub-circuit SWI+, half of the output current II (i.e., 0.5II) would flow through the conducting switches SI0+, SI0- and another half of the output current II (i.e., 0.5II) would be diverted through the diverting switches SI1+', SI1-'. Current through the in-phase switching output terminals NIout+, NIout- would be 0.5 II. On the other hand, within the quadrature switching sub-circuit SWQ+, all of the output current IQ would flow through the conducting switches SQ1+, SQ0+, SQ0-, SQ1- and no current is diverted through the diverting switches SQ1+', SQ0+', SQ1-', SQ0-'. Current through the quadrature switching output terminals NQout+, NQout- would be IQ. Therefore, the output RF signal RFout would have a phase θ as tan-1(|IQ|/0.5|II|), where tan-1(·) denotes an inverse of tangent function. Suppose that |IQ| = |II|, meaning that the in-phase amplifier I-Amp and the quadrature amplifier Q-Amp produces the same output current, the phase difference θ is tan-1(2).

[0018] In another perspective, the switching circuit 24 is controlled mainly by 4 bits, where 2 bits are used for controlling in-phase component (i.e., the output in-phase signal Io) and 2 bits are used for quadrature component (i.e., the output quadrature signal Qo), which is for illustrative purpose. In practice, the switching circuit 14 may be controlled by 2*M bits, where M bits are used for controlling/adjusting in-phase component and M bits are used for controlling/adjusting the quadrature component, and various values of the phase difference θ would be generated.

[0019] In the prior art, the vector modulator utilizes variable gain amplifier (VGA) to adjust the in-phase component and the quadrature component. However, the VGA needs an analog signal to control the gain of the VGA, and a DAC is required, which increases a circuit complexity since the DAC is complicated. In comparison, by utilizing the switching circuit of the present invention, the digital bits B1,...,BN (e.g., the conducting bits BI0, BI1, BQ0, BQ1 or the diverting bits BI0', BI1', BQ0', BQ1') can be directly used to control/adjust the in-phase component and the quadrature component, such that the complexity and the production cost brought by DAC may be spared.

[0020] Note that, the switching circuit 24 generates the phase difference θ only within a range between 0° and 90°, i.e., the first quadrant of a complex plane, and not limited thereto. The switching circuit of the present invention may generate the phase difference θ distributed over a range between 0° and 360°.

[0021] For example, FIG. 4 is a schematic diagram of a switching circuit 44 according to an embodiment of the present invention. The switching circuit 44 is similar to the switching circuit 24, and thus, the same denotations are applied. Different from the switching circuit 24, the switching circuit 44 further comprises a second in-phase switching sub-circuit SWI- and a second quadrature switching sub-circuit SWQ-, in addition to the first in-phase switching sub-circuit SWI+ and the first quadrature switching sub-circuit SWQ+. The in-phase switching sub-circuit SWI- has the same circuit structure as the in-phase switching sub-circuit SWI+, and the quadrature switching sub-circuit SWQ- has the same circuit structure as the quadrature switching sub-circuit SWQ+. Different from the switching sub-circuit SWI+ and SWQ+, a first in-phase switching input terminal NIin+ of the second in-phase switching sub-circuit SWI- is coupled to the negative in-phase output terminal OI-, a second in-phase switching input terminal NIin- of the second in-phase switching sub-circuit SWI- is coupled to the positive in-phase output terminal OI+, a first quadrature switching input terminal NQin+ of the second quadrature switching sub-circuit SWQ- is coupled to the negative quadrature output terminal OQ-, and a second quadrature switching input terminal NQin- of the second quadrature switching sub-circuit SWQ- is coupled to the positive quadrature output terminal OQ+.

[0022] In other words, a current direction of the current flowing through the second in-phase switching sub-circuit SWI- would be opposite to a current direction of the current flowing through the first in-phase switching sub-circuit SWI+, and a current direction of the current flowing through the second quadrature switching sub-circuit SWQ- would be opposite to a current direction of the current flowing through the first quadrature switching sub-circuit SWQ+.

[0023] When the sub-circuits SWI- and SWQ+ are enabled, the switching circuit 44 is able to generate the phase difference θ within a range between 90° and 180°, i.e., the second quadrant. When the sub-circuits SWI- and SWQ- are enabled, the switching circuit 44 is able to generate the phase difference θ within a range between 180° and 270°, i.e., the third quadrant. When the sub-circuits SWI+ and SWQ- are enabled, the switching circuit 44 is able to generate the phase difference θ within a range between 270° and 360°, i.e., the fourth quadrant. Therefore, the switching circuit 44 is able to generate the phase difference θ distributed over the range between 0° and 360°.

[0024] In summary, the vector modulator utilizes the switching circuit comprising the plurality of switches and controlled by the plurality of bits to control/adjust the in-phase component and the quadrature component, such that the complexity and the production cost brought by DAC may be spared.


Claims

1. A vector modulator, characterized by, comprising:

a quadrature component generator (12), configured to generate an input in-phase signal (Ii) and an input quadrature signal (Qi) according to an input radio frequency (RF) signal (RFin);

a switching circuit (14), receiving a plurality of bits (B1,...,BN), comprising a plurality of switches controlled by the plurality of bits, configured to generate an output in-phase signal (Io) and an output quadrature signal (Qo) according to the plurality of bits (B1,...,BN), where the output in-phase signal (Io) and the output quadrature signal (Qo) are related to input in-phase signal (Ii) and the input quadrature signal (Qi); and

a combining module (16), configured to generate an output RF signal (RFout) according to the output in-phase signal (Io) and the output quadrature signal (Qo).


 
2. The vector modulator of claim 1, characterized in that, the switching circuit (14) comprises:

a switching input terminal, coupled to the quadrature component generator (12);

a switching output terminal, coupled to the combining module (16);

a plurality of conducting switches (SI1+, SI0+, SI0-, SI1-), coupled between the switching input terminal and the switching output terminal, controlled by a plurality of conducting bits within the plurality of bits; and

a plurality of diverting switches (SI1+', SI0+', SI1-', SI0-'), coupled to the switching input terminal and receiving a voltage, controlled by a plurality of diverting bits within the plurality of bits, wherein the plurality of diverting bits are complements of the plurality of conducting bits.


 
3. The vector modulator of claim 1, characterized by, further comprising
an in-phase amplifier (I-Amp), coupled between the quadrature component generator (12) and the switching circuit (14), configured to receive the input in-phase signal (Ii) and output an intermediate in-phase signal (Im); and
a quadrature amplifier (Q-Amp), coupled between the quadrature component generator (12) and the switching circuit (14), configured to receive the input quadrature signal (Qi) and output an intermediate quadrature signal (Qm).
 
4. The vector modulator of claim 3, characterized in that,
the input in-phase signal (Ii) comprises a first input in-phase signal (Ii+) and a second input in-phase signal (Ii-);
the input quadrature signal (Qi) comprises a first input quadrature signal (Qi+) and a second input quadrature signal (Qi-);
the in-phase amplifier comprises a first in-phase output terminal (OI+) and a second in-phase output terminal (OI-);
the quadrature amplifier comprises a first quadrature output terminal (OQ+) and a second quadrature output terminal (OQ+);
the intermediate in-phase signal (Im) comprises a first intermediate in-phase signal (Im+) and a negative intermediate in-phase signal (Im-);
the intermediate quadrature signal (Qm) comprises a first intermediate quadrature signal (Qm+) and a negative intermediate quadrature signal (Qm-);
the output in-phase signal (Io) comprises a first output in-phase signal (Io+) and a second output in-phase signal (Io-);
the output quadrature signal (Qo) comprises a first output quadrature signal (Qo+) and a second output quadrature signal (Qo-);
the output RF signal (RFout) comprises a first output RF signal (RFout+) and a second output RF signal (RFout-);
the combining module comprises:

a first combining element, configured to generate the first output RF signal (RFout+) according to the first output in-phase signal (Io+) and the first output quadrature signal (Qo+); and

a second combining element, configured to generate the second output RF signal (RFout-) according to the second output in-phase signal (Io-) and the second output quadrature signal (Qo-).


 
5. The vector modulator of claim 4, characterized in that, the switching circuit (24) comprises:

a first in-phase switching sub-circuit (SWI+), comprising:

a first in-phase switching input terminal (NIin+), coupled to the first in-phase output terminal of the in-phase amplifier;

a second in-phase switching input terminal (NIin-), coupled to the second in-phase output terminal of the in-phase amplifier;

a first in-phase switching output terminal (NIout+);

a second in-phase switching output terminal (NIout-);

a plurality of first in-phase conducting switches (SI1+, SI0+), coupled between the first in-phase switching input terminal (NIin+) and the first in-phase switching output terminal (NIout+), controlled by a plurality of in-phase conducting bits (BI0, BI1) within the plurality of bits; and

a plurality of second in-phase conducting switches (SI0-, SI1-), coupled between the second in-phase switching input terminal (NIin-) and the second in-phase switching output terminal (NIin-), controlled by the plurality of in-phase conducting bits (BI0, BI1) within the plurality of bits;

a plurality of first in-phase diverting switches (SI1+', SI0+'), coupled to the first in-phase switching input terminal (NIin+) and receiving a voltage (VDD), controlled by a plurality of in-phase diverting bits (BI0', BI1') within the plurality of bits, wherein the plurality of in-phase diverting bits (BI0', BI1') are complements of the plurality of in-phase conducting bits (BI0, BI1); and

a plurality of second in-phase diverting switches (SI1-', SI0-'), coupled to the second in-phase switching input terminal (NIin-) and receiving the voltage (VDD), controlled by the plurality of in-phase diverting bits (BI0', BI1'); and

a first quadrature switching sub-circuit (SWQ+), comprising:

a first quadrature switching input terminal (NQin+), coupled to the first quadrature output terminal of the quadrature amplifier;

a second quadrature switching input terminal (NQin-), coupled to the second quadrature output terminal of the quadrature amplifier;

a first quadrature switching output terminal (NQout+);

a second quadrature switching output terminal (NQout+);

a plurality of first quadrature conducting switches (SQ1+, SQ0+), coupled between the first quadrature switching input terminal (NQin+) and the first quadrature switching output terminal (NQout+), controlled by a plurality of quadrature conducting bits (BQ0, BQ1) within the plurality of bits;

a plurality of second quadrature conducting switches (SQ1-, SQ0-), coupled between the second quadrature switching input terminal (NQin-) and the second quadrature switching output terminal (NQout-), controlled by the plurality of quadrature conducting bits (BQ0, BQ1) within the plurality of bits;

a plurality of first quadrature diverting switches (SQ1+', SQ0+'), coupled to the first quadrature switching input terminal (NQin+) and receiving the voltage (VDD), controlled by a plurality of quadrature diverting bits (BQ0', BQ1') within the plurality of bits, wherein the plurality of quadrature diverting bits are complements of the plurality of first quadrature conducting bits; and

a plurality of second quadrature diverting switches (SQ1-', SQ0-'), coupled to the second quadrature switching input terminal (NQin-) and receiving the voltage (VDD), controlled by the plurality of quadrature diverting bits (BQ0', BQ1').


 
6. The vector modulator of claim 5, characterized in that, the switching circuit (14) comprises:

a second in-phase switching sub-circuit (SWI-), comprising:

a first in-phase switching input terminal (NIin+), coupled to the second in-phase output terminal of the in-phase amplifier;

a second in-phase switching input terminal (NIin-), coupled to the first in-phase output terminal of the in-phase amplifier;

a first in-phase switching output terminal (NIout+);

a second in-phase switching output terminal (NIout-);

a plurality of first in-phase conducting switches (SI1+, SI0+), coupled between the first in-phase switching input terminal (NIin+) and the first in-phase switching output terminal (NIout+), controlled by a plurality of in-phase conducting bits (BI0, BI1) within the plurality of bits; and

a plurality of second in-phase conducting switches (SI0-, SI1-), coupled between the second in-phase switching input terminal (NIin-) and the second in-phase switching output terminal (NIin-), controlled by the plurality of in-phase conducting bits (BI0, BI1) within the plurality of bits;

a plurality of first in-phase diverting switches( SI1+', SI0+'), coupled to the first in-phase switching input terminal (NIin+) and receiving the voltage (VDD), controlled by a plurality of in-phase diverting bits (BI0', BI1') within the plurality of bits, wherein the plurality of first in-phase diverting bits (BI0', BI1') are complements of the plurality of in-phase conducting bits (BI0, BI1); and

a plurality of second in-phase diverting switches (SI1-', SI0-'), coupled to the second in-phase switching input terminal (NIin-) and receiving the voltage (VDD), controlled by the plurality of in-phase diverting bits (BI0', BI1'); and

a second quadrature switching sub-circuit (SWQ-), comprising:

a first quadrature switching input terminal (NQin+), coupled to the second quadrature output terminal of the quadrature amplifier;

a second quadrature switching input terminal (NQin-), coupled to the first quadrature output terminal of the quadrature amplifier;

a first quadrature switching output terminal (NQout+);

a second quadrature switching output terminal (NQout+);

a plurality of first quadrature conducting switches (SQ1+, SQ0+), coupled between the first quadrature switching input terminal (NQin+) and the first quadrature switching output terminal (NQout+), controlled by a plurality of quadrature conducting bits (BQ0, BQ1) within the plurality of bits;

a plurality of second quadrature conducting switches (SQ1-, SQ0-), coupled between the second quadrature switching input terminal (NQin-) and the second quadrature switching output terminal (NQout-), controlled by the plurality of quadrature conducting bits (BQ0, BQ1) within the plurality of bits;

a plurality of first quadrature diverting switches (SQ1+', SQ0+'), coupled to the first quadrature switching input terminal (NQin+) and receiving the voltage (VDD), controlled by a plurality of quadrature diverting bits (BQ0', BQ1') within the plurality of bits, wherein the plurality of first quadrature diverting bits are complements of the plurality of first quadrature conducting bits; and

a plurality of second quadrature diverting switches (SQ1-', SQ0-'), coupled to the second quadrature switching input terminal (NQin-) and receiving the voltage (VDD), controlled by the plurality of quadrature diverting bits (BQ0', BQ1').


 


Amended claims in accordance with Rule 137(2) EPC.


1. A vector modulator, characterized by, comprising:

a quadrature component generator (12), configured to generate an input in-phase signal (Ii) and an input quadrature signal (Qi) according to an input radio frequency (RF) signal (RFin);

a switching circuit (14, 24), receiving a plurality of bits (B1,...,BN), comprising a plurality of switches controlled by the plurality of bits, configured to generate an output in-phase signal (Io) and an output quadrature signal (Qo) according to the plurality of bits (B1,...,BN), where the output in-phase signal (Io) and the output quadrature signal (Qo) are related to input in-phase signal (Ii) and the input quadrature signal (Qi); and

a combining module (16), configured to generate an output RF signal (RFout) according to the output in-phase signal (Io) and the output quadrature signal (Qo);

wherein the switching circuit (24) comprises:

a switching input terminal (NIin+), coupled to the quadrature component generator (12);

a switching output terminal (NIout+), coupled to the combining module (16);

a plurality of conducting switches (SI1+, SI0+), coupled between the switching input terminal and the switching output terminal, controlled by a plurality of conducting bits within the plurality of bits, wherein a plurality of first ends of the plurality of conducting switches (SI1+, SI0+) are electrically and directly connected to the switching input terminal (NIin+), and a plurality of second ends of the plurality of conducting switches (SI1+, SI0+) are electrically and directly connected to the switching output terminal (NIout+); and

a plurality of diverting switches (SI1+', SI0+'), coupled to the switching input terminal and receiving a voltage (VDD), controlled by a plurality of diverting bits within the plurality of bits, wherein the plurality of diverting bits are complements of the plurality of conducting bits, a plurality of first ends of the plurality of diverting switches (SI1+', SI0+') are electrically and directly connected to the switching input terminal (NIin+), and a plurality of second ends of the plurality of diverting switches (SI1+', SI0+') receive the voltage (VDD).


 
2. The vector modulator of claim 1, characterized by, further comprising
an in-phase amplifier (I-Amp), coupled between the quadrature component generator (12) and the switching circuit (14), configured to receive the input in-phase signal (Ii) and output an intermediate in-phase signal (Im); and
a quadrature amplifier (Q-Amp), coupled between the quadrature component generator (12) and the switching circuit (14), configured to receive the input quadrature signal (Qi) and output an intermediate quadrature signal (Qm).
 
3. The vector modulator of claim 2, characterized in that,
the input in-phase signal (Ii) comprises a first input in-phase signal (Ii+) and a second input in-phase signal (Ii-);
the input quadrature signal (Qi) comprises a first input quadrature signal (Qi+) and a second input quadrature signal (Qi-);
the in-phase amplifier comprises a first in-phase output terminal (OI+) and a second in-phase output terminal (OI-);
the quadrature amplifier comprises a first quadrature output terminal (OQ+) and a second quadrature output terminal(OQ+);
the intermediate in-phase signal (Im) comprises a first intermediate in-phase signal (Im+) and a negative intermediate in-phase signal (Im-);
the intermediate quadrature signal (Qm) comprises a first intermediate quadrature signal (Qm+) and a negative intermediate quadrature signal (Qm-);
the output in-phase signal (Io) comprises a first output in-phase signal (Io+) and a second output in-phase signal (Io-);
the output quadrature signal (Qo) comprises a first output quadrature signal (Qo+) and a second output quadrature signal (Qo-);
the output RF signal (RFout) comprises a first output RF signal (RFout+) and a second output RF signal (RFout-);
the combining module comprises:

a first combining element, configured to generate the first output RF signal (RFout+) according to the first output in-phase signal (Io+) and the first output quadrature signal (Qo+); and

a second combining element, configured to generate the second output RF signal (RFout-) according to the second output in-phase signal (Io-) and the second output quadrature signal (Qo-).


 
4. The vector modulator of claim 3, characterized in that, the switching circuit (24) comprises:

a first in-phase switching sub-circuit (SWI+), comprising:

a first in-phase switching input terminal (NIin+), coupled to the first in-phase output terminal of the in-phase amplifier;

a second in-phase switching input terminal (NIin-), coupled to the second in-phase output terminal of the in-phase amplifier;

a first in-phase switching output terminal (NIout+);

a second in-phase switching output terminal (NIout-);

a plurality of first in-phase conducting switches (SI1+, SI0+), coupled between the first in-phase switching input terminal (NIin+) and the first in-phase switching output terminal (NIout+), controlled by a plurality of in-phase conducting bits (BI0, BI1) within the plurality of bits; and

a plurality of second in-phase conducting switches (SI0-, SI1-), coupled between the second in-phase switching input terminal (NIin-) and the second in-phase switching output terminal (NIin-), controlled by the plurality of in-phase conducting bits (BI0, BI1) within the plurality of bits;

a plurality of first in-phase diverting switches (SI1+', SI0+'), coupled to the first in-phase switching input terminal (NIin+) and receiving a voltage (VDD), controlled by a plurality of in-phase diverting bits (BI0', BI1') within the plurality of bits, wherein the plurality of in-phase diverting bits (BI0', BI1') are complements of the plurality of in-phase conducting bits (BI0, BI1); and

a plurality of second in-phase diverting switches(SI1-', SI0-'), coupled to the second in-phase switching input terminal (NIin-) and receiving the voltage (VDD), controlled by the plurality of in-phase diverting bits (BI0', BI1'); and

a first quadrature switching sub-circuit (SWQ+), comprising:

a first quadrature switching input terminal (NQin+), coupled to the first quadrature output terminal of the quadrature amplifier;

a second quadrature switching input terminal (NQin-), coupled to the second quadrature output terminal of the quadrature amplifier;

a first quadrature switching output terminal (NQout+);

a second quadrature switching output terminal (NQout+);

a plurality of first quadrature conducting switches (SQ1+, SQ0+), coupled between the first quadrature switching input terminal (NQin+) and the first quadrature switching output terminal (NQout+), controlled by a plurality of quadrature conducting bits (BQ0, BQ1) within the plurality of bits;

a plurality of second quadrature conducting switches (SQ1-, SQ0-), coupled between the second quadrature switching input terminal (NQin-) and the second quadrature switching output terminal (NQout-), controlled by the plurality of quadrature conducting bits (BQ0, BQ1) within the plurality of bits;

a plurality of first quadrature diverting switches (SQ1+', SQ0+'), coupled to the first quadrature switching input terminal (NQin+) and receiving the voltage (VDD), controlled by a plurality of quadrature diverting bits (BQ0', BQ1') within the plurality of bits, wherein the plurality of quadrature diverting bits are complements of the plurality of first quadrature conducting bits; and

a plurality of second quadrature diverting switches (SQ1-', SQ0-'), coupled to the second quadrature switching input terminal (NQin-) and receiving the voltage (VDD), controlled by the plurality of quadrature diverting bits (BQ0', BQ1').


 
5. The vector modulator of claim 4, characterized in that, the switching circuit (14) comprises:

a second in-phase switching sub-circuit (SWI-), comprising:

a first in-phase switching input terminal (NIin+), coupled to the second in-phase output terminal of the in-phase amplifier;

a second in-phase switching input terminal (NIin-), coupled to the first in-phase output terminal of the in-phase amplifier;

a first in-phase switching output terminal (NIout+);

a second in-phase switching output terminal (NIout-);

a plurality of first in-phase conducting switches (SI1+, SI0+), coupled between the first in-phase switching input terminal (NIin+) and the first in-phase switching output terminal (NIout+), controlled by a plurality of in-phase conducting bits (BI0, BI1) within the plurality of bits; and

a plurality of second in-phase conducting switches (SI0-, SI1-), coupled between the second in-phase switching input terminal (NIin-) and the second in-phase switching output terminal (NIin-), controlled by the plurality of in-phase conducting bits (BI0, BI1) within the plurality of bits;

a plurality of first in-phase diverting switches(SI1+', SI0+'), coupled to the first in-phase switching input terminal (NIin+) and receiving the voltage (VDD), controlled by a plurality of in-phase diverting bits (BI0', BI1') within the plurality of bits, wherein the plurality of first in-phase diverting bits (BI0', BI1') are complements of the plurality of in-phase conducting bits (BI0, BI1); and

a plurality of second in-phase diverting switches(SI1-', SI0-'), coupled to the second in-phase switching input terminal (NIin-) and receiving the voltage (VDD), controlled by the plurality of in-phase diverting bits (BI0', BI1'); and

a second quadrature switching sub-circuit (SWQ-), comprising:

a first quadrature switching input terminal (NQin+), coupled to the second quadrature output terminal of the quadrature amplifier;

a second quadrature switching input terminal (NQin-), coupled to the first quadrature output terminal of the quadrature amplifier;

a first quadrature switching output terminal (NQout+);

a second quadrature switching output terminal (NQout+);

a plurality of first quadrature conducting switches (SQ1+, SQ0+), coupled between the first quadrature switching input terminal (NQin+) and the first quadrature switching output terminal (NQout+), controlled by a plurality of quadrature conducting bits (BQ0, BQ1) within the plurality of bits;

a plurality of second quadrature conducting switches (SQ1-, SQ0-), coupled between the second quadrature switching input terminal (NQin-) and the second quadrature switching output terminal (NQout-), controlled by the plurality of quadrature conducting bits (BQ0, BQ1) within the plurality of bits;

a plurality of first quadrature diverting switches (SQ1+', SQ0+'), coupled to the first quadrature switching input terminal (NQin+) and receiving the voltage (VDD), controlled by a plurality of quadrature diverting bits (BQ0', BQ1') within the plurality of bits, wherein the plurality of first quadrature diverting bits are complements of the plurality of first quadrature conducting bits; and

a plurality of second quadrature diverting switches (SQ1-', SQ0-'), coupled to the second quadrature switching input terminal (NQin-) and receiving the voltage (VDD), controlled by the plurality of quadrature diverting bits (BQ0', BQ1').


 




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