(19)
(11)EP 3 699 912 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
09.09.2020 Bulletin 2020/37

(43)Date of publication A2:
26.08.2020 Bulletin 2020/35

(21)Application number: 20152108.5

(22)Date of filing:  27.09.2012
(51)International Patent Classification (IPC): 
G11C 11/4076(2006.01)
G11C 11/4096(2006.01)
G11C 7/10(2006.01)
G06F 13/16(2006.01)
G11C 11/408(2006.01)
G11C 7/22(2006.01)
G11C 11/4072(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 28.09.2011 JP 2011212141

(62)Application number of the earlier application in accordance with Art. 76 EPC:
18182031.7 / 3401912
16206638.5 / 3206209
12186212.2 / 2575137

(71)Applicant: Longitude Licensing Limited
Dublin D18 P3Y9 (IE)

(72)Inventor:
  • Kondo, Chikara
    Tokyo, Tokyo 104-0028 (JP)

(74)Representative: FRKelly 
27 Clyde Road
Dublin D04 F838
Dublin D04 F838 (IE)

  


(54)SEMICONDUCTOR DEVICE


(57) The present teachings relate to a method for operating a system comprising a controller and a plurality of memory devices, the method comprising providing at a first time a first mode register setting command, a first plurality of selection signals, and a first mode signal from the controller to the plurality of memory devices in common, providing at a second time later than the first time a first enable signal having a first logic level from the controller to a first memory device of the plurality of memory devices and a second enable signal having a second logic level opposite the first logic level from the controller to a second memory device of the plurality of memory devices, and storing the first mode signal in a first mode register selected by the first plurality of selection signals in the first memory device and not storing the first mode signal in a first mode register selected by the first plurality of selection signals in the second memory device.







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