(19)
(11)EP 3 734 244 A1

(12)EUROPEAN PATENT APPLICATION

(43)Date of publication:
04.11.2020 Bulletin 2020/45

(21)Application number: 19172183.6

(22)Date of filing:  02.05.2019
(51)International Patent Classification (IPC): 
G01K 7/01(2006.01)
H03K 17/082(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(71)Applicant: Siemens Aktiengesellschaft
80333 München (DE)

(72)Inventor:
  • Melkonyan, Ashot
    81549 München (DE)

  


(54)CIRCUIT ARRANGEMENT AND METHOD FOR CONTROLLING A POWER SEMICONDUCTOR SWITCH


(57) Circuit arrangement for controlling a power semiconductor switch, the switch comprising a gate terminal, a source terminal and a drain terminal with a conduction channel being formed between the source and drain terminals, the circuit arrangement comprising:
- means for generating a control signal by which the semiconductor switch is alternated between a turned-on state and a turned-off state;
- a current source for generating a current into the gate terminal;
- an evaluation unit arranged to:
-- measure the voltage between the gate terminal and one of the source terminal and drain terminal while the semiconductor switch is in the turned-on state,
-- determine from the measured voltage and the current from the current source the absolute temperature of the semiconductor switch.






Description


[0001] The present invention relates to circuit arrangement and method for driving a power semiconductor switching element, such as a SiC JFET or a GaN HEMT switch, the switch comprising a source terminal and a drain terminal and a conduction channel formed between these terminals depending on a voltage applied at a gate terminal.

[0002] Semiconductor switching elements are used for example as power switching elements. There is a need to monitor the temperature of the semiconductor switching element to ensure the safe operation of the semiconductor switching element and a module that contains the switching element. When the temperature of the switching element becomes too high the circuit driving this switching element may advantageously ensure a safe shutdown procedure.

[0003] Typically, a power semiconductor module employs temperature sensors such as NTC (negative temperature coefficient) temperature sensors to find the temperature of a switching element. The temperature sensors are typically arranged on a carrier plate (base plate) on which the semiconductor switching element is also arranged. Alternatively, the temperature sensors may be arranged directly on a heat sink near the semiconductor switching element. In both cases the temperature measurement is associated with an uncertainty which is mainly due to the thermal capacity of the carrier plate or heat sink and the thermal behavior. The time constant of the thermal inertia reduces the reaction rate of the associated temperature monitoring circuit. This can lead to a dynamic overheating of the module and even to a thermal failure.

[0004] The objective of the present invention is to provide a circuit arrangement and a method for driving a semiconductor switching element which allow a precise and immediate determination of the temperature of the semiconductor switching element.

[0005] This objective is achieved by a circuit arrangement according to the features of claim 1 and a method according to the features of claim 5.

[0006] The invention provides a circuit arrangement for controlling a power semiconductor switching element, the switching element comprising a gate terminal, a source terminal and a drain terminal with a conduction channel being formed between the source and drain terminals. The circuit arrangement comprises means for generating a control signal by which the semiconductor switch is alternated between a turned-on state and a turned-off state. The circuit arrangement further comprises a current source for generating a current into the gate terminal and an evaluation unit arranged to measure the voltage between the gate terminal and one of the source and drain terminal while the semiconductor switching element is in the turned-on state and further arranged to determine from the measured voltage and the current from the current source the absolute temperature of the semiconductor switch.

[0007] The method according to the invention for controlling a power semiconductor switch, the switch comprising a gate terminal, a source terminal and a drain terminal with a conduction channel being formed between the source and drain terminals, comprises the steps:
  • generating a control signal by which the semiconductor switch is alternated between a turned-on state and a turned-off state;
  • with a current source, generating a DC current into the gate terminal;
  • measuring the voltage between the gate terminal and one of the source terminal and drain terminal while the semiconductor switch is in the turned-on state,
  • determining from the measured voltage and the current from the current source the absolute temperature of the semiconductor switch.


[0008] The invention recognizes that a junction between the gate and source/drain terminals that can carry current and exhibits a threshold voltage, e.g. a p-n junction or a Schottky junction, may advantageously be employed to determine the temperature of the transistor element. The invention uses the temperature dependence of this junction's I-V characteristic.

[0009] When the voltage between the gate and source terminals exceeds a threshold voltage level of ca. 7 V - 8 V the space charge region penetrates the barrier region and reaches the AlGaN barrier layer. Then the intrinsic gate diode becomes positively biased and starts to conduct a let-trough current. Advantageously the invention uses a current source to inject the small DC sensing current flowing through the gate diode just after switching the switching element into the ON state. This advantageously limits currents being supplied by the gate driver circuit when exceeding the threshold voltage level. The current source may be a resistor of high resistance. With the current being set by the current source the voltage over the gate-source diode is measured and the temperature is determined from the measured voltage.

[0010] Advantageously the invention allows a direct highly dynamic and precise temperature measurement of the power switching element. The measurement is independent from the current flowing through the channel of the semiconductor switching element. In other words, the temperature measurement can be made during operation of the switching element. Since the temperature is not measured at the heat sink or a base plate but instead directly at the semiconductor switching element itself, there is no thermal capacity leading to a measurement lag and no heat spreading leading to false measurement values. This allows precise control of the switching element and fast reactions to over-temperature.

[0011] Further features that may be added alone or together in exemplary embodiments of the invention include:
  • The power semiconductor switch may be a wide-bandgap switch, particularly a SiC-based or GaN-based power semiconductor switch.
  • The power semiconductor switch may be a JFET device or a HEMT device.
  • The current source may be configured to provide a constant current. The temperature can then be directly determined from the measured voltage over the gate diode.
  • The means for generating a control signal may comprise a microprocessor arranged to generate a pulse width modulation signal for controlling the semiconductor switch. This is typical of operation of a half-bridge in a power converter.
  • The circuit arrangement may comprise a unit for detection whether the semiconductor switch is in a turned-on state.
  • The evaluation unit may be further arranged to determine the source-drain current flowing in the power semiconductor switch from the temperature or the determined voltage. This recognizes that the source-drain current, i.e. the main current flowing in the switch heats up the switch and is thus directly responsible for an elevated temperature of the switch. Thus, the source-drain current can be deduced from the measured temperature or the measured voltage. The invention recognizes that this is possible specifically because the temperature measurement happens directly within the power semiconductor switch and thus has a very low reaction time. This contrasts with an external temperature measurement of the switch which is subject to the thermal mass and thermal resistance surrounding the switch and will therefore typically be far too slow to allow, e.g., a timely reaction to an overcurrent.
  • Alternatively or in addition the evaluation unit may be arranged to deduce if a critical current, i.e. an overcurrent is present between source and drain terminal from the measured temperature or the measured voltage.
  • The evaluation unit may be arranged to determine an ambient temperature of the power semiconductor switch and use the ambient temperature in determining the source-drain current. In this way the effect of different ambient temperatures such as 10 °C or 30 °C can be considered in determining the source-drain current for increased precision.


[0012] Embodiments of the present invention are now described with reference to the accompanying drawings to which the invention is not limited. The illustrations of the drawings are in schematic form. Similar or identical elements use the same reference signs throughout the figures.

Fig. 1 gives a schematic representation of an inventive circuit arrangement for driving a GaN-based HEMT transistor which allows determining the temperature of the semiconductor.

Fig. 2 illustrates the typical characteristic of the gate current versus the gate-source voltage.



[0013] Fig. 1 shows an embodiment of a circuit arrangement 20 according to the invention for driving a GaN-based high electron mobility transistor 10. The GaN HEMT device 10 includes a control terminal G (gate) and a first main terminal D (drain) and a second main terminal S (Source). When the GaN HEMT device 10 is turned on, a channel is formed between the first main terminal D and the second main terminal S through which a current can flow. The control terminal G of the GaN HEMT device 10 is connected to a region of n-type conductivity formed from AlGaN (aluminum gallium nitride), forming a Schottky barrier which behaves as a diode.

[0014] The circuit arrangement 20 described hereinafter allows determining the temperature of the aforementioned Schottky diode, that is, the gate-source diode, and thus the temperature of the whole GaN HEMT device 10. The temperature can be determined during operation of the semiconductor switching element.

[0015] The circuit arrangement 20 comprises a unit 21 for detection of a desaturation, a fault memory 22, a unit 23 for signal detection and evaluation, a constant current source 25, a logic gate 26 and a drive signal generating microprocessor 28. The drive signal is a pulse-width modulated signal (PWM signal) which is routed through the logic gate 26 and the unit 23 for signal detection and evaluation to the gate terminal G. The PWM signal from microprocessor 28 switches the GaN HEMT device 10 alternately on and off. The conduction state of the GaN HEMT device 10 alternates according to the PWM signal. A second input of the logic gate 26 is an output of fault memory 22. The constant current source 25 is connect to a supply voltage.

[0016] The unit 23 for signal detection and evaluation is connected between the control terminal G and the second main terminal S. The unit 23 detects the voltage across the gate-source diode. Additionally, it may detect the current flowing into or out of the gate. Resistor 27 is provided for current detection in the circuit.

[0017] The unit 21 for detection of a desaturation is connected to the first main terminal D, i.e. the drain terminal. Unit 21 is used to detect the current conduction state of the GaN HEMT device 10, i.e. whether the GaN HEMT device 10 is currently conducting or blocking current.

[0018] Unit 21 for the detection of desaturation is connected to the fault memory 22. When a fault occurs, an error signal is fed to gate 26, so that the output of gate 26 ensures a blocking state of GaN HEMT device 10. The unit 29 for blocking overcurrent peaks ("blanking time") also receives the output of gate 26. The unit 29 is used to block current peaks, for example during current commutation. On the output side, unit 29 is connected to unit 21.

[0019] The circuit shown in Fig. 1 is a typical driver circuit for a transistor except for the constant current source 25 and the unit 23 for signal detection and evaluation which are not typically part of a driver circuit. Constant current source 25 may be a resistor while the unit 23 for signal detection and evaluation may be provided as an operational amplifier circuit.

[0020] During operation of the GaN HEMT device 10 and when the GaN HEMT device 10 is in a conductive state, i.e. is turned on, the unit 23 for signal detection and evaluation can measure the voltage across the gate-source diode. The current through the diode is equal to the current supplied by the constant current source 25 and may be e.g. 1 mA or 1.5 mA. The measured voltage is therefore a direct measure of the temperature shift of the IV characteristic of the gate-source diode. A higher temperature will yield a lower voltage at the current of the constant current source 25.

[0021] Fig. 2 illustrates a diagram showing the (positive) gate current Ig as a function of the gate-source voltage Vgs of a GaN-HEMT. In the diagram, three experimentally determined IV-curves as a function of temperature are shown. It may be seen that for higher temperatures at the pn junction the current through the gate diode increases for a given voltage. When the current is held constant through the current source, the voltage decreases with rising temperature. In the IV-curves of fig. 2, the voltage difference at a current of 1 mA between temperatures of 25 °C and 55 °C is ca. 800 mV while the voltage difference at a current of 1 mA between temperatures of 25 °C and 75 °C is ca. 1000 mV.

[0022] This means that unit 23 for voltage detection and evaluation may deduce the temperature of the gate diode and thus of the GaN HEMT device 10 by a simple comparison of a measured voltage with values stored in a memory. This can be done with precision and a virtually non-existent time delay. Thus an overtemperature shutdown of a module containing the GaN HEMT device 10 can be prevented. The method can be used to determine the reliability, the aging behavior and the remaining lifetime of the GaN HEMT device 10.

[0023] List of reference numerals
10
GaN HEMT device
20
Circuit arrangement
21
Unit for the detection of desaturation
22
Fault memory
23
Unit for voltage detection and evaluation
25
Constant current source
26
Logic gate
27
Resistor
28
Microprocessor
29
Unit for blocking overcurrent peaks
G
Gate terminal
S
Source terminal
D
Drain terminal



Claims

1. Circuit arrangement (20) for controlling a power semiconductor switch (10), the switch (10) comprising a gate terminal (G), a source terminal (S) and a drain terminal (D) with a conduction channel being formed between the source and drain terminals (S, D), the circuit arrangement (20) comprising:

- means for generating a control signal by which the semiconductor switch (10) is alternated between a turned-on state and a turned-off state;

- a current source (25) for injecting a current into the gate terminal (G);

- an evaluation unit arranged to:

-- measure the voltage between the gate terminal (G) and one of the source terminal and drain terminal (S, D) while the semiconductor switch (10) is in the turned-on state,

-- determine from the measured voltage and the current from the current source (25) the absolute temperature of the semiconductor switch (10).


 
2. The circuit arrangement (20) of claim 1 wherein the power semiconductor switch (10) is a wide-bandgap switch (10), particularly a SiC-based or GaN-based power semiconductor switch (10) .
 
3. The circuit arrangement (20) of claim 1 or 2 wherein the power semiconductor switch (10) is a JFET device or a HEMT device (10).
 
4. The circuit arrangement (20) of any of the preceding claims wherein the current source (25) is configured to provide a constant current.
 
5. The circuit arrangement (20) of any of the preceding claims wherein the means for generating a control signal comprise a microprocessor (28) arranged to generate a pulse width modulation signal for controlling the semiconductor switch (10).
 
6. The circuit arrangement (20) of any of the preceding claims comprising a unit for detection whether the semiconductor switch (10) is in a turned-on state.
 
7. The circuit arrangement (20) of any of the preceding claims wherein the evaluation unit is further arranged to determine the source-drain current flowing in the power semiconductor switch (10) from the temperature.
 
8. The circuit arrangement (20) of any of the preceding claims wherein the evaluation unit is further arranged to determine the presence of an overcurrent flowing in the power semiconductor switch (10) from the temperature.
 
9. The circuit arrangement (20) of claim 7 or 8 wherein the evaluation unit is arranged to determine an ambient temperature of the power semiconductor switch (10) and use the ambient temperature in determining the source-drain current.
 
10. Method for controlling a power semiconductor switch (10), the switch comprising a gate terminal (G), a source terminal (S) and a drain terminal (D) with a conduction channel being formed between the source and drain terminals (S, D), comprising the steps:

- generating a control signal by which the power semiconductor switch (10) is alternated between a turned-on state and a turned-off state;

- with a current source (25), generating a current into the gate terminal (G);

- measuring the voltage between the gate terminal (G) and one of the source terminal (S) and drain terminal (D) while the semiconductor switch (10) is in the turned-on state,

- determining from the measured voltage and the current from the current source (25) the absolute temperature of the semiconductor switch (10).


 
11. The method of claim 10, wherein a constant current is generated with the current source (25).
 
12. The method of claim 10 or 11, wherein a source-drain current of the power semiconductor switch (10) is determined from the measured voltage.
 




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