(19)
(11)EP 3 736 657 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
27.07.2022 Bulletin 2022/30

(21)Application number: 20171289.0

(22)Date of filing:  24.04.2020
(51)International Patent Classification (IPC): 
G06F 1/04(2006.01)
H04L 12/40(2006.01)
(52)Cooperative Patent Classification (CPC):
G06F 1/04; H04L 12/40182

(54)

PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD

VERARBEITUNGSSYSTEM, ZUGEHÖRIGE INTEGRIERTE SCHALTUNG, VORRICHTUNG UND VERFAHREN

SYSTÈME DE TRAITEMENT, CIRCUIT INTÉGRÉ ASSOCIÉ, DISPOSITIF ET PROCÉDÉ


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 08.05.2019 IT 201900006633

(43)Date of publication of application:
11.11.2020 Bulletin 2020/46

(73)Proprietor: STMicroelectronics Application GmbH
85609 Aschheim (DE)

(72)Inventor:
  • NANDLINGER, Mr. Rolf
    D-82211 Herrsching (DE)

(74)Representative: Bosotti, Luciano et al
Buzzi, Notaro & Antonielli d'Oulx S.p.A. Corso Vittorio Emanuele ll, 6
10123 Torino
10123 Torino (IT)


(56)References cited: : 
US-A1- 2013 042 135
US-A1- 2015 003 443
  
  • Hauke Webermann: "CAN Send and Receive with Hardware Timestamping", , 8 March 2017 (2017-03-08), pages 04-6, XP055657065, Retrieved from the Internet: URL:https://esd.eu/sites/default/files/pap er_16_icc_timestamping_hauke_webermann1.pd f [retrieved on 2020-01-13]
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Technical Field



[0001] Embodiments of the present disclosure relate to the time management within processing systems, such as micro-controllers.

Background



[0002] Figure 1 shows a typical electronic system, such as the electronic system of a vehicle, comprising a plurality of processing systems 10, such as embedded systems or integrated circuits, e.g., a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP) or a micro-controller (e.g., dedicated to the automotive market).

[0003] For example, in Figure 1 are shown three processing systems 101, 102 and 103 connected through a suitable communication system 20. For example, the communication system may include a vehicle control bus, such as a Controller Area Network (CAN) bus, and possibly a multimedia bus, such as a Media Oriented Systems Transport (MOST) bus, connected to vehicle control bus via a gateway. Typically, the processing systems 10 are located at different positions of the vehicle and may include, e.g., an Engine Control Unit (ECU), a Transmission Control Unit (TCU), an Anti-lock Braking System (ABS), a body control modules (BCM), and/or a navigation and/or multimedia audio system.

[0004] Future generations of processing systems, in particular micro-controllers dedicated to automotive applications, will exhibit a significant increase in complexity, mainly due to the increasing number of functionalities (such as new protocols, new features, etc.) and to the tight constraints concerning the operation conditions of the system (such as lower power consumption, increased calculation power and speed, etc.).

[0005] Figure 2 shows a block diagram of an exemplary digital processing system 10, such as a micro-controller, which may be used as any of the processing systems 10 of Figure 1.

[0006] In the example considered, the processing system 10 comprises at least one processing unit 102, such as a microprocessor, usually the Central Processing Unit (CPU), programmed via software instructions. Usually, the software executed by the processing unit 102 is stored in a program memory 104, such as a non-volatile memory, such as a Flash memory or EEPROM. Generally, the memory 104 may be integrated with the processing unit 102 in a single integrated circuit, or the memory 104 may be in the form of a separate integrated circuit and connected to the processing unit 102, e.g. via the traces of a printed circuit board. Thus, in general the memory 104 contains the firmware for the processing unit 102, wherein the term firmware includes both the software of a micro-processor and the programming data of a programmable logic circuit, such as a FPGA.

[0007] In the example considered, the processing unit 102 may have associated one or more resources 106 selected from the group of:
  • one or more communication interfaces IF, e.g. for exchanging data via the communication system 20, such as a Universal asynchronous receiver/transmitter (UART), Serial Peripheral Interface Bus (SPI), Inter-Integrated Circuit (I2C), Controller Area Network (CAN) bus, and/or Ethernet interface, and/or a debug interface; and/or
  • one or more analog-to-digital converters AD and/or digital-to-analog converters DA; and/or
  • one or more dedicated digital components DC, such as hardware timers and/or counters, or a cryptographic co-processor; and/or
  • one or more analog components AC, such as comparators, sensors, such as a temperature sensor, etc.; and/or
  • one or more mixed signal components MSC, such as a PWM (Pulse-Width Modulation) driver.


[0008] Accordingly, the digital processing system 10 may support different functionalities. For example, the behavior of the processing unit 102 is determined by the firmware stored in the memory 104a, e.g., the software instructions to be executed by a microprocessor 102 of a micro-controller 10. Thus, by installing a different firmware, the same hardware (micro-controller) can be used for different applications.

[0009] As mentioned before, the processing systems 10 may control different operations of the vehicle, wherein the processing systems 10 may be located at different positions in the vehicle and each processing system 10 may implement one or more functions/operations. Many of these functions/operations have to be execute in real-time. For example, the engine control is subject to thermodynamic laws that should be balanced with the real-time state of the vehicle. Typically, the real time state of the vehicle is monitored via sensors, which may be connected directly to the processing system 10 implementing the Engine Control Unit (ECU) or to other processing systems 10 of the vehicle. Similarly, in order to control/command the operation the motor, the Engine Control Unit (ECU) has to control/command one or more actuators, e.g. in order to inject the fuel, open a valve for gas discharge etc., which may be connected directly to the processing system 10 implementing the Engine Control Unit (ECU) or to other processing systems 10 of the vehicle.

[0010] Thus, in many applications, the execution of a first operation within a processing system 10 has to be synchronized with the execution of a second operation within the same processing system 10 or within a further processing system 10.

[0011] Hence, the present invention relates to a processing system comprising a time reference circuit according to the preamble of Claim 1, which is known, e.g., from Hauke Webermann, "CAN Send and Receive With Hardware Timestamping", 8 March 2017 (2017-03-08), pages 04-06.

[0012] Documents US 2015/003443 A1 and US 2013/042135 A1, disclosing a selection of a subset of bits of a time base value, may also be of interest for the present invention.

Summary



[0013] In view of the above, it is an objective of various embodiments of the present disclosure to provide solutions for generating a time reference within a processing system and for distributing this time reference to plural circuits of the processing system.

[0014] According to one or more embodiments, one or more of the above objectives is achieved by means of a processing system having the features specifically set forth in the claims that follow. Embodiments moreover concern a related integrated circuit, device and method.

[0015] The claims are an integral part of the technical teaching of the disclosure provided herein.

[0016] As mentioned before, various embodiments of the present disclosure relate to a processing system. In various embodiments, the processing system, such as an integrated circuit, comprises a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. For example, the processing system may be a microcontroller and the digital processing unit may be a microprocessor of the microcontroller.

[0017] In various embodiments, the processing system comprises moreover a time reference circuit comprising a first digital counter circuit configured to generate, in response to a clock signal, a system time signal comprising a plurality of bits indicative of a time tick-count. For example, in various embodiments, the first digital counter circuit of the time reference circuit is configured to generate the system time signal by increasing the value of the system time signal by a given amount in response to the clock signal. In various embodiments, this given amount may be programmable by means of the processing unit.

[0018] In various embodiments, the processing system comprises moreover a time base distribution circuit configured to generate a time base signal by selecting a subset of the bits of the system time signal. In various embodiments, the time base distribution circuit is configured to generate a time base signal by selecting a first subset of a given number of bits of the system time signal when a selection signal has a first value, and a second subset of the given number of bits of the system time signal when the selection signal has a second value, whereby the time resolution of the time base signal varies as a function of the selection signal.

[0019] In various embodiments, the time base signal is provided to the resource. In this case, the resource may be configured to detect a given event, store the time base signal to a register in response to the event, and signal the event to the digital processing unit. Accordingly, the digital processing unit may, in response to the event having been signaled by the resource, read via the communication system the time base signal from the register.

[0020] For example, the resource may be an analog-to-digital converter and the event may correspond to the completion of an analog-to-digital conversion, and/or the resource may be a communication interface and the event may correspond to the reception of data via the communication interface.

[0021] In various embodiments, the time reference circuit may also comprise further circuits.

[0022] For example, in various embodiments, the time reference circuit comprises an extended timer circuit comprising a second digital counter circuit configured to generate, in response to the clock signal or a trigger signal generated as a function of the clock signal, an extended system time signal comprising a number of bits being greater than the number of bits of the system time signal, wherein the extended system time signal is readable by means of the digital processing unit.

[0023] In various embodiments, the time reference circuit comprises an operation time counter circuit comprising a plurality of third digital counter circuits configured to generate, in response to the clock signal or a trigger signal generated as a function of the clock signal, respective count values, wherein each of the plurality of third digital counter circuits may be reset, started and stopped by the digital processing unit.

[0024] Finally, in various embodiments, the time reference circuit may comprise a trigger generator circuit comprising one or more fourth digital counter circuits configured to generate, in response to the clock signal or a trigger signal generated as a function of the clock signal, at least one trigger signal.

Brief description of the figures



[0025] Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:
  • Figure 1 shows a typical electronic system;
  • Figure 2 shows a typical processing system of the electronic system of Figure 1;
  • Figure 3 shows an embodiment of a processing system comprising a timer reference circuit configured to generating a system time signal and a circuit configured to use the system time signal;
  • Figure 4 shows an embodiment of the timer reference circuit of Figure 3, wherein the timer reference circuit generates via a counter circuit a global reference time signal and via a time base distribution circuit a plurality of additional reference time signals;
  • Figure 5 shows an embodiment of the counter circuit of Figure 4;
  • Figures 6A and 6B show embodiments how a processing unit of the processing system may obtain the global reference time signal or one of the additional reference time signals;
  • Figures 7 and 8 show embodiments of one or more circuits which use the additional reference time signals in order to store a time stamp directly at a hardware level in response to given events;
  • Figure 9 shows an embodiment of the time base distribution circuit of Figure 4;
  • Figure 10 shows a further embodiment of the timer reference circuit of Figure 3 comprising also an extended timer circuit, an operation time counter circuit and a trigger generator circuit;
  • Figure 11 shows an embodiment of a trigger generator circuit generating a trigger signal adapted to activate the extended timer circuit, operation time counter circuit and trigger generator circuit of Figure 10;
  • Figure 12 shows an embodiment of the extended timer circuit of Figure 10;
  • Figure 13 shows an embodiment of the operation of the extended timer circuit of Figure 12;
  • Figures 14, 15, 16 and 17 shows an embodiment of the trigger generator circuit of Figure 10;
  • Figure 18 shows an embodiment of the operation time counter circuit of Figure 10;
  • Figure 19 shows an embodiment of the operation of the operation time counter circuit of Figure 18; and
  • Figure 20 shows an embodiment of the transmission of the additional reference time signals of Figure 4 to one or more circuits of the processing system.

Detailed Description



[0026] In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0027] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0029] In the following Figures 3 to 20 parts, elements or components which have already been described with reference to Figures 1 and 2 are denoted by the same references previously used in such Figures; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

[0030] As described in the forgoing with respect to Figures 1 and 2, in many applications, the execution of a first operation within a processing system 10 has to be synchronized with the execution of a second operation within the same processing system 10 or within a further processing system 10.

[0031] For example, in many applications the data/message exchange with one or more of the resources 106 of the processing system 10, which e.g. may include information such as status data, sensor data, actuator commands, etc., should be linked to some kind of time reference/time stamp. For a temporal correlation of these functions/operations a common time base is thus required. For example, the conventional approach to this request consists in implementing some time reference within each processing systems 10 configured to execute synchronized operations, wherein the time reference circuit provides a global system time for the respective processing system 10. For example, this internal time reference circuit may be implemented with a timer circuit or a real-time-clock.

[0032] For example, a processing system 10 may acquire sensor data from a sensor via an analog-to-digital converter, ADC (see also block AD in Figure 2). Typically, for this purpose, the ADC is configured to generate an interrupt for the processing unit 102 when the A/D conversion is completed. In response to this interrupt, the processing unit 102, such as a microprocessor programmed via software instructions, may read the digital sample provided by the ADC and read also the global system time from the reference circuit, thereby associating a sampling time/time stamp with the digital sample for the sensor data. Similar interrupts indicating given events, which should then be associated with a given time stamp, may also be generated by other resources 106 of the processing system 10, such as a communication interface generating an interrupt on reception of a message (such as a status message or an actuation command), a timer circuit, etc.

[0033] The time stamping, i.e. the acquiring of the global system time and association of this time to a given event, may thus be performed by the processing unit 102, e.g. via software instructions, e.g. by means of an operating system installed on the processing unit 102. However, such software generated time stamps associated with given events/interrupts signaled by one or more of the resources 106 may have only a coarse accuracy related to the point of time when the event/interrupt has been received or generated, e.g. because they need to be transferred first through several software layers before a software time stamp is added. This delay may thus have a negative impact on the real-time behavior of the overall system and therefore the delay and the variation on the delay should be as small as possible.

[0034] Figure 3 shows an embodiment of a processing system 10a in accordance with the present description.

[0035] In the embodiment considered, the processing system 10a comprises a time reference circuit 122 configured to generate a time reference signal GST, which is provided to a plurality of circuits 110 of the processing system 10a. Generally, the circuit 110 may be any circuit of the processing 10a requiring a reference time. For example, reference can be made to the description of the processing system 10 shown in Figure 2. For example, the circuit 110 may be a processing unit 102 or one of the resources 106 shown in Figure 2. Preferably, the time reference circuit 122 and the circuit(s) 110 are integrated in the same integrated circuit.

[0036] Specifically, in the embodiment considered, the time reference circuit 122 is configured to generate the signal GST in response to a clock signal CLK provided by an oscillator circuit 120. Generally, the oscillator circuit 120 may be integrated in the integrated circuit of the processing system 10a or may be at least in part be connected to a pin of the integrated circuit of the processing system 10a. For example, in various embodiments, the oscillator circuit 120 may be implemented with an external reference oscillator and an internal phase-locked loop (PLL).

[0037] Thus, generally, the time reference circuit 122 receives at input a clock signal CLK and generates the time reference signal GST. Specifically, in various embodiments, the time reference signal GST is not a mere binary trigger signal but corresponds to a data signal having a plurality of bits, wherein the value of the time reference signal GST represents a system time. For example, the time reference signal GST may have 32 or 64 bits.

[0038] Specifically, in various embodiments, the circuit 122 is configured to increase the time reference signal GST in response to the clock signal CLK, such that the time reference signal GST corresponds to the number of "ticks" that have transpired since a given starting date, usually called epoch. Generally, the epoch may be a fixed date, e.g. 1 January 1970 00:00:00 UT similar to the Unix system time or 1 January 1601 00:00:00 UT similar to a Windows based system time, or variable, e.g. from the switch on of the processing system 10a.

[0039] For example, reference can be made to the webpage https://en.wikipedia.org/wiki/System_time for possible encoding schemes of a system time, which may also be applied to the time reference signal GST.

[0040] Accordingly, from a circuit point of view, each tick determined as a function of the clock signal CLK corresponds to a given period/time, such as 100 ns or 1 ms, and the (count) value of the signal GST may be used, e.g., to trigger given operations within the circuits 110. Moreover, by synchronizing the value of the signal GST between plural processing systems 10a (e.g. by using an interface IF shown in Figure 2 and the communication system 20 shown in Figure 1) and by using the same time resolution for the ticks in the various processing systems 10a, the operation of these processing systems 10a may be synchronized.

[0041] As mentioned before, the signal GST is provided to a plurality of circuits 110 of the processing system 10a. Specifically, in various embodiments the signal GST may be provided in reduced resolution to the circuits 110.

[0042] For example, Figure 4 shows an embodiment of such a time reference circuit 122.

[0043] Specifically, as described, in the foregoing the time reference circuit 122 is configured to increase a count value. For example, in Figure 4 is schematically shown a counter circuit 124, configured to increase the signal GST in response to the clock signal CLK.

[0044] For example, Figure 5 shows a possible embodiment of the counter circuit 124.

[0045] In the embodiment considered, the counter circuit 124 comprises a digital counter circuit 1242 configured to increase the value of the signal GST by a given amount INC in response to a clock signal NSC_CLK, e.g. at each rising or falling edge of the clock signal NSC_CLK the digital counter circuit 1242 increase the value of the count value (signal GST) by the value INC. For example, in the embodiment considered, the digital counter circuit 1242 comprises:
  • a register 1248 configured to store the count value (signal GST); and
  • a digital adder circuit 1246 configured to sum the count value (signal GST) provided by the register 1248 and the signal INC, wherein the result is again stored to the register 1248 in response to the clock signal NSC_CLK.


[0046] In various embodiments, the signal INC is programmable and may be stored for this purpose in a register 1244. In various embodiments, the content of the register 1244 is programmable, e.g. by means of the processing unit 102, e.g. via software instructions. For example, in various embodiments, the value of the signal INC is determined as a function of the frequency of the clock signal NSC_CLK in order to implement a nanosecond counter 124. For example, for this purpose, the signal GST may have 64 bits, and for usual clock signals (e.g. in a range between 10MHz and 100MHz), the signal INC may only have 16 bits.

[0047] In various embodiments, the content of the register 1248, i.e. the signal GST, may be readable by the processing unit 102, e.g. via software instructions. Moreover, also the content of the register 1248 may be writeable/programmable, e.g. by means of the processing unit 102, e.g. via software instructions. For example, in this way, the processing unit 102 may set an initial value of the register 1248/signal GST. In fact, after start-up the signal GST indicates essentially the time elapsed since the processing system 10a has been switched on. Conversely, by overwriting the content of the register 1248 may synchronize the signal GST with respect to a starting date/epoch and/or with other processing systems 10.

[0048] As mentioned before, in various embodiments, the register may store 64 bits. However, often the processing unit 102 may only support 32 bits read and write accesses. In this, case the processing unit 102 needs to execute two read or write accesses in order to read or write the content of the register 1248. However, in the meantime the content of the register 1248 may already change.

[0049] Accordingly, in various embodiments, the counter circuit 124 may comprise a further register or latch 1250 configured to store at least part of the content of the register 1248 when a read or write access to the signal GST is performed. For example, once the processing unit 102 requests a read access to the upper or lower 32 bits of the signal GST (as indicated schematically by a signal RW), the register or latch 1250 may store the content of all bits of the signal GST or only the respective lower or upper 32 bits of the signal GST currently not read. Next, when the processing unit 102 requests a read access to the remaining lower or upper 32 bits of the signal GST, the respective bits may be read from the register or latch 1250.

[0050] Generally, the clock signal NSC_CLK may correspond directly to the clock signal CLK shown in Figure 4. Conversely, in the embodiment considered, the counter circuit 124 supports a plurality of clock signals CLK1..CLKk. In this case, the counter circuit 124 may comprise a multiplexer 1240 configured to select one of the clock signals CLK1..CLKk as clock signal NSC_CLK as a function of a selection signal CLK_SEL. In various embodiments, also the signal CLK_SEL may be programmable (e.g. be stored the value of the signal CLK_SEL in a register), e.g. by means of the processing unit 102, e.g. via software instructions.

[0051] Figure 4 shows also that the time reference circuit 122 may also comprise a time base distribution circuit 126. Specifically, the circuit 126 is configured to generate a plurality of time base signals TBI0..TBIn, wherein each of the time base signals TBI0..TBIn is provided to one or more respective circuits 110 of the processing system 10a.

[0052] In various embodiments, one or more of the circuits 110 may be selectable, e.g. by means of a suitable programming of the processing unit 102 or by means of configuration data of the processing system 10a which are read during the start-up of the processing system 10a.

[0053] For example, a time base signal TBI0 may be provided always to the processing unit 102 and/or one or more time base signals TBI1..TBIn may be provided to respective resources 106 of the processing system 10a.

[0054] Accordingly, as schematically shown in Figures 6A and 6B, in various embodiments, the processing unit 102 may be interfaced with the time reference circuit 122 via two interfaces.

[0055] Specifically, as shown in Figure 6A, the processing unit 102 may be connected to the time reference circuit 122 via a system bus 108, e.g. used to connect the resources 106 to the processing system 102. For example, such a system bus may include one or more Advanced Microcontroller Bus Architecture (AMBA) buses, such as an AMBA High-performance Bus (AHB). Accordingly, in various embodiments, a microprocessor 102 may read the content of the register 1248/signal GST via conventional software instructions, e.g. via an operating system OS of the processing unit 102, by using the address associated with the register 1248/signal GST.

[0056] Conversely, a lot of modern microprocessors also include an internal Time Stamp Counter (TSC), which is e.g. included in x86 processors since the Pentium. As shown in Figure 6B, in this case, one of the time base signal, e.g. TBI0, may correspond to the signal of the Time Stamp Counter TSC.

[0057] Substantially, while in Figure 6A the software instruct has to access a hardware resource of the processing system 10a, which has to be routed through the bus system 108, the access in Figure 6B occurs to a (virtual) internal resource of the microprocessor 102.

[0058] As described in the foregoing, one or more time base signals, e.g. TBI1..TBIn are provided to respective (e.g. programmable) resources 106 of the processing system 10a. For example, this is schematically shown in Figure 7, wherein:
  • a time base signal TBI1 is provided to an analog-to-digital converter ADC of the processing system 10a; and/or
  • a time base signal TBI2 is provided to first communication interface IF1 of the processing system 10a, such as a SPI interface; and/or
  • a time base signal TBI3 is provided to second communication interface IF2 of the processing system 10a, such as a CAN bus interface.


[0059] Thus, in the embodiments considered, one or more of the resource 106 of the processing system 10a receive directly a time base signal (TBI0..TBIn) indicative of the global system time GST.

[0060] Accordingly, these one or more resources 106 directly store the value of the respective time base signal in response to given events, e.g. when generating a respective interrupt for the processing unit 102.

[0061] This is schematically shown in Figure 7, wherein each (or at least one) of the resources 106 receiving a time base signal comprise a respective register for storing the value of the respective time base signal, e.g.:
  • the analog-to-digital converter ADC may comprise a register REG1 for storing the content of the time base signal TBI1;
  • the interface IF1 may comprise a register REG2 for storing the content of the time base signal TBI2; and
  • the interface IF2 may comprise a register REG3 for storing the content of the time base signal TBI3.


[0062] The processing system 10a is thus configured that the processing unit 102 reads the content of these registers (REG1, REG2, REG3). Accordingly, in this way, the time stamp is stored directly at a hardware level when the respective event is generated, thereby avoiding that the processing unit 102 has to obtain separately, e.g. via software instructions (see also Figures 6A and 6B), a respective time stamp.

[0063] For example, Figure 8 shows a possible embodiment of the electronic system of a vehicle 30. As described with respect to Figure 1, in this case a plurality of processing systems 10a, 10b, 10c and 10d are connected to a communication system 20, such as a CAN bus.

[0064] For example, in this architecture the blocks of the processing system 10a of Figure 7 may be integrated in an integrated circuit, wherein:
  • the analog-to-digital converter ADC is connected to an analog sensor AS; and/or
  • the communication interface IF1 is connected to a digital sensor DS, and/or
  • the communication interface IF2 is connected to the communications system 20.


[0065] For example, in such a processing system 10a, the analog-to-digital converter ADC may store the value of the respective time base signal TBI1 to the register REG1 when an analog-to-digital conversion has been completed. Optionally, the analog-to-digital converter ADC may generate (preferably simultaneously) an interrupt for the processing unit 102.

[0066] Similarly, the interface IF1 may store the value of the respective time base signal TBI2 to the register REG2 when a response has been received from the digital sensor DS. Optionally, the interface IF1 may generate (preferably simultaneously) an interrupt for the processing unit 102.

[0067] Finally, the interface IF2 may store the value of the respective time base signal TBI3 to the register REG3 when a data-packet has been received via the communication system 20, e.g. from another processing system 10 connected to the communication system 20. Optionally, the interface IF2 may generate (preferably simultaneously) an interrupt for the processing unit 102.

[0068] Accordingly, once the processing unit 102 determines a given event of one of the resources 106, e.g. via a respective interrupt or by periodically reading the content of a respective status register, the processing unit 102 may also read (e.g. in addition to the digital sample provided by the converter ADC, the data received by the interface IF1 and/or the data received by the interface IF2) the content of the respective register having stored the time base signal when the event occurred. For example, as shown in Figure 7, in various embodiments, the resources 106, and in particular the registers REG1, REG2, REG3 may be connected for this purpose to the bus 108. Accordingly, in various embodiments, the processing unit 102 may read the content of the registers REG1, REG2, REG3 via software instructions.

[0069] Generally, the various circuits 110 (processing unit 102 and/or resources 106) may require different resolutions of the time signal GST. Accordingly, as shown in Figure 4, each time base signal TBI0..TBIn has associated a respective time base interface circuit 1260..126n configured to generate the respective time base signal TBI0..TBIn as a function of the signal GST.

[0070] For example, in unclaimed embodiments, each of the time base signals TBI0..TBIn is connected to a given resource 110 of the processing system 10a. Thus, knowing the time resolution supported by a given resource 110, each resource 110 may only receive a given number of bits of the time reference signal GST. Thus, the routing of the bits may be fixed at a hardware level within each time base interface circuit 1260..126n, e.g.:
  • the processing unit 102 may receive all 64 bits of the signal GST;
  • the converter ADC may receive 24 bits of the signal GST;
  • the interface IF1 may receive 16 bits of the signal GST; and
  • the interface IF2 may receive 32 bits of the signal GST.


[0071] Conversely, Figure 9 shows an embodiment of a programmable time base interface circuit 126i, which may be used for at least one of the time base interface circuit 1260..126n.

[0072] Specifically, in the embodiment considered, the time base interface circuit 126i receives at input the signal GST having a given number of bits N1 (e.g. 64 bits) and provides at output a respective time base signal TBIi, wherein the time base signal TBIi has the number of bits N2 (e.g. 64, 32, 24 or 16 bits) supported by the respective resource 110 connected to the time base signal TBIi.

[0073] In the embodiment considered, the time base interface circuit 126i comprises moreover a selection circuit 1262, such as a multiplexer, configured to select for the signal TBIi N2 bits of the signal GST as a function of a selection signal CSEL. In various embodiments, the signal CSEL may be programmable (e.g. be stored the value of the signal CSEL in a register), e.g. by means of the processing unit 102, e.g. via software instructions.

[0074] For example, in various embodiments, the signal CSEL may have two bits and the selection circuit 1262 may be configured to use the following mapping for the signal TBIi:
N2CSELSelected bits of GST
16 "00" [9..24]
"01" [13..28]
24 "00" [3..26]
"01" [6..29]
"10" [9..32]
32 "00" [3..34]
"01" [6..37]
"10" [9..40]
64 - [0..63]


[0075] In various embodiments, the time base interface circuit 126i may also support one or more further reference time signals ETB0 and ETB1. For example, in Figure 9 is shown a further multiplexer 1260 with selects as current reference time signal of the time base interface circuit 126i one of the signals GST, ETB0 or ETB1 as a function of a selection signal SSEL, i.e. the selection circuit 1262 receives at input the current reference time signal selected by the multiplexer 1260. In various embodiments, the signal SSEL may be programmable (e.g. be stored the value of the signal SSEL in a register), e.g. by means of the processing unit 102, e.g. via software instructions.

[0076] Generally, in case the further reference time signal has a number of bits being smaller than the number of bits (N1) of the signal GST the missing (e.g. most significant) bits may be set to "0".

[0077] For example, resources 106 of a processing system 10a which often use an external time stamp bus may be a CAN FD (CAN with Flexible Data-Rate) interface, a sigma-delta analog-to-digital converter, a complex ADC, etc.

[0078] Generally, insofar as the further reference time signal may have a different tick time than the signal GST, also the selection implemented within the selection circuit 1262 (as a function of the selection signal CSEL) may change based on whether the reference time signal GST or a further reference time signal (ETB0, ETB1) has been selected.

[0079] In various embodiments, the time reference circuit 122 may also implement further functions.

[0080] For example, Figure 10 shows an embodiment, wherein the time reference circuit 122 may comprise (in addition to the counter circuit 124 and the time base circuit 126) one or more of the following optional circuits:
  • an extended timer circuit 128; and/or
  • an operation time counter circuit 130; and/or
  • a trigger generator circuit 132.


[0081] Generally, these circuits 128, 130 and 132 have in common that they do not receive directly the reference time signal GST, but they are driven via a trigger signal TRIG generated, e.g., by the counter circuit 124.

[0082] Specifically, in various embodiments, the trigger signal TRIG corresponds to the clock signal CLK used by the counter circuit 124, e.g. the signal NSC_CLK shown in Figure 5.

[0083] Conversely, Figure 11 shows an embodiment of a trigger generator circuit 134, which may be included in the counter circuit 124.

[0084] Specifically, in the embodiment considered, the trigger generator circuit 134 implements a pre-scaler for the clock signal CLK/NSC_CLK used by the counter circuit 124. For example, in the embodiment considered, the trigger generator circuit 134 comprises for this purpose a digital counter 1342 which generates a signal COUNTER EXP INT when the counter reaches a given reference value.

[0085] For example, in various embodiments, the counter 1342 is a down-counter which generates the signal COUNTER EXP INT when the count value of the counter 1342 reaches 0. In this case, the counter 1342 may be configured to set the count value again to a reload value COUNTER_RELOAD_VAL. In various embodiments, the signal COUNTER_RELOAD_VAL may be programmable (e.g. be stored the value of the signal COUNTER_RELOAD_VAL in a register), e.g. by means of the processing unit 102, e.g. via software instructions.

[0086] In various embodiments, the trigger generator circuit 134 may be selectively enabled. For example, in the embodiment considered, the trigger generator circuit 134 may be enabled by enabling the counter 1342 via an enable signal COUNTER_EN. In various embodiments, the signal COUNTER_EN may be programmable (e.g. be stored the value of the signal COUNTER_EN in a register), e.g. by means of the processing unit 102, e.g. via software instructions.

[0087] Thus, the trigger signal TRIG may correspond to the signal COUNTER EXP INT which essentially is set each time the clock signal has reached a given number of COUNTER_RELOAD_VAL cycles.

[0088] In various embodiments, the trigger generator circuit 134 is also configured to synchronize at a circuit 1340 the clock signal CLK/NSC_CLK used by the counter circuit 124 with an auxiliary signal AEVENT indicative of a given event, thereby generating a signal AUX_EVENT_SYNCED being set when the clock signal CLK/NSC_CLK is set and the auxiliary signal AEVENT is set.

[0089] In the embodiment considered, the trigger generator circuit 134 may thus comprise a multiplexer configured to select for the trigger signal TRIG either the signal AUX_EVENT_SYNCED or the signal COUNTER EXP INT as a function of a selection signal EVENT_SOURCE_SEL. In various embodiments, the signal EVENT_SOURCE_SEL may be programmable (e.g. be stored the value of the signal EVENT_SOURCE_SEL in a register), e.g. by means of the processing unit 102, e.g. via software instructions.

[0090] Thus, in the embodiment considered, the circuit 124 implements a Base Time Unit (BTU), which essentially comprises a counter 1242, such as a 64-bit nanosecond counter (NSC). Preferably, the time tick granularity of this counter is programmable via the signal INC and should be set based on clock signal NSC_CLK used, such that a single tick period equals to one nanosecond. For example, assuming a clock source frequency of 10MHz, the increment step INC should be (10^9/10^5) = 100 or 0x64. Conversely, the trigger/event generator 134 is configured to generate periodic pulse based on a programmable (e.g. timeout) counter 1342 which runs with the clock signal NSC_CLK.

[0091] As mentioned before, the trigger signal TRIG may be used by the optional circuits 128, 130 and 132.

[0092] For example, Figure 12 shows an embodiment of an extended timer circuit 128.

[0093] Specifically, in the embodiment considered, the extended timer circuit 128 is implemented with a counter circuit 128 configured to generate a time signal ENTP having 80 bits, wherein the bit sequence of the lower 64 bits follows the Network Time Protocol (NTP) format, which is, e.g., described at https://en.wikipedia.org/wiki/ Network_Time_Protocol#Timestamps.

[0094] Specifically, also such a NTP format uses essentially a fist bit-sequence 1280b of 32 bits indicative of the seconds lapsed since the era epoch of 1st January 1900. Conversely, a second bit-sequence 1280c of 32 bits is indicative of the fraction of seconds. Accordingly, the 32-bit (seconds) counter 1280b would overflow in year 2036. To overcome this potential overflow the updated NTPv4 format uses 64-bit for second and 64-bit for fraction of second. But this extended range is essentially useless for typical processing systems 10a, and accordingly only an additional 16-bit overflow counter 1280a is added in the embodiment considered, thereby using essentially a 48-bit second counter (IEEE 1588-2008 implementation).

[0095] In various embodiments, the resolution for the "fraction of seconds" stored is 1 nanosecond. Accordingly, in this case, the counter 1280c should perform a rollover when the respective count value reaches 0x3B9A_C9FF.

[0096] In various embodiments, the extended timer circuit 128 may be driven either via the trigger signal TRIG or directly via the clock signal CLK/NSC_CLK used by the counter circuit 124.

[0097] Accordingly, in various embodiments, also the increment step size ExNTP_INC_STEP for the extended timer circuit 128, in particular the counter 1280c, may be programmable, e.g. by means of the processing unit 102, e.g. via software instructions. For example, when the extended timer circuit 128 uses the clock signal CLK/NSC_CLK having a frequency of 100MHz, the step ExNTP_INC_STEP should be set to 10. Conversely, when the extended timer circuit 128 uses the trigger signal TRIG with a pre-scale value COUNTER_RELOAD_VAL of 4 for the same clock signal CLK/NSC_CLK (100MHz), the step size ExNTP_INC_STEP should be 40.

[0098] In various embodiments, the value of the extended timer circuit 128 may be readable and optionally also writable by means of the processing unit 102, e.g. via software instructions. In case the processing unit 102 has less bits, e.g. only 32, the processing unit 102 may perform plural consecutive accesses to the values of the counter 1280a, 1280b and 1280c. Thus, also in this case may be used a register or latch to store the remaining bits as described with respect to Figure 5 for the counter circuit 124.

[0099] Moreover, in various embodiments, the extended timer circuit 128 may also support a synchronization operation via a synchronization signal SYNC provided by another NTP timer circuit 136, such as the NTP timer of an (external or internal) Ethernet MAC (IEEE 1588-2008) complaint module.

[0100] For example, a possible procedure for synchronizing the extended timer circuit 128 is shown in Figure 13.

[0101] After a start step 1000, the processing unit 102 obtains (e.g. from the module 136) and stores at a step 1002 the 16 (MSB) bits to the counter 1280a.

[0102] At a next step 1004, the processing unit 102 activates the synchronization mode of the extended timer circuit 128, e.g. by sending a suitable command to the extended timer circuit 128. Accordingly, the extended timer circuit 128 will store the signal SYNC to the lower 64 bits, i.e. will overwrite the content of the count values 1280b and 1280c.

[0103] In various embodiments, the processing unit 102 may then obtain at a step 1006 again the 16 MSB from the module 136 and verify at a step 1008 whether the corresponding bits provided by the module 136 changed, e.g. performed an overflow.

[0104] In case the bits changed (output "N" of the verification step 1008), the processing unit 102 may return to the step 1002 for performing a new synchronization operation.

[0105] Conversely, in case the bits did not change (output "Y" of the verification step 1008), the procedure ends at a stop step 1010.

[0106] As mentioned before, the time reference circuit 122 may also comprise an optional trigger generator circuit 132. For example, Figure 14 shows a possible implementation of the trigger generator circuit 132.

[0107] Specifically, in the embodiment considered, the trigger generator circuit 132 receives at input the trigger signal TRIG and generates one or more trigger signals TRIG0..TRIGm.

[0108] For example, in the embodiment considered, the trigger generator circuit 132 comprises at least one trigger generator sub-circuit 1320..132m, wherein each trigger generator sub-circuit is configured to generate one or more respective trigger signals TRIG0..TRIGm.

[0109] For example, Figure 15 shows a possible embodiment of a generic trigger generator sub-circuit 132i.

[0110] In the embodiment considered, the trigger generator sub-circuit 132i essentially comprises a digital counter 1322 configured to increase a respective count value in response to the trigger signal TRIG and the trigger generator sub-circuit 132i is configured to set one or more respective trigger signals TRIGi as a function of the count value of the counter 1322.

[0111] In various embodiments, the counter 1322 does not receive directly the trigger signal TRIG, but the signal TRIG is provided to a further programmable pre-scale circuit 1320 and the counter 1322 is increased in response to the pre-scaled trigger signal TRIG. The respective description of the pre-scale circuit 1342 (see Figure 11) applies also to the pre-scale circuit 1320.

[0112] Accordingly, in various embodiments, each trigger generator sub-circuit 132i may comprise a respective pre-scale circuit 1320 and counter 1322.

[0113] As mentioned before the one or more trigger signals TRIGi of a given trigger generator sub-circuit 132i are generated as a function of the count value of the respective counter 1322.

[0114] Figures 16 and 17 show in this respect two embodiment which may be implemented alternatively or also in combination (e.g. by using a respective mode selection signal).

[0115] Specifically, Figure 16 shows an embodiment, wherein the trigger generator sub-circuit 132i is operated as a timeout counter configured to generate a signal RE when the counter 1322 has counted for a given number of cycles.

[0116] For example, in the embodiment considered, the counter 1322 is operated as a up or down counter and when the counter 1322 reaches a given value (e.g. 0x0000 0000 or 0xFFFF FFFF for a 32 bit counter), the counter 1322 loads a given reload value REL_VAL and generates a reload signal RE. In various embodiments, the signal REL_VAL may be programmable (e.g. be stored the value of the signal REL_VAL in a register 1324), e.g. by means of the processing unit 102, e.g. via software instructions. Similarly, also the count direction (up or down) of the counter 1322 may be programmable.

[0117] Accordingly, in the embodiment considered, the trigger signal TRIGi may correspond to the reload signal RE. In the embodiment considered, the reload signal RE is also stored to a status register 1326 of the trigger generator sub-circuit 132i.

[0118] Conversely, Figure 17 shows an embodiment, wherein the trigger generator sub-circuit 132i is operated as a compare module.

[0119] Specifically, in the embodiment considered, the counter 1322 is again reset to a given start value (typically 0) and the counter 1322 is activated, thereby varying the respective count value. For example, in various embodiments, the counter 1322 may be reset and started via the processing unit 102, e.g. via software instructions. In various embodiments, the count direction (up or down) of the counter 1322 may be programmable.

[0120] In the embodiment the count value of the counter 1322 is provided to one or more comparators 1330. For example in Figure 17 are shown four comparators 13300..13303. Each of the comparators 13300..13303 is configured to compare the count value of the counter 1322 with a respective comparison value COMP_VAL0..COMP_VAL3. In various embodiments, the comparison values COMP_VAL0..COMP_VAL3 may be programmable (e.g. be stored the comparison values COMP_VAL0..COMP_VAL3 in respective registers 13280..13283), e.g. by means of the processing unit 102, e.g. via software instructions.

[0121] Accordingly, in the embodiment considered, each of the comparators 13300..13303 may generate a respective trigger signal TRIGi0..TRIGi3 when the count value of the counter 1322 corresponds to the respective comparison value COMP_VAL0..COMP_VAL3. In the embodiment considered, the values of the trigger signals TRIGi0..TRIGi3 are also stored to respective bits CMP0..CMP3 of a status register 1326 of the trigger generator sub-circuit 132i.

[0122] Generally, the trigger signals provided by the trigger generator sub-circuit 132i may thus be used in various modes, such as:
  • a mere flags which are stored to a status register 1326 of the trigger generator sub-circuit 132i;
  • generate an interrupt for the processing unit 102;
  • generate trigger signals/interrupts for other resources 106 of the processing system 10a, such as starting an A/D conversion, obtaining sensor data from a digital sensor, etc.


[0123] In various embodiments, each of the trigger generator sub-circuit 132i may also be associated with a given circuit 110 (processing unit 102 or resource 106) of the processing system 10a.

[0124] In various embodiments, the use of the trigger signal, such as simple storage to the status register 1326 or also the generation of an interrupt for the processing unit 102 may be programmable.

[0125] As mentioned before, in various embodiments, the time reference circuit 122 may also comprise an operation time counter circuit 130. For example, Figure 18 shows an embodiment of the operation time counter circuit 130.

[0126] In the embodiment considered, the operation time counter circuit 130 comprises at least one counter 13020..1302l, wherein each counter 13020..1302l is configured to generate a respective count value OTC0..OTCl, which may be read (and possibly also written) via the processing unit 102, e.g. via software instructions. Moreover, in various embodiments, each of the counter 13020..1302l may be reset and/or started and/or stopped by the processing unit 102, e.g. via software instructions.

[0127] Generally, each of the counters 13020..1302l may have essentially the architecture of the counter 1242 shown in Figure 5 (possibly also comprising the register or latch 1250 for improving the read access to the count value). In fact, also in this case, each of the counters 13020..1302l is configured to increase the respective count value by a given increase rate, which is programmable via the processing unit 102, e.g. via software instructions.

[0128] Accordingly, with respect to the counter circuit 124 shown in Figure 5, each of the counters 13020..1302l operates in response to the trigger signal TRIG and not directly the clock signal NSC_CLK. However, as also described with respect to the to the extended time circuit 128, in various embodiments also the clock source for the counter 13020..1302l may be chosen between the clock signal NSC_CLK or the trigger signal TRIG. Thus, by setting/programming the increase rate in an appropriate manner, also the counters 13020..1302l may be used as nanoseconds counters (similar to the extended time circuit 128).

[0129] For example, the counters 13020..1302l may be used to monitor the operating time of given application executed by the processing unit 102.

[0130] In various embodiments, the counters 13020..1302l are configured to preserve the respective count values and configuration also over functional reset. For example, this is schematically shown in Figure 19.

[0131] Specifically, in response to a power-on reset or destructive reset at a step 2000, the processing unit 102 may configure at a step 2004 one (or more) of the counter(s) 13020..1302l. For example, the processing unit 102 may read a given initial count value from a non-volatile memory 104 of the processing system 10a and write the initial count value to the selected counter 13020..1302l.

[0132] Accordingly, the selected counter 13020..1302l will wait at a step 2006 for a new count event (as indicated by the trigger signal TRIG or the clock signal NSC_CLK). Specifically, in the absence of a count event (output "N" of the step 2006), the counter returns to the step 2006. Conversely, when a count event is signaled (output "Y" of the step 2006), the counter increases at a step 2008 the count value.

[0133] As schematically shown in Figure 19, in various embodiments, the processing unit 102 may periodically store the count value of the selected counter 13020..1302l. For example, for this purpose the processing unit 102 may verify at a step 2010 whether a given store interval has lapsed. In case the store interval has not elapsed (output "N" of the step 2010), the procedure returns to the step 2006. Conversely, in case store interval has elapsed (output "Y" of the step 2010), the processing unit 102 may overwrite at a step 2012 the initial count value in the non-volatile memory 104 of the processing unit 10a with the current count value of the selected counter 13020..13021, and the procedure returns to the step 2012.

[0134] Accordingly, by storing the count value to a non-volatile memory 104 and reprogramming the count value to the selected counter 13020..13021, the count value may be conserved also after a power-on/destructive reset.

[0135] Conversely, when a function reset occurs at a step 2002, the counters 13020..1302l may already preserve the respective count values and configuration. Accordingly, in this case the step 2004 may be omitted, i.e. the procedure may directly proceed to the step 2006.

[0136] In various embodiments, one or more of the time reference signals (global system time GST and/or the time reference signals TBI0..TBIn) may be transmitted in encoded format.

[0137] For example, this is schematically shown in Figure 20 for the time reference signals TBI0..TBIn. Specifically, as described with respect to Figure 4, each of the time base interface circuit 1260..126n is configured to generate a respective time reference signals TBI0..TBIn, which is provided to a respective circuit 1100..110n (processing unit 102 or resource 106) .

[0138] In the embodiment considered, the reference signals TBI0..TBIn are not transmitted directly to the respective circuit 110, but each time base interface circuit 1260..126n provides the respective time reference signal TBI0..TBIn to an encoder circuit 1380..138n, thereby generating respective encoded time reference signals. Next, each encoder circuit 1380..138n transmits the respective encoded time reference signal via a respective communication channel 1420..142n to a respective decoder circuit 1400..140n. Finally, the decoder circuits 1400..140n decode the respective received encoded time reference signal and provided the decoded time reference signal to the respective circuit 1100..110n.

[0139] For example, the encoder and decoder circuit 1380..138n and 1400..140n may be:
  • Gray code encoders and decoders;
  • error detection and possibly correction encoders and decoders.


[0140] Accordingly, the various solutions described in the foregoing may have one or more of the following features:
  • the counter circuit 124 may be used to implement a nanosecond counter (see e.g. Figure 5);
  • a plurality of additional reference time signals TBI0..TBIn may be generated by the circuit 126, which may be used by one or more resources 106 of the processing system 10a in order to directly store at a hardware level a value indicative of the count value of the counter circuit 124 when given events are detected in the respective resource 106 (see e.g. Figures 6B and 7) ;
  • the additional reference time signals TBI0..TBIn may have a programmable width and/or resolution (see e.g. Figure 9);
  • the additional reference time signals TBI0..TBIn may operate with different clock signal (see e.g. Figure 11);
  • an extended NTP timer 128 may be used which provides the seconds (and fractions of seconds) passed since January 1, 1900 (see e.g. Figure 12);
  • one or more (operational) time counters 13020..1302l may record the execution or lifetime of applications executed by the processing unit 102 (see e.g. Figures 18 and 19); .
  • the trigger generator circuits 1320..132m may be used to generate periodic interrupts for the processing unit 102 or the resources 106 (see e.g. Figure 16);
  • the trigger generator circuits 1320..132m may be used to generate interrupts when the counter value reaches given comparison values (see e.g. Figure 17).


[0141] Accordingly, the solutions disclosed herein uses a high resolution (64-bit) global system time GST, which is provided at a hardware level to the processing unit 102 and/or (in reduced resolution) to one or more resources 106 of the processing system 10a, which thus may store a time stamp in response to given events. This feature enables (e.g. the operating system of) the processing unit 102 to obtain accurate hardware based time stamps instead of coarse software based time stamps. In fact, the captured hardware based time stamp values have a very short and constant delay versus the event which have triggered the time stamp capturing. The time at which the processing unit 102 is processing the hardware time stamp values has thus no influence any more on the accuracy of the time stamp information.

[0142] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.


Claims

1. A processing system (10a) comprising:

- a digital processing unit (102) programmable as a function of a firmware stored to a non-volatile memory (104);

- a first resource (106; ADC) and a second resource (106; IF1) connected to said digital processing unit (102) via a communication system (108), wherein said first resource (106; ADC) comprises a first register (REG1) and said second resource (106; IF1) comprises a second register (REG2);

- a time reference circuit (122) comprising a first digital counter circuit (124) configured to generate, in response to a clock signal (CLK), a system time signal (GST) comprising a plurality of bits indicative of a time tick-count;

characterized in that said processing system (10a) comprises a first and a second time base distribution circuit (126) configured to generate a first time base signal (TBI1) and a second time base signal (TBI2) by selecting a respective subset of the bits of said system time signal (GST), wherein said first time base signal (TBI1) is provided to said first resource (106; ADC) and said second time base signal (TBI2) is provided to said second resource (106; IF1), wherein said first and said second time base distribution circuit (126) are configured to generate said first time base signal (TBI1) and said second time base signal (TBI21), respectively, by selecting (1262):

- a respective first subset of a respective given number of bits of said system time signal (GST) when a respective selection signal (CSEL) has a first value; and

- a respective second subset of the respective given number of bits of said system time signal (GST) when the respective selection signal (CSEL) has a second value, whereby a time resolution of the respective time base signal varies as a function of the respective selection signal (CSEL);

wherein each of said first resource (106; ADC) and said second resource (106; IF1) is configured to:

- detect a respective given event,

- store the respective time base signal (TBI1, TBI2) to the respective register (REG1, REG2) in response to the respective event, and

- signal the respective event to said digital processing unit (102); and

wherein said digital processing unit (102) is adapted to read via said communication system (108):

- in response to an event having been signaled by said first resource (106; ADC), said first time base signal (TBI1) from said first register (REG1), and

- in response to an event having been signaled by said second resource (106; IF1), said second time base signal (TBI2) from said second register (REG2).


 
2. The processing system (10a) according to Claim 1, wherein said first and said second resource (106) are selected from the list of:

- a communication interface (IF), such as a Universal asynchronous receiver/transmitter, Serial Peripheral Interface Bus, Inter-Integrated Circuit, Controller Area Network bus or Ethernet interface, or a debug interface;

- an analog-to-digital converter (AD) or a digital-to-analog converters (DA);

- a digital component (DC), such as a hardware timer, counter or a cryptographic co-processor;

- an analog component (AC), such as a comparator or sensor, such as a temperature sensor; and

- an analog/digital mixed signal component (MSC), such as a PWM (Pulse-Width Modulation) driver.


 
3. The processing system (10a) according to Claim 1 or Claim 2, wherein:

- said first resource (106; ADC) is an analog-to-digital converter (ADC), and wherein said event corresponds to the completion of an analog-to-digital conversion; and/or

- said second resource (106; IF1) is a communication interface (IF1, IF2), and wherein said event corresponds to the reception of data via said communication interface (IF1, IF2).


 
4. The processing system (10a) according to any of the previous claims, wherein said processing system (10a) is a microcontroller, and wherein said digital processing unit (102) is a microprocessor of said microcontroller.
 
5. The processing system (10a) according to any of the previous claims, wherein said first digital counter circuit (124) of said time reference circuit (122) is configured to generate said system time signal (GST) by increasing the value of said system time signal (GST) by a given amount (INC) in response to said clock signal (CLK).
 
6. The processing system (10a) according to Claim 5, wherein said given amount (INC) is programmable by means of said processing unit (102).
 
7. The processing system (10a) according to any of the previous claims, wherein said selection signals (CSEL) are programmable by means of the processing unit (102).
 
8. The processing system (10a) according to any of the previous claims, comprising at least one of:

- an extended timer circuit (128) comprising a second digital counter circuit (1280a, 1280b, 1280c) configured to generate, in response to said clock signal (CLK) or a trigger signal (TRIG) generated as a function of said clock signal (CLK), an extended system time signal (ENTP) comprising a number of bits being greater than the number of bits of said system time signal (GST), wherein said extended system time signal (ENTP) is readable by means of said digital processing unit (102); and/or

- an operation time counter circuit (130) comprising a plurality of third digital counter circuits (13020..1302l) configured to generate, in response to said clock signal (CLK) or a trigger signal (TRIG) generated as a function of said clock signal (CLK), respective count values (OTC0..OTCl), wherein each of said plurality of third digital counter circuits (13020..1302l) is reset, started and stopped by said digital processing unit (102); and/or

- a trigger generator circuit (132) comprising one or more fourth digital counter circuits (1322) configured to generate, in response to said clock signal (CLK) or a trigger signal (TRIG) generated as a function of said clock signal (CLK), at least one trigger signal (TRIG0..TRIGm).


 
9. The processing system (10a) according to any of the previous claims, wherein said digital processing unit (102) is a microprocessor, wherein said time reference circuit (122) comprises a register (1248) configured to store said system time signal (GST), wherein said microprocessor (102) is connected to said time reference circuit (122) via a system bus (108), and wherein said microprocessor (102) is adapted to read the content of said register (1248) via software instructions by using an address associated with said register (1248).
 
10. The processing system (10a) according to Claim 9, wherein said processing system (10a) comprises a further time base distribution circuit (1260) configured to generate a further time base signal (TBI0), wherein said microprocessor comprises a virtual internal Time Stamp Counter, wherein said further time base signal (TBI0) corresponds to the signal of said virtual internal Time Stamp Counter.
 
11. The processing system (10a) according to Claim 9, wherein said register (1248) has 64 bits, wherein said microprocessor (102) only supports 32 bits read and write accesses, wherein said microprocessor (102) is configured to execute two read accesses in order to read the content of said register (1248),

wherein said first digital counter circuit (124) comprises a further register or latch (1250) configured to, once the microprocessor (102) requests a read access to the upper or lower 32 bits of said system time signal (GST), store at least the respective lower or upper 32 bits of the system time signal (GST) currently not read, and

wherein, when the microprocessor (102) requests a read access to the remaining lower or upper 32 bits of the system time signal (GST), the respective bits are read from said further register or latch (1250).


 
12. An integrated circuit, such as a micro-controller, comprising a processing system (10a) according to any of Claims 1 to 11.
 
13. A device, such as a vehicle, comprising a plurality of processing systems (10a) according to any of Claims 1 to 11.
 
14. A method of operating a processing system (10a) according to any of Claim 1 to 11, comprising:

- generating via said time reference circuit (122) said system time signal (GST);

- generating via said first and said second time base distribution circuit (126) said first time base signal (TBI1) and said second time base signal (TBI2);

- detecting via said first resource (106) a given event;

- in response to said event, storing said first time base signal (TBI1) to said first register (REG1);

- signaling said event to said digital processing unit (102); and

- reading via said digital processing unit (102) said first time base signal (TBI1) from said first register (REG1).


 


Ansprüche

1. Verarbeitungssystem (10a), umfassend:

- eine digitale Verarbeitungseinheit (102), die als eine Funktion einer in einem nichtflüchtigen Speicher (104) gespeicherten Firmware programmierbar ist;

- eine erste Ressource (106; ADC) und eine zweite Ressource (106; IF1), die über ein Kommunikationssystem (108) mit der digitalen Verarbeitungseinheit (102) verbunden sind, wobei die erste Ressource (106; ADC) ein erstes Register (REG1) umfasst und die zweite Ressource (106; IF1) ein zweites Register (REG2) umfasst;

- eine Zeitreferenzschaltung (122), die eine erste digitale Zählerschaltung (124) umfasst, die konfiguriert ist, als Reaktion auf ein Taktsignal (CLK) ein Systemzeitsignal (GST) zu erzeugen, das eine Vielzahl von Bits umfasst, die eine Zeit-Tick-Zählung angeben;

dadurch gekennzeichnet, dass das Verarbeitungssystem (10a) eine erste und eine zweite Zeitbasisverteilungsschaltung (126) umfasst, die konfiguriert ist, ein erstes Zeitbasissignal (TBI1) und ein zweites Zeitbasissignal (TBI2) durch Auswählen eines jeweiligen Teilsatzes der Bits des Systemzeitsignals (GST) zu erzeugen, wobei das erste Zeitbasissignal (TBI1) der ersten Ressource (106; ADC) bereitgestellt wird und das zweite Zeitbasissignal (TBI2) der zweiten Ressource (106; IF1) bereitgestellt wird, wobei die erste und die zweite Zeitbasisverteilungsschaltung (126) konfiguriert sind, das erste Zeitbasissignal (TBI1) bzw. das zweite Zeitbasissignal (TBI2) zu erzeugen durch Auswählen (1262) von:

- einem jeweiligen ersten Teilsatz einer jeweiligen gegebenen Anzahl von Bits des Systemzeitsignals (GST), wenn ein jeweiliges Auswahlsignal (CSEL) einen ersten Wert aufweist; und

- einem jeweiligen zweiten Teilsatz der jeweiligen gegebenen Anzahl von Bits des Systemzeitsignals (GST), wenn das jeweilige Auswahlsignal (CSEL) einen zweiten Wert aufweist, wobei eine Zeitauflösung des jeweiligen Zeitbasissignals als eine Funktion des jeweiligen Auswahlsignals (CSEL) variiert;

wobei sowohl die erste Ressource (106; ADC) als auch die zweite Ressource (106; IF1) konfiguriert ist zum:

- Detektieren eines jeweiligen gegebenen Ereignisses,

- Speichern des jeweiligen Zeitbasissignals (TBI1, TBI2) in das jeweilige Register (REG1, REG2) als Reaktion auf das jeweilige Ereignis, und

- Signalisieren des jeweiligen Ereignisses an die digitale Verarbeitungseinheit (102); und

wobei die digitale Verarbeitungseinheit (102) eingerichtet ist, über das Kommunikationssystem (108) zu lesen:

- als Reaktion darauf, dass ein Ereignis durch die erste Ressource (106; ADC) signalisiert wurde, das erste Zeitbasissignal (TBI1) aus dem ersten Register (REG1), und

- als Reaktion darauf, dass ein Ereignis durch die zweite Ressource (106; IF1) signalisiert wurde, das zweite Zeitbasissignal (TBI2) aus dem zweiten Register (REG2).


 
2. Verarbeitungssystem (10a) nach Anspruch 1, wobei die erste und die zweite Ressource (106) aus der folgenden Liste ausgewählt werden:

- eine Kommunikationsschnittstelle (IF), wie etwa eine Universal-Asynchronous-Receiver/Transmitter-, Serial-Peripheral-Interface-Bus-, Inter-Integrated-Circuit-, Controller-Area-Network-Bus- oder Ethernet-Schnittstelle oder eine Debug-Schnittstelle;

- einen Analog-Digital-Wandler (AD) oder einen Digital-Analog-Wandler (DA);

- eine digitale Komponente (DC), wie etwa ein Hardware-Timer, ein Zähler oder ein kryptografischer Coprozessor;

- eine analoge Komponente (AC), wie etwa ein Komparator oder ein Sensor, wie etwa ein Temperatursensor; und

- eine analoge/digitale Mischsignalkomponente (MSC), wie etwa ein PWM(Pulsweitenmodulation)-Treiber.


 
3. Verarbeitungssystem (10a) nach Anspruch 1 oder Anspruch 2, wobei:

- die erste Ressource (106; ADC) ein Analog-Digital-Wandler (ADC) ist, und wobei das Ereignis dem Abschluss einer Analog-Digital-Umwandlung entspricht; und/oder

- die zweite Ressource (106; IF1) eine Kommunikationsschnittstelle (IF1, IF2) ist, und wobei das Ereignis dem Empfang von Daten über die Kommunikationsschnittstelle (IF1, IF2) entspricht.


 
4. Verarbeitungssystem (10a) nach einem der vorstehenden Ansprüche, wobei das Verarbeitungssystem (10a) ein Mikrocontroller ist, und wobei die digitale Verarbeitungseinheit (102) ein Mikroprozessor des Mikrocontrollers ist.
 
5. Verarbeitungssystem (10a) nach einem der vorstehenden Ansprüche, wobei die erste digitale Zählerschaltung (124) der Zeitreferenzschaltung (122) konfiguriert ist, das Systemzeitsignal (GST) durch Erhöhen des Wertes des Systemzeitsignals (GST) um einen gegebenen Betrag (INC) als Reaktion auf das Taktsignal (CLK) zu erzeugen.
 
6. Verarbeitungssystem (10a) nach Anspruch 5, wobei der gegebene Betrag (INC) mittels der Verarbeitungseinheit (102) programmierbar ist.
 
7. Verarbeitungssystem (10a) nach einem der vorstehenden Ansprüche, wobei die Auswahlsignale (CSEL) mittels der Verarbeitungseinheit (102) programmierbar sind.
 
8. Verarbeitungssystem (10a) nach einem der vorstehenden Ansprüche, umfassend mindestens eines von:

- einer erweiterten Timer-Schaltung (128), die eine zweite digitale Zählerschaltung (1280a, 1280b, 1280c) umfasst, die konfiguriert ist, als Reaktion auf das Taktsignal (CLK) oder ein Auslösesignal (TRIG), das als eine Funktion des Taktsignals (CLK) erzeugt wird, ein erweitertes Systemzeitsignal (ENTP) zu erzeugen, das eine Anzahl von Bits umfasst, die größer ist als die Anzahl von Bits des Systemzeitsignals (GST), wobei das erweiterte Systemzeitsignal (ENTP) mittels der digitalen Verarbeitungseinheit (102) lesbar ist; und/oder

- einer Betriebszeitzählerschaltung (130), die eine Vielzahl dritter digitaler Zählerschaltungen (13020..13021) umfasst, die konfiguriert sind, als Reaktion auf das Taktsignal (CLK) oder ein Auslösesignal (TRIG), das als eine Funktion des Taktsignals (CLK) erzeugt wird, jeweilige Zählwerte (OTC0..OTC1) zu erzeugen, wobei jede der Vielzahl dritter digitaler Zählerschaltungen (13020..13021) durch die digitale Verarbeitungseinheit (102) zurückgesetzt, gestartet und gestoppt wird; und/oder

- einer Auslösegeneratorschaltung (132), die eine oder mehrere vierte digitale Zählerschaltungen (1322) umfasst, die konfiguriert sind, als Reaktion auf das Taktsignal (CLK) oder ein Auslösesignal (TRIG), das als eine Funktion des Taktsignals (CLK) erzeugt wird, mindestens ein Auslösesignal (TRIG0..TRIGm) zu erzeugen.


 
9. Verarbeitungssystem (10a) nach einem der vorstehenden Ansprüche, wobei die digitale Verarbeitungseinheit (102) ein Mikroprozessor ist, wobei die Zeitreferenzschaltung (122) ein Register (1248) umfasst, das konfiguriert ist, das Systemzeitsignal (GST) zu speichern, wobei der Mikroprozessor (102) über einen Systembus (108) mit der Zeitreferenzschaltung (122) verbunden ist und wobei der Mikroprozessor (102) eingerichtet ist, den Inhalt des Registers (1248) über Softwareanweisungen unter Verwendung einer Adresse, die mit dem Register (1248) assoziiert ist, zu lesen.
 
10. Verarbeitungssystem (10a) nach Anspruch 9, wobei das Verarbeitungssystem (10a) eine weitere Zeitbasisverteilungsschaltung (1260) umfasst, die konfiguriert ist, ein weiteres Zeitbasissignal (TBI0) zu erzeugen, wobei der Mikroprozessor einen virtuellen internen Zeitstempelzähler umfasst, wobei das weitere Zeitbasissignal (TBI0) dem Signal des virtuellen internen Zeitstempelzählers entspricht.
 
11. Verarbeitungssystem (10a) nach Anspruch 9, wobei das Register (1248) 64 Bits aufweist, wobei der Mikroprozessor (102) nur 32-Bits-Lese- und -Schreibzugriffe unterstützt, wobei der Mikroprozessor (102) konfiguriert ist, zwei Lesezugriffe auszuführen, um den Inhalt des Registers (1248) zu lesen,

wobei die erste digitale Zählerschaltung (124) ein weiteres Register oder Latch (1250) umfasst, das konfiguriert ist, sobald der Mikroprozessor (102) einen Lesezugriff auf die oberen oder unteren 32 Bits des Systemzeitsignals (GST) anfordert, zumindest die jeweiligen unteren oder oberen 32 Bits des Systemzeitsignals (GST), die gegenwärtig nicht gelesen werden, zu speichern, und

wobei, wenn der Mikroprozessor (102) einen Lesezugriff auf die verbleibenden unteren oder oberen 32 Bits des Systemzeitsignals (GST) anfordert, die jeweiligen Bits aus dem weiteren Register oder Latch (1250) gelesen werden.


 
12. Integrierte Schaltung, wie etwa ein Mikrocontroller, die ein Verarbeitungssystem (10a) nach einem der Ansprüche 1 bis 11 umfasst.
 
13. Vorrichtung, wie etwa ein Fahrzeug, die eine Vielzahl von Verarbeitungssystemen (10a) nach einem der Ansprüche 1 bis 11 umfasst.
 
14. Verfahren zum Betreiben eines Verarbeitungssystems (10a) nach einem der Ansprüche 1 bis 11, umfassend:

- Erzeugen des Systemzeitsignals (GST) mittels der Zeitreferenzschaltung (122);

- Erzeugen des ersten Zeitbasissignals (TBI1) und des zweiten Zeitbasissignals (TBI2) mittels der ersten und der zweiten Zeitbasisverteilungsschaltung (126);

- Detektieren eines gegebenen Ereignisses mittels der ersten Ressource (106);

- als Reaktion auf das Ereignis, Speichern des ersten Zeitbasissignals (TBI1) in das erste Register (REG1);

- Signalisieren des Ereignisses an die digitale Verarbeitungseinheit (102); und

- Lesen des ersten Zeitbasissignals (TBI1) aus dem ersten Register (REG1) mittels der digitalen Verarbeitungseinheit (102).


 


Revendications

1. Système de traitement (10a) comprenant :

- une unité de traitement numérique (102) programmable en fonction d'un micrologiciel stocké dans une mémoire non volatile (104) ;

- une première ressource (106 ; ADC) et une deuxième ressource (106 ; IF1) connectées à ladite unité de traitement numérique (102) par l'intermédiaire d'un système de communication (108), ladite première ressource (106 ; ADC) comprenant un premier registre (REG1) et ladite deuxième ressource (106 ; IF1) comprenant un deuxième registre (REG2) ;

- un circuit de référence de temps (122) comprenant un premier circuit compteur numérique (124) configuré pour générer, en réponse à un signal d'horloge (CLK), un signal de temps système (GST) comprenant une pluralité de bits indicatifs d'un compte de tics de temps ;

caractérisé en ce que ledit système de traitement (10a) comprend un premier et un deuxième circuit de distribution de base de temps (126) configurés pour générer un premier signal de base de temps (TBI1) et un deuxième signal de base de temps (TBI2) par sélection d'un sous-ensemble respectif des bits dudit signal de temps système (GST), ledit premier signal de base de temps (TBI1) étant fourni à ladite première ressource (106 ; ADC) et ledit deuxième signal de base de temps (TBI2) étant fourni à ladite deuxième ressource (106 ; IF1), ledit premier et ledit deuxième circuit de distribution de base de temps (126) étant configurés pour générer ledit premier signal de base de temps (TBI1) et ledit deuxième signal de base de temps (TBI21), respectivement, par sélection (1262) :

- d'un premier sous-ensemble respectif d'un nombre donné respectif de bits dudit signal de temps système (GST) quand un signal de sélection respectif (CSEL) a une première valeur ; et

- d'un deuxième sous-ensemble respectif du nombre donné respectif de bits dudit signal de temps système (GST) quand le signal de sélection respectif (CSEL) a une deuxième valeur, moyennant quoi une résolution temporelle du signal de base de temps respectif varie en fonction du signal de sélection respectif (CSEL) ;

dans lequel chacune de ladite première ressource (106 ; ADC) et de ladite deuxième ressource (106 ; IF1) est configurée pour :

- détecter un événement donné respectif,

- stocker le signal de base de temps respectif (TBI1, TBI2) dans le registre respectif (REG1, REG2) en réponse à l'événement respectif, et

- signaler l'événement respectif à ladite unité de traitement numérique (102) ; et

dans lequel ladite unité de traitement numérique (102) est conçue pour lire par l'intermédiaire dudit système de communication (108) :

- en réponse à un événement ayant été signalé par ladite première ressource (106 ; ADC), ledit premier signal de base de temps (TBI1) dans ledit premier registre (REG1), et

- en réponse à un événement ayant été signalé par ladite deuxième ressource (106 ; IF1), ledit deuxième signal de base de temps (TBI2) dans ledit deuxième registre (REG2).


 
2. Système de traitement (10a) selon la revendication 1, dans lequel ladite première et ladite deuxième ressource (106) sont sélectionnées dans la liste constituée :

- d'une interface de communication (IF), telle qu'une interface d'émetteur/récepteur asynchrone universel, de bus d'interface périphérique série, inter-circuits intégrés, de bus de réseau de contrôleurs ou Ethernet, ou d'une interface de débogage ;

- d'un convertisseur analogique-numérique (AD) ou d'un convertisseur numérique-analogique (DA) ;

- d'un composant numérique (DC), tel qu'un temporisateur/compteur matériel ou un coprocesseur cryptographique ;

- d'un composant analogique (AC), tel qu'un comparateur ou capteur, tel qu'un capteur de température ; et

- d'un composant à signaux mixtes (MSC) analogique/numérique, tel qu'un circuit de pilotage PWM (modulation d'impulsions en durée).


 
3. Système de traitement (10a) selon la revendication 1 ou la revendication 2, dans lequel :

- ladite première ressource (106 ; ADC) est un convertisseur analogique-numérique (ADC), et dans lequel ledit événement correspond à l'achèvement d'une conversion analogique-numérique ; et/ou

- ladite deuxième ressource (106 ; IF1) est une interface de communication (IF1, IF2), et dans lequel ledit événement correspond à la réception de données par l'intermédiaire de ladite interface de communication (IF1, IF2).


 
4. Système de traitement (10a) selon n'importe laquelle des revendications précédentes, ledit système de traitement (10a) étant un microcontrôleur, et dans lequel ladite unité de traitement numérique (102) est un microprocesseur dudit microcontrôleur.
 
5. Système de traitement (10a) selon n'importe laquelle des revendications précédentes, dans lequel ledit premier circuit compteur numérique (124) dudit circuit de référence de temps (122) est configuré pour générer ledit signal de temps système (GST) par accroissement de la valeur dudit signal de temps système (GST) d'une quantité donnée (INC) en réponse audit signal d'horloge (CLK).
 
6. Système de traitement (10a) selon la revendication 5, dans lequel ladite quantité donnée (INC) est programmable au moyen de ladite unité de traitement (102).
 
7. Système de traitement (10a) selon n'importe laquelle des revendications précédentes, dans lequel lesdits signaux de sélection (CSEL) sont programmables au moyen de l'unité de traitement (102).
 
8. Système de traitement (10a) selon n'importe laquelle des revendications précédentes, comprenant au moins un élément parmi :

- un circuit temporisateur étendu (128) comprenant un deuxième circuit compteur numérique (1280a, 1280b, 1280c) configuré pour générer, en réponse audit signal d'horloge (CLK) ou à un signal déclencheur (TRIG) généré en fonction dudit signal d'horloge (CLK), un signal de temps système étendu (ENTP) comprenant un nombre de bits qui est supérieur au nombre de bits dudit signal de temps système (GST), ledit signal de temps système étendu (ENTP) étant lisible au moyen de ladite unité de traitement numérique (102) ; et/ou

- un circuit compteur de temps d'opération (130) comprenant une pluralité de troisièmes circuits compteurs numériques (13020..13021) configurés pour générer, en réponse audit signal d'horloge (CLK) ou à un signal déclencheur (TRIG) généré en fonction dudit signal d'horloge (CLK), des valeurs de compte respectives (OTC0..OTCl), chaque circuit compteur de ladite pluralité de troisièmes circuits compteurs numériques (13020..1302l) étant réinitialisé, démarré et arrêté par ladite unité de traitement numérique (102) ; et/ou

- un circuit générateur de déclencheur (132) comprenant un ou plusieurs quatrièmes circuits compteurs numériques (1322) configurés pour générer, en réponse audit signal d'horloge (CLK) ou à un signal déclencheur (TRIG) généré en fonction dudit signal d'horloge (CLK), au moins un signal déclencheur (TRIG0..TRIGm).


 
9. Système de traitement (10a) selon n'importe laquelle des revendications précédentes, dans lequel ladite unité de traitement numérique (102) est un microprocesseur, dans lequel ledit circuit de référence de temps (122) comprend un registre (1248) configuré pour stocker ledit signal de temps système (GST), dans lequel ledit microprocesseur (102) est connecté audit circuit de référence de temps (122) par l'intermédiaire d'un bus système (108), et dans lequel ledit microprocesseur (102) est conçu pour lire le contenu dudit registre (1248) par l'intermédiaire d'instructions logicielles par utilisation d'une adresse associée audit registre (1248).
 
10. Système de traitement (10a) selon la revendication 9, ledit système de traitement (10a) comprenant un circuit de distribution de base de temps supplémentaire (1260) configuré pour générer un signal de base de temps supplémentaire (TBI0), dans lequel ledit microprocesseur comprend un compteur d'horodatage interne virtuel, dans lequel ledit signal de base de temps supplémentaire (TBI0) correspond au signal dudit compteur d'horodatage interne virtuel.
 
11. Système de traitement (10a) selon la revendication 9, dans lequel ledit registre (1248) a 64 bits, dans lequel ledit microprocesseur (102) prend seulement en charge des accès en lecture et en écriture à 32 bits, dans lequel ledit microprocesseur (102) est configuré pour exécuter deux accès en lecture afin de lire le contenu dudit registre (1248),

dans lequel ledit premier circuit compteur numérique (124) comprend un registre ou verrou supplémentaire (1250) configuré pour, une fois que le microprocesseur (102) a demandé un accès en lecture aux 32 bits supérieurs ou inférieurs dudit signal de temps système (GST), stocker au moins les 32 bits inférieurs ou supérieurs respectifs du signal de temps système (GST) actuellement non lus, et

dans lequel, lorsque le microprocesseur (102) demande un accès en lecture aux 32 bits inférieurs ou supérieurs restants du signal de temps système (GST), les bits respectifs sont lus dans ledit registre ou verrou supplémentaire (1250).


 
12. Circuit intégré, tel qu'un microcontrôleur, comprenant un système de traitement (10a) selon n'importe laquelle des revendications 1 à 11.
 
13. Dispositif, tel qu'un véhicule, comprenant une pluralité de systèmes de traitement (10a) selon n'importe laquelle des revendications 1 à 11.
 
14. Procédé de fonctionnement d'un système de traitement (10a) selon n'importe laquelle des revendications 1 à 11, comprenant :

- la génération, par l'intermédiaire dudit circuit de référence de temps (122), dudit signal de temps système (GST) ;

- la génération, par l'intermédiaire dudit premier et dudit deuxième circuit de distribution de base de temps (126), dudit premier signal de base de temps (TBI1) et dudit deuxième signal de base de temps (TBI2) ;

- la détection, par l'intermédiaire de ladite première ressource (106), d'un événement donné ;

- en réponse audit événement, le stockage dudit premier signal de base de temps (TBI1) dans ledit premier registre (REG1) ;

- la signalisation dudit événement à ladite unité de traitement numérique (102) ; et

- la lecture, par l'intermédiaire de ladite unité de traitement numérique (102), dudit premier signal de base de temps (TBI1) dans ledit premier registre (REG1).


 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description