(19)
(11)EP 3 779 943 A1

(12)EUROPEAN PATENT APPLICATION
published in accordance with Art. 153(4) EPC

(43)Date of publication:
17.02.2021 Bulletin 2021/07

(21)Application number: 18889953.8

(22)Date of filing:  07.12.2018
(51)Int. Cl.: 
G09G 3/20  (2006.01)
(86)International application number:
PCT/CN2018/119772
(87)International publication number:
WO 2019/196447 (17.10.2019 Gazette  2019/42)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 13.04.2018 CN 201810329788

(71)Applicants:
  • BOE TECHNOLOGY GROUP CO., LTD.
    Beijing 100015 (CN)
  • Chengdu BOE Optoelectronics Technology Co., Ltd.
    Hi-tech Development Zone Chengdu Sichuan 611731 (CN)

(72)Inventors:
  • HUANG, Weiyun
    Beijing 100176 (CN)
  • KO, Youngyik
    Beijing 100176 (CN)

(74)Representative: Lavoix 
Bayerstrasse 83
80335 München
80335 München (DE)

  


(54)GATE DRIVE MODULE, GATE DRIVE CONTROL METHOD, AND DISPLAY APPARATUS


(57) The present disclosure provides a gate driving module, including a gate driving circuit and a control circuit. The gate driving circuit includes a first shift register sub-circuitry and a second shift register sub-circuitry connected to each other in a cascaded manner. A first shift register unit is connected to a corresponding gate line at a first display sub-region. A second shift register unit is connected to a clock signal line and a corresponding gate line at a second display sub-region, and configured to generate a gate driving signal in accordance with a voltage signal on the clock signal line and output the gate driving signal to the gate line. The control circuit is configured to, when a display panel is in a non-planar state and the second shift register unit is performing a gate driving scanning operation, apply a first voltage signal to the clock signal line, so as to enable the second shift register unit to output a signal for turning off a transistor corresponding to the gate line.




Description

CROSS-REFERENCE TO RELATED APPLICATION



[0001] The present application claims a priority of the Chinese patent application No.201810329788.9 filed on April 13, 2018, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD



[0002] The present disclosure relates to the field of display driving technology, in particular to a gate driving module, a gate driving control method and a display device.

BACKGROUND



[0003] Flexible display panel is foldable and may be applied to a foldable terminal, e.g., a foldable mobile phone or a foldable flat-panel computer. Usually, when the foldable terminal is unfolded, it is necessary to display an image in a double-sided manner, and when the foldable terminal is folded, it is merely necessary to display an image in a single-sided manner. In order to reduce the power consumption, it is necessary to turn off shift register units at a region where no image is to be displayed. A conventional scheme is to provide at least two gate driving circuits for at least two display sub-regions of a display panel when the display panel is folded. In this way, each display sub-region is controlled by one gate driving circuit. However, at this time, a driving Integrated Circuit (IC) needs to support more clock signals and start signals. In addition, the at least two gate driving circuits are not connected to each other in cascaded manner, so during a gate driving scanning operation, clock signal mismatch may easily occur, and there may exist differences between gate loadings for the at least two gate driving circuits. As a result, such a phenomenon as split-screen may occur at the at least two display sub-regions when an image is displayed in a full-screen mode.

SUMMARY



[0004] In one aspect, the present disclosure provides in some embodiments a gate driving module for use in a display panel provided with a display region. When the display panel is in a non-planar state, the display region includes a plurality of display sub-regions. The gate driving module includes a gate driving circuit. The gate driving circuit includes a plurality of shift register sub-circuitries connected to each other in a cascaded manner. A first shift register sub-circuitry of the plurality of shift register sub-circuitries includes at least one level of first shift register unit, and a second shift register sub-circuitry of the plurality of shift register sub-circuitries includes at least one level of second shift register unit. The gate driving module further includes a control circuit. Each first shift register unit of the at least one level of first shift register unit is connected to a gate line at a first display sub-region of the plurality of display sub-regions. Each second shift register unit of the at least one level of second shift register unit is connected to a clock signal line and a gate line arranged at a second display sub-region of the plurality of display sub-regions, and configured to generate a gate driving signal in accordance with a voltage signal on the clock signal line and output the gate driving signal to the gate line. The control circuit is configured to, when the display panel is in the non-planar state and one second shift register unit of the at least one level of second shift register unit is performing a gate driving scanning operation, apply a first voltage signal to the clock signal line, so as to enable the second shift register unit to control the gate line to output a signal for turning off a transistor corresponding to the gate line.

[0005] In a possible embodiment of the present disclosure, when the display panel is in the non-planar state, the display panel is folded, and the display region is divided by one or more folding axes into a plurality of display sub-regions; or when the display panel is the non-planar state, the display panel is curled.

[0006] In a possible embodiment of the present disclosure, there are one folding axis, one first shift register sub-circuitry and one second shift register sub-circuitry. A gate driving signal output end of a last-level first shift register unit of the first shift register sub-circuitry is connected to an input end of a first-level second shift register unit of the second shift register sub-circuitry, and a gate driving signal output end of the first-level second shift register unit of the second shift register sub-circuitry is connected to a resetting end of the last-level first shift register unit of the first shift register sub-circuitry.

[0007] In a possible embodiment of the present disclosure, there are two folding axes, two first register sub-circuitries, two first display sub-regions corresponding to the first register unit sub-circuitries respectively, one second shift register sub-circuitry and one second display sub-region. A gate driving signal output end of a last-level first shift register unit of a first one of the first shift register sub-circuitries is connected to an input end of a first-level second shift register unit of the second shift register sub-circuitry, a gate driving signal output end of the first-level second shift register unit of the second shift register sub-circuitry is connected to a resetting end of the last-level first shift register unit of the first one of the first shift register sub-circuitries, a gate driving signal output end of the last-level second shift register unit of the second shift register sub-circuitry is connected to an input end of a first-level first shift register unit of a second one of the first shift register sub-circuitries, and a gate driving signal output end of the first-level first shift register unit of the second one of the first shift register sub-circuitries is connected to a resetting end of the last-level second shift register unit of the second shift register sub-circuitry.

[0008] In a possible embodiment of the present disclosure, the first shift register unit is further connected to the clock signal line, and configured to generate a gate driving signal in accordance with the voltage signal on the clock signal line and output the gate driving signal to the gate line connected to the first shift register unit. The control circuit is further configured to, when the display panel is in the non-planar state and the first shift register unit is performing a gate driving scanning operation, apply the clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line.

[0009] In a possible embodiment of the present disclosure, the control circuit is further configured to, when the display panel is in the non-planar state, apply the clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line when the first shift register unit is performing a gate driving scanning operation, and enable the second shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line when the second shift register unit is performing a gate driving scanning operation.

[0010] In a possible embodiment of the present disclosure, when the display panel is in a planar state, the display panel is changed from a folded state to an unfolded state; or when the display panel is in the planar state, the display panel is changed from a curled state to the unfolded state.

[0011] In a possible embodiment of the present disclosure, the gate driving module further includes a detection circuit configured to detect whether the display panel is in the non-planar state or the planar state, generate a corresponding state indication signal, and transmit the state indication signal to the control circuit.

[0012] In a possible embodiment of the present disclosure, the control circuit is further configured to, within a black image display time period immediately before a non-planar time period, apply a predetermined data voltage to a data line connected to a subpixel at the second display sub-region, thereby to enable the subpixel to display a black image. The non-planar time period is a time period within which a first voltage signal is applied by the control circuit to the clock signal line.

[0013] In a possible embodiment of the present disclosure, the clock signal line includes a first clock signal line and a second clock signal line. Odd-numbered-level first shift register units of the first shift register sub-circuitry are connected to the first clock signal input end, and even-numbered-level first shift register units of the first shift register sub-circuitry are connected to the second clock signal input end. The first shift register sub-circuitry includes even-numbered levels of first shift register units, odd-numbered-level second shift register units of the second shift register sub-circuitry are connected to the first clock signal input end, and even-numbered-level second shift register units of the second shift register sub-circuitry are connected to the second clock signal input end.

[0014] In a possible embodiment of the present disclosure, the clock signal line includes a first clock signal line and a second clock signal line. Odd-numbered-level first shift register units of the first shift register sub-circuitry are connected to the first clock signal input end, and even-numbered-level first shift register units of the first shift register sub-circuitry are connected to the second clock signal input end. The first shift register sub-circuitry includes odd-numbered levels of first shift register units, odd-numbered-level second shift register units of the second shift register sub-circuitry are connected to the second clock signal input end, and even-numbered-level second shift register units of the second shift register sub-circuitry are connected to the first clock signal input end.

[0015] In another aspect, the present disclosure provides in some embodiments a gate driving control method for use in the above-mentioned gate driving module, including, when the display panel is in a non-planar state and the second shift register unit is performing a gate driving scanning operation, applying, by the control circuit, a first voltage signal to the clock signal line, so as to enable the second shift register unit to control the gate line to output a signal for turning off the transistor corresponding to the gate line.

[0016] In a possible embodiment of the present disclosure, the first shift register unit is further connected to the clock signal line. The gate driving control method further includes, when the display panel is in the non-planar state and the first shift register unit is performing the gate driving scanning operation, applying, by the control circuit, a clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line.

[0017] In a possible embodiment of the present disclosure, the gate driving control method further includes, when the display panel is in a planar state, applying, by the control circuit, a clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line when the first register unit is performing the gate driving scanning operation, and enable the second shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line when the second shift register unit is performing the gate driving scanning operation.

[0018] In a possible embodiment of the present disclosure, the gate driving module further includes a detection circuit, and the gate driving control method further includes detecting, by the detection circuit, whether the display panel is in the non-planar state or the planar state, generating a corresponding state indication signal, and transmitting the state indication signal to the control circuit.

[0019] In a possible embodiment of the present disclosure, the gate driving control method further includes, within a black image display time period immediately before a non-planar time period, applying, by the control circuit, a predetermined data voltage to a data line connected to a subpixel at a second display sub-region, so as to enable the subpixel to display a black image. The non-planar time period is a time period within which a first voltage signal is applied by the control circuit to the clock signal line.

[0020] In yet another aspect, the present disclosure provides in some embodiments a display device including the above-mentioned gate driving module.

[0021] In a possible embodiment of the present disclosure, the display device further includes a driving integrated circuit and a plurality of gate lines extending in a first direction. Each folding axis extends in the first direction, and a control circuit of the gate driving module is arranged in the driving integrated circuit.

[0022] In a possible embodiment of the present disclosure, a gate driving circuit of the gate driving module is arranged at a peripheral region of a display panel to which an extension direction of the plurality of gate lines points.

[0023] In a possible embodiment of the present disclosure, the plurality of gate lines is arranged in a longitudinal direction, the gate driving circuit of the gate driving module is arranged at an upper side or a lower side of the display panel, and the longitudinal direction is substantially the same as the first direction.

[0024] In a possible embodiment of the present disclosure, the plurality of gate lines is arranged in a longitudinal direction. The gate driving module includes two gate driving circuits. A first gate driving circuit of the two gate driving circuits is arranged at an upper side of the display panel in such a manner that each shift register unit is connected to an upper end of the corresponding gate line, and a second gate driving circuit of the two gate driving circuits is arranged at a lower side of the display panel in such a manner that each shift register unit is connected to a lower end of the corresponding gate line. The longitudinal direction is substantially the same as the first direction.

[0025] In a possible embodiment of the present disclosure, the first gate diving circuit and the second gate driving circuit are each a Gate On Array (GOA) circuit arranged on an array substrate.

BRIEF DESCRIPTION OF THE DRAWINGS



[0026] In order to illustrate the technical solutions of the present disclosure or the related art in a clearer manner, the drawings desired for the present disclosure or the related art will be described hereinafter briefly. Obviously, the following drawings merely relate to some embodiments of the present disclosure, and based on these drawings, a person skilled in the art may obtain the other drawings without any creative effort.

Fig.1 is a schematic view showing a display panel including a gate driving module in an unfolded state (i.e., a planar state) according to one embodiment of the present disclosure;

Fig.2 is a schematic view showing the display panel including the gate driving module in a folded state (i.e., a non-planar state) according to one embodiment of the present disclosure;

Fig.3 is a schematic view showing the gate driving module according to one embodiment of the present disclosure;

Fig.4 is a sequence diagram of the gate driving module when the display panel is in the folded state according to one embodiment of the present disclosure;

Fig.5 is another sequence diagram of the gate driving module when the display panel is in the unfolded state according to one embodiment of the present disclosure; and

Fig.6 is a schematic view showing a display device according to one embodiment of the present disclosure.


DETAILED DESCRIPTION OF THE EMBODIMENTS



[0027] In order to make the objects, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.

[0028] All transistors adopted in the embodiments of the present disclosure may be thin film transistors (TFTs), field effect transistors (FETs) or any other elements having an identical characteristic. In order to differentiate two electrodes other than a gate electrode from each other, one of the two electrodes is called as first electrode and the other is called as second electrode. In actual use, the first electrode may be a drain electrode while the second electrode may be a source electrode, or the first electrode may be a source electrode while the second electrode may be a drain electrode.

[0029] The present disclosure provides in some embodiments a gate driving module for use in a display panel provided with a display region. When the display panel is in a folded state, the display region is divided by one or more folding axes into a plurality of display sub-regions. The gate driving module includes a gate driving circuit. The gate driving circuit includes a plurality of shift register sub-circuitries connected to each other in a cascaded manner. A first shift register sub-circuitry of the plurality of shift register sub-circuitries includes at least one level of first shift register unit, and a second shift register sub-circuitry of the plurality of shift register sub-circuitries includes at least one level of second shift register unit. The gate driving module further includes a control circuit. Each first shift register unit of the at least one level of first shift register unit is connected to a gate line at a first display sub-region of the plurality of display sub-regions. Each second shift register unit of the at least one level of second shift register unit is connected to a clock signal line and a gate line arranged at a second display sub-region of the plurality of display sub-regions, and configured to generate a gate driving signal in accordance with a voltage signal on the clock signal line and output the gate driving signal to the gate line. The control circuit is configured to, when the display panel is in the folded state and one second shift register unit of the at least one level of second shift register unit is performing a gate driving scanning operation, apply a first voltage signal to the clock signal line, so as to enable the second shift register unit to control a gate line to output a signal for turning off a transistor corresponding to the gate line.

[0030] According to the gate driving module in the embodiments of the present disclosure, instead of dividing the gate driving circuit physically (for the gate driving module in the embodiments of the present disclosure, the first shift register sub-circuitry and the second shift register sub-circuitry are connected to each other in a cascaded manner), when the display panel is in the folded state and the second shift register unit (e.g., the second shift register unit corresponds to the second display sub-region where no image is displayed when the display panel is in the folded state) is performing the gate driving scanning operation, the control circuitry may apply the first voltage signal to the clock signal line, so as to enable the second shift register unit to control a gate line to output the signal for turning off the transistor corresponding to the gate line, thereby to prevent any image from being displayed at the second display sub-region. As a result, it is able to display the image in a split-screen manner through time sequence adjustment when the display panel is in the folded state, and reduce the power consumption for a gate driving operation.

[0031] During the implementation, the display panel may be, but not limited to, a flexible display panel which is capable of being folded or curled so as to be in a non-planar state.

[0032] In actual use, when a transistor of a subpixel connected to a gate line in an active area (AA) of the display panel is a p-type transistor, the first voltage signal may be a high voltage signal, so as to turn off the transistor. When the transistor of the subpixel connected to the gate line in the active area of the display panel is an n-type transistor, the first voltage signal may be a low voltage signal, so as to turn off the transistor. In other words, in the embodiments of the present disclosure, a type of the transistor of the subpixel connected to the gate line in the active area of the display panel will not be particularly defined.

[0033] As shown in Fig.1, when the display panel 10 is in the unfolded state (i.e., a planar state), the display panel 10 may include a display region 11. In Fig.1, a dotted line represents the folding axis.

[0034] As shown in Fig.2, in a possible embodiment of the present disclosure, when the display panel 10 is in the folded state, the display region is divided by the folding axis into a first display sub-region 20 (when the display panel 10 is in the folded state, the first display sub-region 20 is a front display region where an image is to be displayed normally) and a second display sub-region (when the display panel 10 is in the folded state, i.e., the non-planar state, the second display sub-region is folded in such a manner as to be shielded by the first display sub-region and thus not shown in Fig.2). In Fig.2, a dotted line represents the folding axis.

[0035] In actual use, there may exist more than one folding axis, i.e., at least two folding axes. When the display panel 10 is in the folded state, the display region 11 may be divided by the at least two folding axes into at least three display sub-regions. For example, when the gate driving module includes two folding axes and the display panel is in the folded state, the display region may include, but not limited to, two first display sub-regions where an image is to be displayed normally, and one second display sub-region where no image is to be displayed.

[0036] In a possible embodiment of the present disclosure, there may exist one folding axis, one first shift register sub-circuitry and one second shift register sub-circuitry. A gate driving signal output end of a last-level first shift register unit of the first shift register sub-circuitry may be connected to an input end of a first-level second shift register unit of the second shift register sub-circuitry, and a gate driving signal output end of the first-level second shift register unit of the second shift register sub-circuitry may be connected to a resetting end of the last-level first shift register unit of the first shift register sub-circuitry.

[0037] When the display panel is in the folded state and merely divided into two display sub-regions, the last-level first shift register unit of the first shift register sub-circuitry may be connected to the first-level second shift register unit of the second shift-register sub-circuitry, so that the first shift register sub-circuitry and the second shift register sub-circuitry may be connected to each other in a cascaded manner.

[0038] In another possible embodiment of the present disclosure, there may exist two folding axes, two first register sub-circuitries, two first display sub-regions corresponding to the first register unit sub-circuitries respectively, one second shift register sub-circuitry and one second display sub-region.

[0039] To be specific, a gate driving signal output end of a last-level first shift register unit of a first one of the first shift register sub-circuitries may be connected to an input end of a first-level second shift register unit of the second shift register sub-circuitry.

[0040] A gate driving signal output end of the first-level second shift register unit of the second shift register sub-circuitry may be connected to a resetting end of the last-level first shift register unit of the first one of the first shift register sub-circuitries.

[0041] A gate driving signal output end of the last-level second shift register unit of the second shift register sub-circuitry may be connected to an input end of a first-level first shift register unit of a second one of the first shift register sub-circuitries.

[0042] A gate driving signal output end of the first-level first shift register unit of the second one of the first shift register sub-circuitries may be connected to a resetting end of the last-level second shift register unit of the second shift register sub-circuitry.

[0043] In another possible embodiment of the present disclosure, when the display panel is in the folded state, the display panel may be divided into three display sub-regions, i.e., two display sub-regions where an image is to be displayed normally and one display sub-region where no image is to be displayed. In other words, the gate driving module may include two first shift register sub-circuitries and one second shift register sub-circuitry. The first one of the two first shift register sub-circuitries may be connected to the second shift register sub-circuitry in a cascaded manner, and the second shift register sub-circuitry may be connected to the second one of the two first shift register sub-circuitries in a cascaded manner.

[0044] To be specific, the first shift register unit may be further connected to the clock signal line, and further configured to generate a gate driving signal in accordance with the voltage signal on the clock signal line and output the gate driving signal to the gate line connected to the first shift register unit.

[0045] The control circuit is further configured to, when the display panel is in the folded state and the first shift register unit is performing the gate driving scanning operation, apply the clock signal to the clock signal line, so as to enable the first shift register unit to control a gate line to output a signal for turning on the transistor corresponding to the gate line.

[0046] When the display panel is in the folded state (i.e., the non-planar state) and the first shift register unit at the first display sub-region where an image is to be displayed normally is performing the gate driving scanning operation, the control circuit may apply the clock signal to the clock signal line normally, so as to enable the first shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line, thereby to enable the image to be displayed normally at the first display sub-region.

[0047] To be specific, the control circuit is further configured to, when the display panel is in the unfolded state (i.e., the planar state), apply the clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line when the first shift register unit is performing the gate driving scanning operation, and enable the second shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line when the second shift register unit is performing the gate driving scanning operation.

[0048] Correspondingly, when the display panel is in the unfolded state, as shown in Fig.3, the control circuit 30 may apply the clock signal to the clock signal line normally, so as to display the image normally at the display region of the display panel.

[0049] To be specific, the control circuit 30 may be implemented as an IC chip, which includes a memory storing therein a relevant computer program and a processor for calling the computer program and executing relevant processing. The computer program may be executed by the processor, so as to enable the control circuit 30 to apply the clock signal to the clock signal line normally, thereby to display the image normally at the display region of the display panel.

[0050] During the implementation, as shown in Fig.3, the gate driving module may further include a detection circuit 40 configured to detect whether the display panel is in the folded state or the unfolded state, generate a corresponding state indication signal, and transmit the state indication signal to the control circuit 30.

[0051] Correspondingly, the gate driving module may further include the detection circuit 40, so as to detect a state of the display panel.

[0052] To be specific, the detection circuit 40 may be a device capable of capturing a real-time image or a real-time state of the display panel, e.g., an electronic camera, a video camera, or an image sensor.

[0053] During the implementation, the control circuit 30 is further configured to, within a black image display time period immediately before a folding time period, apply a predetermined data voltage to a data line connected to a subpixel at the second display sub-region, thereby to enable the subpixel to display a black image. The folding time period may be a time period within which a first voltage signal is applied by the control circuit to the clock signal line.

[0054] A duration of the black image display time period may be set in accordance with the practical need. For example, the black image display time period may be one frame, and the control circuit may, within one frame before a time period within which the first voltage signal is applied to the clock signal line, control the subpixels at the second display sub-region to display a black image, so as to be ready for the folded state.

[0055] In a possible embodiment of the present disclosure, the clock signal line may include a first clock signal line and a second clock signal line.

[0056] Odd-numbered-level first shift register units of the first shift register sub-circuitry may be connected to the first clock signal input end, and even-numbered-level first shift register units of the first shift register sub-circuitry may be connected to the second clock signal input end.

[0057] The first shift register sub-circuitry may include even-numbered levels of first shift register units. Odd-numbered-level second shift register units of the second shift register sub-circuitry may be connected to the first clock signal input end, and even-numbered-level second shift register units of the second shift register sub-circuitry may be connected to the second clock signal input end.

[0058] During the implementation, when the clock signal line includes the first clock signal line and the second clock signal line, for the gate driving module in the embodiments of the present disclosure, the odd-numbered-level shift register units of the gate driving circuit may be connected to the first clock signal line, and the even-numbered-level shift register units of the gate driving circuit may be connected to the second clock signal line. When the first shift register sub-circuitry includes even-numbered levels of first shift register units, the odd-numbered-level second shift register units of the second shift register sub-circuitry may be the odd-numbered-level shift register units of the gate driving circuit, and the even-numbered-level second shift register units of the second shift register sub-circuitry may be the even-numbered-level shift register units of the gate driving circuit.

[0059] In another possible embodiment of the present disclosure, the clock signal line may include a first clock signal line and a second clock signal line.

[0060] Odd-numbered-level first shift register units of the first shift register sub-circuitry may be connected to the first clock signal input end, and even-numbered-level first shift register units of the first shift register sub-circuitry may be connected to the second clock signal input end.

[0061] The first shift register sub-circuitry may include odd-numbered levels of first shift register units. Odd-numbered-level second shift register units of the second shift register sub-circuitry may be connected to the second clock signal input end, and even-numbered-level second shift register units of the second shift register sub-circuitry may be connected to the first clock signal input end.

[0062] During the implementation, when the clock signal line includes the first clock signal line and the second clock signal line, for the gate driving module in the embodiments of the present disclosure, the odd-numbered-level shift register units of the gate driving circuit may be connected to the first clock signal line, and the even-numbered-level shift register units of the gate driving circuit may be connected to the second clock signal line.

[0063] During the implementation, when the clock signal line includes the first clock signal line and the second clock signal line, for the gate driving module in the embodiments of the present disclosure, the odd-numbered-level shift register units of the gate driving circuit may be connected to the first clock signal line, and the even-numbered-level shift register units of the gate driving circuit may be connected to the second clock signal line. When the first shift register sub-circuitry includes odd-numbered levels of first shift register units, the even-numbered-level second shift register units of the second shift register sub-circuitry may be the odd-numbered-level shift register units of the gate driving circuit, and the odd-numbered-level second shift register units of the second shift register sub-circuitry may be the even-numbered-level shift register units of the gate driving circuit.

[0064] In actual use, the number of the clock signal lines may not be limited to two, and there may exist 2A clock signal lines, where A is a positive integer. For example, when A is 2, there may exist four clock signal lines. At this time, a (4a-3)th-level shift register unit of the gate driving circuit may be connected to a first clock signal line, a (4a-2)th-level shift register unit of the gate driving circuit may be connected to a second clock signal line, a (4a-1)th-level shift register unit of the gate driving circuit may be connected to a third clock signal line, and a (4a)th-level shift register unit of the gate driving circuit may be connected to a fourth clock signal line, where a is a positive integer, and 4a is smaller than or equal to the number of levels of the shift register units of the gate driving circuit.

[0065] The gate driving module will be described hereinafter in more details in conjunction with a specific embodiment.

[0066] In this embodiment of the present disclosure, the gate driving module may be applied to a display panel provided with a display region. When the display panel is in the folded state, the display region may be divided by the folding axis into a first display sub-region and a second display sub-region. The display driving module may include a gate driving circuit.

[0067] As shown in Fig.3, the gate driving circuit may include a first shift register sub-circuitry S1 and a second shift register sub-circuitry S2 connected to each other in a cascaded manner.

[0068] The first shift register sub-circuitry S1 may include N levels of shift register units. In Fig.3, S11 represents a first-level first shift register unit, S12 represents a second-level first shift register unit, S13 represents a third-level first shift register unit, and SIN represents an Nth-level first shift register unit, where N is an odd number greater than 3.

[0069] Similarly, the second shift register sub-circuitry S2 may include a first-level second shift register unit S21, a second-level second shift register unit S22, a third-level second shift register unit S23, a fourth-level second shift register unit S24 and a fifth-level second shift register unit S25.

[0070] As shown in Fig.3, the gate driving module may further include a control circuit 30.

[0071] S11 may be connected to a first gate line (not shown in Fig.3) at the first display sub-region, S12 may be connected to a second gate line (not shown in Fig.3) at the first display sub-region, S13 may be connected to a third gate line (not shown in Fig.3) at the first display sub-region, and SIN may be connected to an Nth gate line (not shown in Fig.3) at the first display sub-region.

[0072] S21 may be connected to a first gate line (not shown in Fig.3) at the second display sub-region, S22 may be connected to a second gate line (not shown in Fig.3) at the second display sub-region, S23 may be connected to a third gate line (not shown in Fig.3) at the second display sub-region, S24 may be connected to a fourth gate line (not shown in Fig.3) at the second display sub-region, and S25 may be connected to a fifth gate line (not shown in Fig.3) at the second display sub-region.

[0073] S11 may be connected to a first clock signal line CKB, S12 may be connected to a second clock signal line CK, S13 may be connected to the first clock signal lien CKB, SIN may be connected to the first clock signal line CKB, S21 may be connected to the second clock signal line CK, S22 may be connected to the first clock signal line CKB, S23 may be connected to the second clock signal line CK, S24 may be connected to the first clock signal line CKB, and S25 may be connected to the second clock signal line CK.

[0074] A start signal STV may be applied to an input end INPUT 11 of S11, a resetting end RESET 11 of S11 may be connected to a gate driving signal output end OUT12 of S12, an input end INPUT 12 of S12 may be connected to a gate driving signal output end OUT 11 of S11, a resetting end RESET 12 of S12 may be connected to a gate driving signal output end OUT13 of S13 ,an input end of S13 may be connected to the gate driving signal output end OUT12 of S12, a resetting end RESET 13 of S13 may be connected to a gate driving signal output end of the fourth-level first shift register unit (not shown in Fig.3), an input end of SIN INPUT1N may be connected to a gate driving signal output end of an (N-1)th-level first shift register unit (not shown in Fig.3), a resetting end RESET IN of SIN may be connected to a gate driving signal output end OUT21 of S21, an input end INPTU21 of S21 may be connected to a gate driving signal output end OUT IN of SIN, a resetting end RESET21 of S21 may be connected to a gate driving signal output end OUT22 of S22, an input end INPTU22 of S22 may be connected to the gate driving signal output end OUT21 of S21, a resetting end RESET22 of S22 may be connected to a gate driving signal output end OUT23 of S23, an input end INPTU23 of S23 may be connected to the gate driving signal output end OUT22 of S22, a resetting end RESET23 of S23 may be connected to a gate driving signal output end OUT24 of S24, an input end INPUT24 of S24 may be connected to a gate driving signal output end OUTPUT 23 of S23, a resetting end RESET24 of S24 may be connected to a gate driving signal output end OUT25 of S25, and an input end INPUT25 of S25 may be connected to the gate driving signal output end OUT24 of S24.

[0075] In addition, an external resetting signal (not shown in Fig.3) may be applied to a resetting end RESET25 of S25.

[0076] The control circuit 30 maybe connected to the first clock signal line CKB and the second clock signal line CK.

[0077] As shown in Fig.4, when the display panel is in the folded state, within a display time period t11 of one frame Tz, when S11, S12, S13 and SIN are performing the gate driving scanning operation, the control circuit 30 may apply a first clock signal to CKB and apply a second clock signal to CK, so as to enable S11 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT11, enable S12 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT12 , enable S13 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT13, and enable SIN to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT IN, thereby to display an image normally at the first display sub-region when the display panel is folded. Within a non-display time period t12 of each frame, when S21, S22, S23, S24 and S25 are performing the gate driving scanning operation, the control circuit 30 may apply high voltage signals to CKB and CK respectively (at this time, a transistor of each subpixel connected to the corresponding gate line is a p-type transistor), so as to enable S21, S22, S23, S24 and S25 to control gate lines to output signals for turning off the transistors corresponding to the gate lines respectively, thereby to prevent any image from being displayed at the second display sub-region.

[0078] During the implementation, the control circuit may be connected to CK and CKB.

[0079] As shown in Fig.5, when the display panel is in the unfolded state, within a first display time period t21 of one frame display time Tz, when S11, S12, S13 and SIN are performing the gate driving scanning operation, the control circuit 30 may apply the first clock signal to CKB and apply the second clock signal to CK, so as to enable S11 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT11, enable S12 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT12, enable S13 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT13, and enable SIN to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT1N, thereby to display an image normally at the first display sub-region when the display panel is unfolded. Within a second display time period t22 of each frame display time Tz, when S21, S22, S23, S24 and S25 are performing the gate driving scanning operation, the control circuit 30 may apply the first clock signal to CKB and apply the second clock signal to CK, so as to enable S21 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT21, enable S22 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT22, enable S23 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT23, enable S24 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT24, and enable S25 to output a signal for turning on a transistor connected to a corresponding gate line through the gate driving signal from OUT25, thereby to display an image normally at the second display sub-region when the display panel is unfolded.

[0080] During the implementation, within one frame before a time period within which the high voltage signals are applied to CK and CKB, the control circuit 30 may apply a black-state voltage to the second display sub-region, so as to be ready for the folded state where no image is to be displayed at the second display sub-region.

[0081] During the operation of the gate driving module, when the display panel is in the folded state and an image is to be displayed in a half-screen manner, it is merely necessary for the control circuit 30 to apply the high voltage signals to CKB and CK within the non-display time period t12 of one frame display time Tz. No pulse signal is outputted by CK and CKB any longer, so it is able to reduce the power consumption for the gate driving operation. In the embodiments of the present disclosure, the half-screen display is achieved through the time sequence adjustment, so it is able flexibly adjust a position where the image is to be displayed in a half-screen manner. For example, it is merely necessary to adjust a time sequence of the signals on CK and a time sequence of the signals on CKB, so as to adjust a position of the folding axis from an Nth gate line to an Mth gate (M is a positive integer) line at the display region. As a result, it is able to improve the compatibility of the display panel.

[0082] The present disclosure further provides in some embodiments a gate driving control method for use in the above-mentioned gate driving module. The gate driving control method includes, when the display panel is in the folded state and the second shift register unit is performing the gate driving scanning operation, applying, by the control circuit, a first voltage signal to the clock signal line, so as to enable the second shift register unit to control the gate line to output a signal for turning off the transistor corresponding to the gate line.

[0083] According to the gate driving control method in the embodiments of the present disclosure, instead of dividing the gate driving circuit physically, when the display panel is in the folded state and the second shift register unit is performing the gate driving scanning operation, the control circuitry may apply the first voltage signal to the clock signal line, so as to enable the second shift register unit to control the gate line to output the signal for turning off the transistor corresponding to the gate line, thereby to prevent any image from being displayed at the second display sub-region. As a result, it is able to display the image in a split-screen manner through time sequence adjustment when the display panel is in the folded state, and reduce the power consumption for a gate driving operation.

[0084] In actual use, the first shift register unit may be further connected to the clock signal line. The gate driving control method may further include, when the display panel is in the folded state and the first shift register unit is performing the gate driving scanning operation, applying, by the control circuit, a clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line.

[0085] When the display panel is in the folded state and the first shift register unit at the first display sub-region where an image is to be displayed normally is performing the gate driving scanning operation, the control circuit may apply the clock signal to the clock signal line normally, so as to enable the first shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line, thereby to display the image normally at the first display sub-region.

[0086] To be specific, gate driving control method may further include, when the display panel is in the unfolded state, applying, by the control circuit, a clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line when the first register unit is performing the gate driving scanning operation, and enable the second shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line when the second shift register unit is performing the gate driving scanning operation.

[0087] When the display panel is in the unfolded state, the control circuit may apply the clock signal to the clock signal line normally, so as to display an image at the display region of the display panel normally.

[0088] To be specific, the gate driving module may further include a detection circuit, and the gate driving control method may further include detecting, by the detection circuit, whether the display panel is in the folded state or the un-folded state, generating a corresponding state indication signal, and transmitting the state indication signal to the control circuit.

[0089] To be specific, the detection circuit may be any device capable of capturing a real-time image or a real-time state of the display panel, e.g., an electronic camera, a video camera or an image sensor.

[0090] During the implementation, the gate driving control method may further include, within a black image display time period immediately before a non-planar time period, applying a predetermined data voltage to a data line connected to a subpixel at a second display sub-region, so as to enable the subpixel to display a black image. The non-planar time period may be a time period within which a first voltage signal is applied by the control circuit to the clock signal line.

[0091] A duration of the black image display time period may be set in accordance with the practical need. For example, the black image display time period may be one frame display time, and the control circuit may, within one frame display time before a time period within which the first voltage signal is applied to the clock signal line, control the subpixels at the second display sub-region to display a black image, so as to be ready for the folded state.

[0092] The present disclosure further provides in some embodiments a display device including the above-mentioned gate driving module.

[0093] To be specific, the display device may further include a driving integrated circuit and a plurality of gate lines extending in a first direction. Each folding axis may extend in the first direction, and a control circuit of the gate driving module may be arranged in the driving integrated circuit.

[0094] During the implementation, the control circuit may be arranged in the driving integrated circuit (IC), and the folding axis and the plurality of gate lines may all extend in the first direction.

[0095] During the implementation, a gate driving circuit of the gate driving module may be arranged at a peripheral region of a display panel to which an extension direction of the plurality of gate lines points.

[0096] In a possible embodiment of the present disclosure, the plurality of gate lines may be arranged in a longitudinal direction, the gate driving circuit of the gate driving module may be arranged at an upper side or a lower side of the display panel, and the longitudinal direction may be substantially the same as the first direction.

[0097] When the display panel is of a small size, the gate driving module may merely include one gate driving circuit. When the plurality of gate lines and the folding axis are arranged in the longitudinal direction, the gate driving circuit may be arranged at the upper side or the lower side of the display panel, and the longitudinal direction may be substantially the same as the first direction.

[0098] In another possible embodiment of the present disclosure, the plurality of gate lines may be arranged in a longitudinal direction. The gate driving module may include two gate driving circuits that are a first gate driving circuit and a second gate driving circuit. The first gate driving circuit may be arranged at an upper side of the display panel in such a manner that each shift register unit is connected to an upper end of the corresponding gate line, and a second gate driving circuit may be arranged at a lower side of the display panel in such a manner that each shift register unit is connected to a lower end of the corresponding gate line.

[0099] When the display panel is of a relatively large size, the gate driving module may include two gate driving circuits, i.e., the first gate driving circuit arranged at the upper side of the display panel, and the second gate driving circuit arranged at the lower side of the display panel. The gate driving scanning operation may be performed on the gate lines simultaneously through the first gate driving circuit and the second gate driving circuit.

[0100] As shown in Fig.6, when the display panel 10 is in the unfolded stated, the display panel 10 may include a display region 11. In Fig.6, a dotted line represents the folding axis. A display sub-region on the left of the folding axis is the first display sub-region, and a display sub-region on the right of the folding axis is the second display sub-region.

[0101] In Fig.6, reference number 61 represents the first gate driving circuit, reference number 62 represents the second gate driving circuit, and DIC represents the driving IC. The control circuit may be arranged in the driving IC.

[0102] The first gate driving circuit 61 may include a plurality of shift register units (not shown) connected to each other in a cascaded manner, and the second gate driving circuit 62 may include a plurality of shift register units (not shown) connected to each other in a cascaded manner.

[0103] In actual use, the first gate driving circuit and the second gate driving circuit may each be a GOA circuit.

[0104] The display device may be any product or member having a display function, e.g., electronic paper, organic light-emitting diode (OLED) display device, liquid crystal display (LCD) device, mobile phone, flat-panel computer, television, display, laptop computer, digital photo frame or navigator.

[0105] The above embodiments are for illustrative purposes only, but the present disclosure is not limited thereto. Obviously, a person skilled in the art may make further modifications and improvements without departing from the spirit of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.


Claims

1. A gate driving module for use in a display device, wherein the display device is provided with a display region, when the display panel is in a non-planar state, the display region comprises a plurality of display sub-regions,
wherein the gate driving module comprises a gate driving circuit;
the gate driving circuit comprises a plurality of shift register sub-circuitries connected to each other in a cascaded manner;
a first shift register sub-circuitry of the plurality of shift register sub-circuitries comprises at least one level of first shift register unit, and a second shift register sub-circuitry of the plurality of shift register sub-circuitries comprises at least one level of second shift register unit;
the gate driving module further comprises a control circuit;
each first shift register unit of the at least one level of first shift register unit is connected to a gate line at a first display sub-region of the plurality of display sub-regions;
each second shift register unit of the at least one level of second shift register unit is connected to a clock signal line and a gate line arranged at a second display sub-region of the plurality of display sub-regions, and configured to generate a gate driving signal in accordance with a voltage signal on the clock signal line and output the gate driving signal to the gate line; and
the control circuit is configured to, when the display panel is in the non-planar state and one second shift register unit of the at least one level of second shift register unit is performing a gate driving scanning operation, apply a first voltage signal to the clock signal line, so as to enable the second shift register unit to control the gate line to output a signal for turning off a transistor corresponding to the gate line.
 
2. The gate driving module according to claim 1, wherein when the display panel is in the non-planar state, the display panel is folded, and the display region is divided by one or more folding axes into a plurality of display sub-regions; or when the display panel is the non-planar state, the display panel is curled.
 
3. The gate driving module according to claim 2, wherein there are one folding axis, one first shift register sub-circuitry and one second shift register sub-circuitry;
a gate driving signal output end of a last-level first shift register unit of the first shift register sub-circuitry is connected to an input end of a first-level second shift register unit of the second shift register sub-circuitry; and
a gate driving signal output end of the first-level second shift register unit of the second shift register sub-circuitry is connected to a resetting end of the last-level first shift register unit of the first shift register sub-circuitry.
 
4. The gate driving module according to claim 2, wherein there are two folding axes, two first register sub-circuitries, two first display sub-regions corresponding to the first register unit sub-circuitries respectively, one second shift register sub-circuitry and one second display sub-region;
a gate driving signal output end of a last-level first shift register unit of a first one of the first shift register sub-circuitries is connected to an input end of a first-level second shift register unit of the second shift register sub-circuitry;
a gate driving signal output end of the first-level second shift register unit of the second shift register sub-circuitry is connected to a resetting end of the last-level first shift register unit of the first one of the first shift register sub-circuitries;
a gate driving signal output end of the last-level second shift register unit of the second shift register sub-circuitry is connected to an input end of a first-level first shift register unit of a second one of the first shift register sub-circuitries; and
a gate driving signal output end of the first-level first shift register unit of the second one of the first shift register sub-circuitries is connected to a resetting end of the last-level second shift register unit of the second shift register sub-circuitry.
 
5. The gate driving module according to any one of claims 1 to 4, wherein the first shift register unit is further connected to the clock signal line, and configured to generate a gate driving signal in accordance with the voltage signal on the clock signal line and output the gate driving signal to the gate line connected to the first shift register unit; and
the control circuit is further configured to, when the display panel is in the non-planar state and the first shift register unit is performing a gate driving scanning operation, apply the clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line.
 
6. The gate driving module according to any one of claims 1 to 5, wherein the control circuit is further configured to, when the display panel is in the planar state, apply the clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line when the first shift register unit is performing a gate driving scanning operation, and enable the second shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line when the second shift register unit is performing a gate driving scanning operation.
 
7. The gate driving module according to claim 6, wherein when the display panel is in a planar state, the display panel is changed from a folded state to an unfolded state; or when the display panel is in the planar state, the display panel is changed from a curled state to the unfolded state.
 
8. The gate driving module according to any one of claims 1 to 7, further comprising a detection circuit configured to detect whether the display panel is in the non-planar state or the planar state, generate a corresponding state indication signal, and transmit the state indication signal to the control circuit.
 
9. The gate driving module according to any one of claims 1 to 8, wherein the control circuit is further configured to, within a black image display time period immediately before a non-planar time period, apply a predetermined data voltage to a data line connected to a subpixel at the second display sub-region, thereby to enable the subpixel to display a black image; and
the non-planar time period is a time period within which a first voltage signal is applied by the control circuit to the clock signal line.
 
10. The gate driving module according to any one of claims 1 to 9, wherein the clock signal line comprises a first clock signal line and a second clock signal line;
odd-numbered-level first shift register units of the first shift register sub-circuitry are connected to the first clock signal input end, and even-numbered-level first shift register units of the first shift register sub-circuitry are connected to the second clock signal input end; and
the first shift register sub-circuitry comprises even-numbered levels of first shift register units, odd-numbered-level second shift register units of the second shift register sub-circuitry are connected to the first clock signal input end, and even-numbered-level second shift register units of the second shift register sub-circuitry are connected to the second clock signal input end.
 
11. The gate driving module according to any one of claims 1 to 9, wherein the clock signal line comprises a first clock signal line and a second clock signal line;
odd-numbered-level first shift register units of the first shift register sub-circuitry are connected to the first clock signal input end, and even-numbered-level first shift register units of the first shift register sub-circuitry are connected to the second clock signal input end; and
the first shift register sub-circuitry comprises odd-numbered levels of first shift register units, odd-numbered-level second shift register units of the second shift register sub-circuitry are connected to the second clock signal input end, and even-numbered-level second shift register units of the second shift register sub-circuitry are connected to the first clock signal input end.
 
12. A gate driving control method for use in the gate driving module according to any one of claims 1 to 11, comprising, when the display panel is in a non-planar state and the second shift register unit is performing a gate driving scanning operation, applying, by the control circuit, a first voltage signal to the clock signal line, so as to enable the second shift register unit to control the gate line to output a signal for turning off the transistor corresponding to the gate line.
 
13. The gate driving control method according to claim 12, wherein the first shift register unit is further connected to the clock signal line, wherein the gate driving control method further comprises, when the display panel is in the non-planar state and the first shift register unit is performing the gate driving scanning operation, applying, by the control circuit, a clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output a signal for turning on the transistor corresponding to the gate line.
 
14. The gate driving control method according to claim 12 or 13, further comprising, when the display panel is in a planar state, applying, by the control circuit, a clock signal to the clock signal line, so as to enable the first shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line when the first register unit is performing the gate driving scanning operation, and enable the second shift register unit to control the gate line to output the signal for turning on the transistor corresponding to the gate line when the second shift register unit is performing the gate driving scanning operation.
 
15. The gate driving control method according to any one of claims 12 to 14, wherein the gate driving module further comprises a detection circuit, wherein the gate driving control method further comprises detecting, by the detection circuit, whether the display panel is in the non-planar state or the planar state, generating a corresponding state indication signal, and transmitting the state indication signal to the control circuit.
 
16. The gate driving control method according to any one of claims 12 to 15, further comprising, within a black image display time period immediately before a non-planar time period, applying, by the control circuit, a predetermined data voltage to a data line connected to a subpixel at a second display sub-region, so as to enable the subpixel to display a black image, wherein the non-planar time period is a time period within which a first voltage signal is applied by the control circuit to the clock signal line.
 
17. A display device, comprising the gate driving module according to any one of claims 1 to 11.
 
18. The display device according to claim 17, further comprising a driving integrated circuit and a plurality of gate lines extending in a first direction, wherein each folding axis extends in the first direction, and a control circuit of the gate driving module is arranged in the driving integrated circuit.
 
19. The display device according to claim 18, wherein a gate driving circuit of the gate driving module is arranged at a peripheral region of a display panel to which an extension direction of the plurality of gate lines points.
 
20. The display device according to claim 19, wherein the plurality of gate lines is arranged in a longitudinal direction, the gate driving circuit of the gate driving module is arranged at an upper side or a lower side of the display panel, and the longitudinal direction is substantially the same as the first direction.
 
21. The display device according to claim 19, wherein the plurality of gate lines is arranged in a longitudinal direction;
the gate driving module comprises two gate driving circuits;
a first gate driving circuit of the two gate driving circuits is arranged at an upper side of the display panel in such a manner that each shift register unit is connected to an upper end of the corresponding gate line, and a second gate driving circuit of the two gate driving circuits is arranged at a lower side of the display panel in such a manner that each shift register unit is connected to a lower end of the corresponding gate line; and
the longitudinal direction is substantially the same as the first direction.
 
22. The display device according to claim 21, wherein the first gate diving circuit and the second gate driving circuit are each a Gate On Array (GOA) circuit arranged on an array substrate.
 




Drawing

























REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description