(19)
(11)EP 3 780 067 A1

(12)EUROPEAN PATENT APPLICATION
published in accordance with Art. 153(4) EPC

(43)Date of publication:
17.02.2021 Bulletin 2021/07

(21)Application number: 19777812.9

(22)Date of filing:  27.03.2019
(51)Int. Cl.: 
H01L 21/28  (2006.01)
H01L 21/336  (2006.01)
(86)International application number:
PCT/CN2019/079932
(87)International publication number:
WO 2019/184957 (03.10.2019 Gazette  2019/40)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 27.03.2018 CN 201810259783

(71)Applicant: CSMC Technologies Fab2 Co., Ltd.
Jiangsu 214028 (CN)

(72)Inventors:
  • FANG, Dong
    Jiangsu 214028 (CN)
  • BIAN, Zheng
    Jiangsu 214028 (CN)

(74)Representative: Noble, Nicholas et al
Kilburn & Strode LLP Lacon London 84 Theobalds Road
London WC1X 8NL
London WC1X 8NL (GB)

  


(54)TRENCHED SPLIT-GATE DEVICE AND METHOD FOR MANUFACTURING SAME


(57) A method for manufacturing a trenched split-gate device, comprising: etching a semiconductor substrate to form a trench (120); depositing an oxide inside the trench to form a floating-gate oxide layer such that the floating-gate oxide layer gradually thickens from top to bottom along a sidewall of the trench, wherein a portion of the floating-gate oxide layer at a lower part of the sidewall of the trench has the same thickness as a portion of the floating-gate oxide layer at a bottom part of the trench; depositing polysilicon inside the trench to form a floating-gate polysilicon layer (123); growing an insulation medium on an upper surface of the floating-gate polysilicon layer to form an isolation layer (124); and forming a control gate on the isolation layer inside the trench.




Description

CROSS REFERENCE TO RELATED APPLICATIONS



[0001] This application claims priority to Chinese patent application No. 2018102597833, filed before the China National Intellectual Property Administration on March 27, 2018 , entitled "Trench split-gate device and method for manufacturing the same", the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD



[0002] The application relates to the technical field of semiconductor manufacturing, in particular to a trench split-gate device and a method for manufacturing the same.

BACKGROUND



[0003] Since the split-gate device structure was put forward, due to the advantages of the split-gate structure with low resistance and low gate capacitance etc., there is a trend that the products of medium and low voltage ordinary trench type VDMOS (vertical double diffused metal oxide semiconductor field-effect transistor) are gradually replaced by the trench split-gate VDMOS devices.

[0004] At present, after a thin oxide layer is grown using thermal oxidation method or thermal oxidation, the lower part of the oxide layer in the trench can be realized by growing an oxide layer on the surface of the thin oxide layer using furnace tube oxidation method or deposition method. With the oxide layer grown by the above methods, the thickness of the oxide layer at the bottom of the trench is usually thinner than that of the oxide layer on the side wall of the trench. With the increase of the thickness of the oxide layer at the bottom of the trench and the increase of the depth of the trench, the ratio of the thickness of the oxide layer at the bottom and the thickness of the oxide layer on the side wall of the trench trends to decrease. When a reverse voltage is applied across the source end and drain end of VDMOS, a thicker oxide layer at the bottom of the trench is required to adapt to withstand voltage. Because the thickness of the oxide layer at the bottom of the trench is less than that of the oxide layer on the side wall oxide layer of the trench, the oxidation process is increased in order to achieve a thicker oxide layer at the bottom of the trench, which causes the thickness of the oxide layer on the side wall of the trench is thicker and a wider trench is required to adapt to the thicker oxide layer on the side wall of the trench. Accordingly, the area of chip is larger and the specific on resistance is higher.

SUMMARY



[0005] According to various embodiments of the present disclosure, a trench split-gate device and a method for manufacturing the same are provided.

[0006] According to one aspect of the present disclosure, a method for manufacturing a trench split-gate device is provided, which comprises: etching a semiconductor substrate to form a trench; depositing oxide in the trench to form a floating gate oxide layer, in which the floating gate oxide layer is gradually thickened from top to bottom along a side wall of the trench, and a thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at a bottom of the trench; depositing polysilicon into the trench to form a floating gate polycrystalline layer; growing an insulating medium on an upper surface of the floating gate polycrystalline layer to form an isolation layer; and forming a control gate on the isolation layer in the trench.

[0007] According to another aspect of the present disclosure, a trench split-gate device is provided, which includes: a semiconductor substrate in which a trench is provided; a floating gate oxide layer provided on an inner wall of the trench, a thickness of the floating gate oxide layer being gradually increased along the side wall of the trench to a bottom of the trench, and the thickness of the floating gate oxide layer at a lower part of the side wall of the trench being the same as that of the floating gate oxide layer at the bottom of the trench; a floating gate polycrystalline layer provided on a surface of the floating gate oxide layer; an isolation layer provided on the floating gate polycrystalline layer, and a control gate provided on the isolation layer to control the on and off of the device.

[0008] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS



[0009] In order to better describe and explain the embodiments or examples of those applications disclosed herein, reference can be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered to limit the scope of any of the disclosed inventions, the embodiments and/or examples currently described, and the best model of these applications as currently understood.

FIG 1 is a flow chart of a method for manufacturing a trench split-gate device provided by an embodiment of the present disclosure;

FIG 2 is a flow chart of a method for manufacturing a trench split-gate device provided by a specific embodiment of the present disclosure;

FIG 3A ~ FIG 3G are schematic sectional views of the cell of the trench split-gate device manufactured by the method in FIG 2;

FIG 4 is a flow chart of the method for manufacturing a trench split-gate device provided by another specific embodiment of the present disclosure;

FIG 5A ∼ 5H are schematic sectional views of the cell of trench split-gate devices manufactured by the method in FIG 4.


DETAILED DESCRIPTION OF THE EMBODIMENTS



[0010] As shown in FIG 1, a method for manufacturing a trench split-gate device is provided by the present disclosure, which comprises the following steps:

At S100: a semiconductor substrate is etched to form a trench.

At S 110: an oxide is deposited in the trench to form a floating gate oxide layer, in which the floating gate oxide layer is gradually thickened from top to bottom along the side wall of the trench, and a thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench.

At S120: polysilicon is deposited into the trench to form a floating gate polycrystalline layer.

At S130: an insulating medium is grown on the upper surface of the floating gate polycrystalline layer to form an isolation layer.

At S140: a control gate is formed on the isolation layer in the trench.



[0011] In the above method for manufacturing a trench split-gate device, a gradually changing floating gate oxide layer is grown on the trench side wall, in order that the thickness of the floating gate oxide layer is gradually increased from the isolation layer position to the bottom position of the trench and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench. The thickness of the floating gate oxide gradually changing can reduce the width of the trench and further reduce the cell area and the specific on resistance of the device. In addition, the thickness of the floating gate oxide layer is gradually increased from the side wall of the trench, and the thickness of the floating gate oxide at the lower part of the side wall of the trench is the same as that at the bottom of the trench. Said floating gate oxide layer also adapts to the continually increasing voltage from the control gate to the bottom of the trench, such that the device will not be broken down due to a non-adaptive voltage.

[0012] In one of embodiments, etching the semiconductor substrate to form a trench specifically comprises: etching the semiconductor substrate vertically to make the side wall of the trench vertical up and down. The step of depositing an oxide into the trench to form a floating gate oxide layer comprises: forming a first oxide layer on the inner surface of the trench; forming a second oxide layer on the first oxide layer using high density plasma chemical vapor deposition process in which the thickness of the second oxide layer is controlled to gradually increase from top to bottom along the trench side wall and the thickness of the second oxide layer at the lower part of the side wall of the trench is the same as that of the second oxide layer at the bottom of the trench. In the example, by controlling the pressure of the reaction chamber and the flow rate of the reaction gas flowing into the reaction chamber, the thickness of the second oxide layer along the side wall of the trench can be controlled to gradually increase.

[0013] Specifically, referring to FIG 2, the method for manufacturing the trench split-gate device according to the embodiment specifically comprises the following steps:
At S200: a semiconductor substrate is etched to form a trench.

[0014] A semiconductor substrate is a kind of semiconductor material, which provides mechanical supports and electrical properties for manufacturing a transistor and an integrated circuit. In the present embodiment, the semiconductor substrate can include semiconductor elements such as monocrystal, polycrystalline, or amorphous silicon or germanium, and can also include a mixed semiconductor structure such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof.

[0015] Specifically, referring to FIG 3A, the semiconductor substrate includes a highly doped bulk layer 100 and a lightly doped epitaxial layer 110. The doping types of the bulk layer 100 and the epitaxial layer 110 are the same, which can be N-type impurity. In this disclosure, the epitaxial layer 110 is etched vertically from top to bottom using dry etching process in order that the side wall of the trench 120 formed by etching is vertical up and down.

[0016] At S210: a first oxide layer is formed on the inner surface of the trench.

[0017] In the embodiment, a first oxide layer can be formed on the inner surface of the trench using the furnace tube oxidation method, and the first oxide layer can be silicon oxide.

[0018] Specifically, the semiconductor substrate can be placed in a certain gas atmosphere and a certain temperature atmosphere to have the semiconductor substrate react with oxygen or water vapor to generate silicon dioxide during the preparation. The gas atmosphere refers to nitrogen and/or oxygen and/or hydrogen, and the temperature range is from about 700°C raised to about 1100°C and then back to about 700°C. As shown in FIG 3B, in the embodiment, the thickness of the first oxide layer 121 in the trench 120 is the same everywhere.

[0019] At S220: a second oxide layer is formed on the first oxide layer using high density plasma chemical vapor deposition process. By controlling the pressure of the reaction chamber and the flow rate of the reaction gas flowing into the reaction chamber, the thickness of the second oxide layer is gradually increased from top to bottom along the side wall of the trench, and the thickness of the second oxide layer at the lower part of the side wall of the trench is the same as that of the second oxide layer at the bottom of the trench.

[0020] As shown in FIG 3C, after the preparation of the first oxide layer 121 is completed, a second oxide layer 122 is deposited on the surface of the first oxide layer 121 at the bottom of the trench 120 using high density plasma chemical vapor deposition (HDP CVD) process, in which the second oxide layer 122 can be silicon oxide. During the preparation, silane, oxygen, hydrogen, helium and the like reaction gases flow into the reaction chamber. During the deposition process, by controlling the pressure of the reaction chamber and the flow rate of the reaction gas flowing into the reaction chamber, the amount of silicon dioxide attached to the side wall and the bottom of the trench 120 generated by the reaction is controlled. Firstly, a certain amount of reaction gas flows into the reaction chamber under a certain pressure. The reaction gas reaches the bottom of the trench 120 under the pressure of the cavity, and reacts at the bottom of the trench 120 to generate oxidation products with thicker thickness. Then, the pressure is reduced at regular intervals and the flow rate of the reaction gas flowing into the reaction chamber is reduced. At a lower pressure, the reaction gas is gradually raised and a deposition reaction is taken place on the side wall of the trench 120 to generate oxidation products with thinner thickness. Further, the thickness of the second oxide layer 122 deposited on the side wall of the trench 120 is gradually reduced from bottom to up. The thickness of the second oxide layer 122 at the lower part of the side wall of the trench 120 is the same as that of the second oxide layer 122 deposited at the bottom the trench 120. Therefore, the thickness of the floating gate oxide constituted of the first oxide layer 121 and the second oxide layer 22 is gradually increased from top to bottom along the side wall of the trench, and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench. In the present embodiment, the flow rate of the reaction gas can be 15% - 20% for silane, 20% - 25% for oxygen, 25% - 35% for hydrogen and 20% - 40% for helium.

[0021] Compared with the ordinary atmospheric pressure chemical vapor deposition method, the thickness of the second oxide layer 122 formed by the deposition can be controlled by the HDP CVD process used in the embodiment of present disclosure, such that the thickness of the second oxide layer 122 deposited on the side wall of the trench 120 is gradually increased from the top to the bottom, and the thickness of the second oxide layer 122 at the bottom of the trench 120 is the same as that of the second oxide layer 122 at the lower part of the side wall of the trench 120. On the one hand, increasing the thickness of the the floating gate oxide at the bottom of the trench can make the device adapt to withstand voltage and avoid the device to be broken down by high voltage. On the other hand, under the condition that the thickness of the floating gate oxide at the bottom of the trench is the same, the floating gate oxide layer on the side wall of the trench in the present disclosure is thinner than the floating gate oxide layer on the side wall of the trench in a traditional process, and the width of the trench is smaller than that of the trench in a traditional process. Therefore the cell area is reduced, the number of cell per unit area on the chip is increased and the specific on resistance of the device is reduced.

[0022] At S230: polysilicon is deposited into the trench to form a floating gate polycrystalline layer.

[0023] Referring to FIG 3D, in the embodiment, polysilicon can be deposited in the trench using low-pressure chemical vapor deposition method to form a floating gate polycrystalline layer 123. After the polysilicon is filled in the trench 120, the polysilicon can be etched back or ground in order that the upper surface of the floating gate polycrystalline layer 123 is lower than the lower surface of the P-type well region formed in the subsequent process.

[0024] At S240: an insulating medium is grown on the surface of floating gate polycrystalline layer to form an isolation layer.

[0025] Referring to FIG 3E, in this embodiment, insulating medium may be grown on the surface of the floating gate polycrystalline layer 123 using thermal oxidation method or chemical vapor deposition method to form an isolation layer 124, in which the insulating medium can be silicon nitride, silicon oxide or silicon oxynitride, and the isolation layer 124 is used to isolate the floating gate polycrystalline layer 123 from the control gate formed in the subsequent process.

[0026] Further, before the step of forming the isolation layer 124 on the upper surface of the floating gate polycrystalline layer 123, the method further comprises a step of removing the first oxide layer 121 above the floating gate polycrystalline layer 123. Specifically, the first oxide layer 121 above the floating gate polycrystalline layer 123 can be removed using dry etching technology.

[0027] At S250: a control gate is formed on the isolation layer in the trench.

[0028] Further, referring to FIG 3F, the step of forming a control gate on the isolation layer 124 in the trench 120 specifically includes: forming a control gate oxide layer 125 on the trench side wall above the isolation layer 124; forming a control gate polycrystalline layer 126 by depositing the polysilicon on the isolation layer 124 in the trench 120 where the control gate polycrystalline layer 126 is adjacent to the control gate oxide layer 125; etching back or grinding the control gate polycrystalline layer 126. The control gate is constituted by the control gate oxide layer 125 and the control gate polycrystalline layer 126 together.

[0029] Specifically, in the present embodiment, the polysilicon can be deposited in the trench 120 using low-pressure chemical vapor deposition method, and the polysilicon is doped at the same time. The polysilicon outside the trench 120 can be etched using dry etching process to form a control gate.

[0030] In the method for manufacturing a trench split-gate device provided by the embodiment, by using the high-density plasma chemical vapor deposition process, the thickness of the second oxide layer at the bottom and on the side wall of the trench can be adjusted by adjusting the pressure of the reaction chamber and the flow rate of the reaction gas. The thickness of the floating gate oxide on the side wall of the trench is gradually increased from top to bottom, and the thickness of the floating gate oxide at the lower part of the side wall of the trench is the same as that of the floating gate oxide at the bottom of the trench. Therefore, on the one hand, it can meet the requirement of withstanding the gradually changing voltage, and at the same time, the width of the trench can be reduced by the gradually changing thickness of the floating gate oxide, threby further reducing the cell area, increasing the number of cell receivable per unit area on the chip, and reducing the specific on resistance of the device.

[0031] Referring to FIG 3G, after the step of forming a control gate on the isolation layer in the trench, the method further comprises: forming a P-type well region 130 by injecting the P-type impurity to push junctions at both sides of the trench 120. An N-type heavily doped region 131 is formed in the P-well region 130 on both sides of the trench 120 by injecting a highly doped N-type impurity. Then, an isolation oxide layer 140 is formed on the control gate using thermal oxidation method. The isolated oxide layer 140 is etched to form a contact hole 141 penetrating the P-type well region, and the N-type heavily doped region 131 is located between the contact hole 141 and the trench 120. Heavily doped P-type impurity is injected into P-well region through the contact hole 141 to form a P-type heavily doped region 132. After that, the contact hole 141 is filled, and finally a source electrode is formed on the isolation oxide layer 140, and a drain electrode is formed on the lower surface of the bulk layer 100, and thus the basic structure of the trench split-gate device is formed.

[0032] A trench split-gate device is also provided by the embodiment, which is manufactured according to the steps of the method shown in FIG 2. Specifically, as shown in FIG 3G, the trench split-gate device includes a semiconductor substrate, which includes a bulk layer 100 and an epitaxial layer 110. A trench 120 is provided in the semiconductor substrate, the trench 120 is arranged in the epitaxial layer 110, and the side wall of the trench 120 is vertical up and down. The inner wall of the trench 120 is provided with a floating gate oxide layer. The floating gate oxide includes a first oxide layer 121 on the inner wall of the trench 120 and a second oxide layer 122 on the first oxide layer 121. The thickness of the first oxide layer 121 on the side wall of the trench 120 is uniform everywhere, the thickness of the second oxide layer 122 is gradually increased from top to bottom along the side wall of the trench 120, and the thickness of the second oxide layer 122 at the lower part of the side wall of the trench 120 is the same as that of the second oxide layer 122 at the bottom of the trench 120. Therefore, the total thickness of the floating gate oxide constituted of the first oxide layer 121 and the second oxide layer 122 is gradually increased from top to bottom along the side wall of the trench 120, and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench 120 is the same as that of the floating gate oxide layer at the bottom of the trench 120. A floating gate polycrystalline layer 123 is provided on the surface of the floating gate oxide layer. A floating gate structure is constituted of floating gate polycrystalline layer 123 and floating gate oxide layer together. The upper surface of the floating gate polycrystalline layer 123 is provided with an isolation layer 124. A control gate polycrystalline layer 126 and a control gate oxide layer 125 are provided on the isolation layer 124. A control gate structure is constituted of the control gate polycrystalline layer 126 and the control gate oxide layer 125 together.

[0033] In the trench split-gate device provided by the embodiment of the disclosure, the second oxide layer is formed using HDP CVD process at the bottom and on side wall of the trench, such that the thickness of the second oxide layer is gradually increased from top to bottom along the side wall of the trench, and the thickness of the second oxide layer at the lower part of the side wall of the trench is the same as that of the second oxide layer at the bottom of the trench. Furthermore, the total thickness of the floating gate oxide constituted of the first oxide layer and the second oxide layer is gradually increased from top to bottom along the side wall of the trench, and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench. Therefore, on the one hand, it can meet requirement of withstanding the gradually changing voltage, and at the same time, the width of the trench can be reduced by the gradually changing thickness of the floating gate oxide, and thus the cell area is further reduced and the specific on resistance of the device is reduced.

[0034] In another embodiment, the step of etching a semiconductor substrate to form a trench specifically comprises: etching the semiconductor substrate to form a vertical upper half trench. The semiconductor substrate is etched obliquely downward from the bottom of the upper half trench to form a lower half trench extending downward from the bottom of the half trench and with a width gradually increased from the top to the bottom. And the bottom of the lower half trench is concave arc-shaped. The step of depositing oxide into the trench to form a floating gate oxide layer includes: forming a first oxide layer on the inner surface of the trench; etching the first oxide layer to make the side wall of the first oxide layer vertical up and down; forming a second oxide layer on the first oxide layer at the bottom of the lower half trench using high density plasma chemical vapor deposition process, in which the thickness of the floating gate oxide layer constituted of the first oxide layer and the second oxide layer is gradually increased from top to bottom along the side wall of the trench. The thickness of the floating gate oxide at the lower part of the side wall of the lower half of the trench is the same as that of the floating gate oxide at the bottom of the lower half of the trench.

[0035] Specifically, referring to FIG 4, in the present embodiment, the method for manufacturing the trench split-gate device specifically includes the following steps:
At S300: a semiconductor substrate is etched to form a vertical upper half trench.

[0036] Referring to FIG 5A, the semiconductor substrate includes a bulk layer 200 and an epitaxial layer 210. In this embodiment, the semiconductor substrate is vertically etched using dry etching technique to form a vertically downward upper half trench 221 in the epitaxial layer 210. During the etching process, the polymer generated by the reaction of the etching gas and the silicon substrate is reserved to protect the upper half trench 221, so that the surface of the upper half trench 221 will not be etched when proceeding with the next step.

[0037] At S310: the semiconductor substrate is etched obliquely downward from the bottom of the upper half trench to form a lower half trench extending downward from the bottom of the upper half trench and with a width gradually increased from the top to the bottom.

[0038] Referring to FIG 5B, similarly using the dry etching technology, the epitaxial layer 211 is etched obliquely downward from the bottom of the vertical upper trench 221 to form the lower half trench 222 extending downward from the bottom of the upper half trench 221 and with a width gradually increased from the top to the bottom, and the bottom of the lower half trench 222 is concave arc-shaped. The trench 220 is constituted of the upper half trench 221 and the lower half trench 222 together. After the etching of trench 220 is completed, the step of acid pickling is carried out to remove the polymer attached on the surface of trench 220 generated by etching.

[0039] At S320: a first oxide layer is formed on the inner surface of the trench.

[0040] Referring to FIG 5C, a first oxide layer 223 can be oxidizedly formed on the inner surface of trench 220 using furnace tube oxidation method or CVD process. Specifically, in the present embodiment, the first oxide layer 223 is grown by oxidizing on the surface of trench 220 using furnace tube oxidation method.

[0041] At S330: the first oxide layer is etched to enable the side wall of the first oxide layer vertical up and down.

[0042] After the growing process is completed, the first oxide layer 223 is dry etched, so that the side wall of the first oxide layer 223 of the inner wall of the trench is vertical up and down, and the thickness of the first oxide layer 223 of the side wall of the lower half trench 222 is gradually increased from top to bottom.

[0043] At S340: a second oxide layer is formed on the first oxide layer at the bottom of the lower half trench using high density plasma chemical vapor deposition process, in which the thickness of the floating gate oxide layer formed by the combination of the first oxide layer and the second oxide layer gradually increased from top to bottom along the side wall of the trench, and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench.

[0044] Referring to FIG 5D, a second oxide layer 224 is deposited on the first oxide layer 223 at the bottom of the lower half trench 222 using HDP CVD deposition method to thicken the floating gate oxide layer at the bottom of the lower half trench 222 and enhance the performance of the device withstanding voltage. Since the thickness of the first oxide layer 223 on the side wall of the lower half trench 222 gradually increases from top to bottom along the lower half trench 222, and the second oxide layer 224 is located on the first oxide layer 223 at the bottom of the lower half trench 222, the total thickness of the floating gate oxide layer formed by the first oxide layer 223 and the second oxide layer 224 gradually increases from top to bottom along the side wall of the lower half trench 222, and the thickness of the floating gate oxide layer at the lower part of the side wall of the lower half trench 222 is the same as that of the floating gate oxide at the bottom of half trench 222.

[0045] At S350: polysilicon is deposited into the trench to form a floating gate polycrystalline layer.

[0046] As shown in FIG 5E, in the present embodiment, polysilicon can be deposited in the trench 220 using low-pressure chemical vapor deposition method to form a floating gate polycrystalline layer 225. Furthermore, after the polysilicon is filled in the trench 220, the polysilicon can be etched back or ground in order that the upper surface of the floating gate polycrystalline layer 225 is lower than the lower surface of the P-type well region formed in the subsequent processes.

[0047] At S360: an insulating medium is grown on the surface of the floating gate polycrystalline layer to form an isolation layer.

[0048] As shown in FIG 5F, insulating medium can be deposited on the surface of floating gate polycrystalline layer 225 using thermal oxidation method or chemical vapor deposition method to form an isolation layer 226. The insulating medium can be silicon nitride or silicon oxide or silicon oxynitride, which is used for isolating the floating gate polycrystalline layer 225 and the control gate formed in subsequent processes.

[0049] Further, before the step of forming an isolation layer 226 on the upper surface of the floating gate polycrystalline layer 225, the method can further include the step of removing the first oxide layer 222 above the floating gate polycrystalline layer 225. Specifically, the first oxide layer 223 above the floating gate polycrystalline layer 225 can be removed using dry etching technology.

[0050] At S370: a control gate is formed on the isolation layer in the trench.

[0051] Further, as shown in FIG 5G, forming a control gate on the isolation layer 226 in the trench 220 specifically includes: forming a control gate oxide layer 227 on the side wall of the trench above the isolation layer 226; depositing polysilicon on the isolation layer 226 in the trench 220 to form a control gate polycrystalline layer 228 in which the control gate polycrystalline layer 228 is adjacent to the control gate oxide layer 227; and etching back or grinding the control gate polycrystalline layer 228 to form the control gate, where the control gate includes a control gate oxide layer 227 and a control gate polycrystalline layer 228.

[0052] Specifically, in this embodiment, polysilicon can be deposited in trench 220 using low-pressure chemical vapor deposition method, and polysilicon is doped at the same time. The polysilicon outside the trench 220 can be etched using dry etching process to form the control gate.

[0053] In the method for manufacturing the trench split-gate device provided by the present embodiment, the lower half trench with the width gradually increased from the top to the bottom is formed by etching the vertical upper half trench firstly and then etching obliquely downward from the bottom of the upper half trench. The trench is constituted by the upper half trench and the lower half trench together. Then a first oxide layer is grown on the inner side of the trench, in which the thickness of the first oxide layer in the lower half trench gradually increases from top to bottom along the side wall of the lower half trench. Next, a second oxide layer is deposited on the first oxide layer at the bottom of the lower half trench to increase the thickness of the floating gate oxide layer at the bottom of the lower half trench, in order that the total thickness of the floating gate oxide layer constituted of the first oxide layer and the second oxide layer is gradually increase from top to bottom along the side wall of the lower half trench, and the thickness of the floating gate oxide layer at the lower part of the lower half trench is the same as that of the floating gate oxide layer at the bottom of the lower half trench. Therefore, on the one hand, it can meet the requirement of withstanding the gradually changing voltage, and at the same time, it can reduce the cell area and the specific on resistance of the device.

[0054] Referring to FIG 5H, after the step of forming a control gate on the isolation layer in the trench, the method further includes: forming a P-type well region 230 by injecting the P-type impurity to push junctions at both sides of the trench 220. An N-type heavily doped region 231 is formed in the P-type well region 230 on both sides of the trench 220 by injecting highly doped N-type impurity. An isolated oxide layer 240 can be formed on the control gate using thermal oxidation method. A contact hole 241 penetrating the P-type well region is formed by etching the isolated oxide layer 240. The N-type heavily doped region 231 is located between the contact hole 241 and the trench 220. A P-type heavily doped region 232 is formed by injecting heavily doped P-type impurity into P-well region through contact hole 241. After that, the contact hole 241 is filled, and finally a source electrode is formed on the isolation oxide layer 240, a drain electrode is formed on the lower surface of the bulk layer 200, and thus a basic structure of the split-gate device is formed.

[0055] The present embodiment also provides a trench split-gate device, which is manufactured according to the steps of the method shown in FIG 4. Specifically, as shown in FIG 5H, the trench split-gate device includes a semiconductor substrate. The semiconductor substrate includes a bulk layer 200 and an epitaxial layer 210. A trench 220 is provided in the epitaxial layer 210. The trench 220 includes an upper half trench 221 with side wall vertical up and down and a lower half trench 222 extending downward from the bottom of the upper half trench and with a width gradually increased from the top to the bottom. The bottom of the lower half trench is concave arc-shaped. The inner wall of the trench 220 is provided with an oxide layer, which includes a first oxide layer 223 on the inner wall of the trench and a second oxide layer 224 on the first oxide layer 223 at the bottom of the trench. The thickness of the first oxide layer 223 on the inner wall of the lower half trench 222 is gradually increased from top to bottom along the side wall of the lower half trench 222, and the second oxide layer 224 is used to increase the thickness of the floating gate oxide layer at the bottom of the lower half trench 222. Therefore, the total thickness of the floating gate oxide constituted of the first oxide layer 223 and the second oxide layer 224 is gradually increased from top to bottom along the side wall of the lower half trench 222, and the thickness of the floating gate oxide layer at lower part of the side wall of the lower half trench 222 is the same as that of the floating gate oxide layer at the bottom half trench 222. A floating gate polycrystalline layer 225 is provided on the surface of the floating gate oxide layer. The upper surface of the floating gate polycrystalline layer 225 is provided with an isolation layer 226. The side wall of the upper half trench 221 above the isolation layer 226 is provided with a control gate oxide layer 227. The control gate polycrystalline layer 228 is located on the isolation layer 226 and adjacent to the control gate oxide layer 227. The control gate of the trench split-gate device is constituted by the control gate oxide layer 227 and the control gate polycrystalline layer 228 together.

[0056] In the trench split-gate device provided by the embodiment of the invention, the width of the lower half trench is gradually increased from top to bottom, and the thickness of the first oxide layer which is grown on the inner wall of the lower half trench is gradually increased from top to bottom, and the second oxide layer is used to thicken the bottom of the trench, such that the total thickness of the floating gate oxide layer constituted by the first oxide layer and the second oxide layer is gradually increased from top to bottom along the side wall of the lower half trench. The thickness of floating gate oxide at the lower part of the sided wall of the lower half trench is the same as that of the floating gate oxide at the bottom of the lower half trench. Therefore, on the one hand, it can meet the requirement of withstanding the gradually changing voltage. At the same time, the gradually changing thickness of the floating gate oxide can reduce the width of the trench, and further reduce the cell area and the specific on resistance of the device.

[0057] It should be understood that although the steps in the flowchart of FIG 1, FIG 2 and FIG 4 are shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict sequence restriction on the execution of these steps, which can be performed in other orders. Moreover, at least a part of the steps in FIG 1, FIG 2 and FIG 4 may include a plurality of sub steps or stages, which are not necessarily completed at the same time, but can be executed at different times, and their execution sequence is not necessarily in sequence, but can be executed in turn or alternately with at least one part of the sub steps or stages of other steps.


Claims

1. A method for manufacturing a trench split-gate device, comprising:

etching a semiconductor substrate to form a trench;

depositing oxide in the trench to form a floating gate oxide layer, wherein the floating gate oxide layer is gradually thickened from top to bottom along a side wall of the trench, and a thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at a bottom of the trench;

depositing polysilicon into the trench to form a floating gate polycrystalline layer;

growing an insulating medium on an upper surface of the floating gate polycrystalline layer to form an isolation layer; and

forming a control gate on the isolation layer in the trench.


 
2. The method according to claim 1, wherein said etching a semiconductor substrate to form a trench specifically comprises: etching the semiconductor substrate vertically to enable the side wall of the trench vertical up and down.
 
3. The method according to claim 2, wherein the step of depositing oxide in the trench to form a floating gate oxide layer comprises:

forming a first oxide layer on an inner surface of the trench;

forming a second oxide layer on the first oxide layer;

controlling the second oxide layer to thicken from top to bottom along the side wall of the trench, a thickness of the second oxide layer at the lower part of the side wall of the trench being the same as that of the second oxide layer at the bottom of the trench.


 
4. The method according to claim 3, wherein a thickness of the first oxide layer on the inner surface of the trench is the same everywhere.
 
5. The method according to claim 4, wherein said controlling the second oxide layer to thicken from top to bottom along the side wall of the trench comprises:
gradually thickening the second oxide layer from top to bottom along the side wall of the trench by controlling a pressure of a reaction chamber and a flow rate of a gas flowing into the reaction chamber, the thickness of the second oxide layer at the lower part of the side wall of the trench being the same as that of the second oxide layer at bottom of the trench.
 
6. The method according to claim 5, wherein the flow rate of the reaction gas includes: 15% - 20% for silane, 20% - 25% for oxygen, 25% - 35% for hydrogen, and 20% - 40% for helium.
 
7. The method according to claim 1, wherein said etching a semiconductor substrate to form a trench specifically comprises:

etching the semiconductor substrate to form a vertical upper half trench;

etching the semiconductor substrate obliquely downward from a bottom of the upper half trench to form a lower half trench extending downward from the bottom of the upper half trench and with a width gradually increased from top to bottom, and a bottom of the lower half trench being concave arc-shaped, and the trench being constituted by the upper half trench and the lower half trench together.


 
8. The method according to claim 7, wherein the step of depositing oxides in the trench to form a floating gate oxide layer comprises:

forming a first oxide layer on an inner surface of the trench;

etching the first oxide layer to enable a side wall of the first oxide layer vertical up and down;

forming a second oxide layer on the first oxide layer at the bottom of the lower half trench using high density plasma chemical vapor deposition process, wherein the floating gate oxide layer is gradually thickened from top to bottom along a side wall of the lower half trench, and the thickness of the floating gate oxide layer at a lower part of the side wall of the lower half trench is the same as that of the floating gate oxide layer at the bottom of the lower half trench.


 
9. The method according to claim 8, wherein said forming a first oxide layer on an inner surface of the trench specifically comprises: forming the first oxide layer on the inner surface of the trench using thermal oxidation method.
 
10. The method according to claim 1, wherein before the step of growing an insulating medium on an upper surface of the floating gate polycrystalline layer to form an isolation layer, the method further comprises a step of removing the first oxide layer above the floating gate polycrystalline layer.
 
11. The method according to any one of claims 1-10, wherein the step of forming a control gate on the isolation layer in the trench comprises:

forming a control gate oxide layer on the side wall of the trench above the isolation layer;

depositing polysilicon on the isolation layer in the trench to form a control gate polycrystalline layer;

etching back or grinding the control gate polycrystalline layer to form the control gate.


 
12. A trench split-gate device, comprising:

a semiconductor substrate in which a trench is provided;

a floating gate oxide layer provided on an inner wall of the trench, a thickness of the floating gate oxide layer being gradually increased along a side wall of the trench to a bottom of the trench, and the thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench;

a floating gate polycrystalline layer provided on a surface of the floating gate oxide layer;

an isolation layer provided on the floating gate polycrystalline layer; and

a control gate provided on the isolation layer to control on and off of the device.


 
13. The trench split-gate device according to claim 12, wherein the side wall of the trench is vertical from top to bottom, and the floating gate oxide layer includes a first oxide layer on the inner wall of the trench and a second oxide layer on the first oxide layer, the second oxide layer being gradually thickened from top to bottom along the side wall of the trench, wherein the thickness of the first oxide layer on the inner wall of the trench is the same everywhere;
a thickness of the second oxide layer at the lower part of the side wall of the trench being the same as that of the second oxide layer at the bottom of the trench.
 
14. The trench split-gate device according to claim 13, wherein the trench includes an upper half trench and a lower half trench, a width of the lower half trench is gradually increased from a position of the isolation layer to a position of a bottom of the lower half trench, and the bottom of the lower half trench is concave arc-shaped.
 
15. The trench split-gate device according to claim 14, wherein the floating gate oxide layer includes a first oxide layer on the inner wall of the trench and a second oxide layer provided on the first oxide layer and at the bottom of the trench, and the first oxide layer is gradually thickened from top to bottom along the side wall of the lower half trench.
 




Drawing































REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description