(19)
(11)EP 3 828 932 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
07.09.2022 Bulletin 2022/36

(21)Application number: 19212580.5

(22)Date of filing:  29.11.2019
(51)International Patent Classification (IPC): 
H01L 27/146(2006.01)
(52)Cooperative Patent Classification (CPC):
H01L 27/1463; H01L 27/1464; H01L 27/14683

(54)

METHOD FOR MANUFACTURING A SENSOR DEVICE WITH A BURIED DEEP TRENCH STRUCTURE AND SENSOR DEVICE

VERFAHREN ZUR HERSTELLUNG EINER SENSORVORRICHTUNG MIT EINER EINGELASSENEN GRABENSTRUKTUR UND SENSORVORRICHTUNG

PROCÉDÉ DE FABRICATION D'UN DISPOSITIF DE CAPTEUR DOTÉ D'UNE STRUCTURE ENTERRÉE EN TRANCHES PROFONDES ET DISPOSITIF DE CAPTEUR


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(43)Date of publication of application:
02.06.2021 Bulletin 2021/22

(73)Proprietor: Infineon Technologies Dresden GmbH & Co . KG
01099 Dresden (DE)

(72)Inventors:
  • GLEMET, Magali
    01109 Dresden (DE)
  • BINDER, Boris
    01067 Dresden (DE)
  • FEICK, Henning
    01099 Dresden (DE)
  • OFFENBERG, Dirk
    01099 Dresden (DE)

(74)Representative: Hersina, Günter et al
Schoppe, Zimmermann, Stöckeler Zinkler, Schenk & Partner mbB Patentanwälte Radlkoferstrasse 2
81373 München
81373 München (DE)


(56)References cited: : 
US-A1- 2015 380 447
US-A1- 2019 096 929
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    GENERAL DESCRIPTION



    [0001] Embodiments of the present disclosure relate to the field of manufacturing sensor devices in a semiconductor substrate. More specifically, embodiments relate to the field of manufacturing sensor devices with a buried deep trench structure, being particularly beneficial in the field of optical sensor devices, such as image sensor arrays or time of flight sensors, by providing a crosstalk prevention and drift field generation.

    TECHNICAL BACKGROUND



    [0002] Photosensitive components have become an indispensable part of the semiconductor market. These chips, such as optical sensors, are becoming smaller and have to achieve the required luminous efficacy even with a significantly reduced surface area. For image sensor arrays it is very important to suppress crosstalk between the individual pixels of the array, in particular for small pixels or in the case of high pixel densities. Therefore, deep trenches can be used to prevent optical and electrical crosstalk between the pixels. Deep trenches can be processed from the wafer front side, for example a front side of a semiconductor substrate, with the drawback of surface area consumption. Alternatively, trenches can be processed from the backside of the semiconductor substrate, resulting in a more cost intensive process. The document US2019/096929A is a relevant prior art.

    [0003] Furthermore, for example in time of flight sensor devices, electrical drift fields are needed to accelerate generated charge carriers, for example electrons or holes. This can be done by special arrangements of doping profiles, leading to cost intensive process sequences. The doping profiles may be introduced into the semiconductor substrate by a sequence of epitaxial depositions, ion implantations and temperature processes. These processes are complicated, expensive and little reproducible.

    [0004] Therefore, there is a need for a new method for efficiently manufacturing sensor devices having an effective crosstalk prevention and drift field generation.

    [0005] Such a method is provided by the method for manufacturing a sensor device with a buried deep trench structure according to claim 1. In addition, specific implementations of different embodiments of the method for manufacturing a sensor device are defined in the dependent claims.

    Summary



    [0006] According to an embodiment, a method for manufacturing a sensor device with a buried deep trench structure comprises: providing a semiconductor substrate having a sensing region, which extends vertically below a main surface region of the semiconductor substrate into the semiconductor substrate, wherein a masking layer is arranged on the main surface region of the semiconductor substrate; etching a deep trench structure into the semiconductor substrate through revealed areas of the masking layer for arranging the deep trench structure laterally relative to the sensing region and vertically from the main surface region into the semiconductor substrate; selectively depositing by epitaxy a doped semiconductor layer on a surface region of the deep trench structure for providing a coated deep trench structure; at least partially removing the masking layer for revealing the main surface region of the semiconductor substrate; depositing a semiconductor capping layer on the main surface region of the semiconductor substrate, wherein the semiconductor capping layer covers and closes the coated deep trench structure and forms together with the semiconductor substrate a thickened semiconductor substrate having the buried deep trench structure; and out-diffusing dopants of the doped semiconductor layer into the thickened semiconductor substrate wherein the out-diffused dopants provide a trench doping region that extends from the doped semiconductor layer into the semiconductor substrate.

    [0007] According to a further embodiment, a sensor device with a buried deep trench structure comprises: a semiconductor substrate having a sensing region, which extends vertically below a main surface region of the semiconductor substrate into the semiconductor substrate; a semiconductor capping layer that extends vertically below the main surface region of the semiconductor substrate into the semiconductor substrate; a buried deep trench structure that extends vertically below the capping layer into the semiconductor substrate and laterally relative to the sensing region, wherein the buried deep trench structure comprises a doped semiconductor layer, the doped semiconductor layer extending from a surface region of the buried deep trench structure into the semiconductor substrate; a trench doping region that extends from the doped semiconductor layer of the buried deep trench structure into the semiconductor substrate; electronic circuitry for the sensing region in a capping region of the thickened semiconductor substrate vertically above the buried deep trench structure 50.

    Brief Description of the Figures



    [0008] Embodiments of the method for manufacturing a sensor device with a buried deep trench structure are described herein making reference to the appended drawings and figures.
    Fig. 1
    shows an exemplary process flow (flowchart) of a method for manufacturing a sensor device with a buried trench structure according to an embodiment.
    Figs. 2a-g
    show schematic cross-sectional views (schematic snapshots) of a semiconductor substrate and manufactured elements of the sensor device at different stages of the manufacturing method according to an embodiment.
    Figs. 3a-d
    show schematic top views of a semiconductor substrate and manufactured elements of the sensor device at different stages of the manufacturing method according to an embodiment.
    Figs. 4a-f
    show schematic top views of semiconductor substrates and manufactured elements of the sensor device according to further embodiments.
    Fig. 5
    shows a schematic cross-sectional view of a semiconductor substrate and manufactured elements of a sensor device according to an embodiment.
    Fig. 6
    shows schematic cross-sectional views (schematic snapshots) of a semiconductor substrate and elements of the manufactured sensor at different stages of the manufacturing according to a further embodiment.
    Figs. 7a-e
    show cross-sectional electron microscopy images of a semiconductor substrate at different stages of the manufacturing method according to an embodiment.
    Fig. 8
    shows a lateral distribution of dopants of a trench doping region of a sensor device according to an embodiment of the manufacturing method.
    Fig. 9
    shows schematic cross-sectional views (schematic snapshots) of a semiconductor substrate and elements of the sensor device at different stages of the manufacturing according to a further embodiment.
    Fig. 10
    shows schematic cross-sectional views (schematic snapshots) of a semiconductor substrate and elements of the sensor device at different stages of the manufacturing according to a further embodiment.
    Fig. 11
    shows schematic cross-sectional views (schematic snapshots) of a semiconductor substrate and elements of the sensor device at different stages of the manufacturing according to a further embodiment.
    Fig. 12
    shows a schematic cross-sectional view of a sensor device with a buried deep trench structure according to an embodiment.


    [0009] Before discussing the present embodiments in further detail using the drawings, it is pointed out that in the figures and the specification identical elements and elements having the same functionality and/or the same technical or physical effect are usually provided with the same reference numbers or are identified with the same name, so that the description of these elements and of the functionality thereof as illustrated in the different embodiments are mutually exchangeable or may be applied to one another in the different embodiments.

    Detailed Description of Illustrative Embodiments



    [0010] In the following description, embodiments are discussed in detail, however, it should be appreciated that the embodiments provide many applicable concepts that can be embodied in a wide variety of semiconductor devices. The specific embodiments discussed are merely illustrative of specific ways to make and use the present concept, and do not limit the scope of the embodiments. In the following description of embodiments, the same or similar elements having the same function have associated therewith the same reference signs or the same name, and a description of such elements will not be repeated for every embodiment. Moreover, features of the different embodiments described hereinafter may be combined with each other, unless specifically noted otherwise.

    [0011] It is understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly" connected to another element, "connected" or "coupled," there are no intermediate elements. Other terms used to describe the relationship between elements should be construed in a similar fashion (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", and "on" versus "directly on", etc.).

    [0012] For facilitating the description of the different embodiments, the figures comprise a Cartesian coordinate system x, y, z, wherein the x-y-plane corresponds, i.e. is parallel, to the main surface region of the semiconductor substrate, and wherein the depth direction vertical to the main surface region and into the semiconductor substrate corresponds to the "z" direction, i.e. is parallel to the z direction. In the following description, the term "lateral" means a direction parallel to the x-direction, wherein the term "vertical" means a direction parallel to the z-direction.

    [0013] The terms "above" or "vertically above" or "top" refer to a relative position located in the vertical direction which extends from the main surface region of the semiconductor substrate and points away from the semiconductor substrate. Similarly, the terms "below" or "vertically below" or "bottom" refer to a relative position located in the vertical direction which extends from the main surface region of the semiconductor substrate and points into the semiconductor substrate.

    [0014] Fig. 1 and Figs. 2a-g show an exemplary process flow or flowchart of a method 100 of manufacturing a sensor device with a buried trench structure according to an embodiment. In order to facilitate the presentation, the description of Fig. 1 already includes reference numbers of the embodiment shown in Figs. 2a-g. The references numbers relating to Figs. 2a-g are represented by two-digit numbers.

    [0015] As shown in Fig. 1, the method 100 comprises a step 110 of providing a semiconductor substrate 10, referred to as substrate 10 hereafter for the sake of clarity. The substrate 10 has a sensing region 14, which extends vertically below a main surface region 12 of the substrate 10 into the substrate 10, wherein a masking layer 16 is arranged on the main surface region 12 of the substrate 10. In step 120, a deep trench structure 20 is etched into the substrate 10 through revealed areas 18 of the masking layer 16. The deep trench structure 20 extends vertically from the main surface region 12 into the substrate 10 and is arranged laterally relative to the sensing region 14. The deep trench structure 20 may border the sensing region 14 directly, or may be at a distance from the sensing region 14. In step 130, a doped semiconductor layer 32, referred to as doped layer 32 in the following, is selectively deposited by epitaxy on a surface region 22 of the deep trench structure 20 for providing a coated deep trench structure 30. The doped layer 32 may have a defined thickness and a defined doping concentration. The masking layer 16 prevents the main surface region 12 from being covered with dopants during the selective epitaxial deposition 130. In step 140, the masking layer 16 is at least partially removed for revealing the main surface region 12 of the substrate 10. In step 150, a semiconductor capping layer 52, referred to as capping layer 52 hereafter, is deposited on the main surface region 12 of the substrate 10 to cover and close the coated deep trench structure 30. The capping layer 52 forms together with the substrate 10 a thickened semiconductor substrate 10', referred to as thickened substrate 10' in the following. The thickened substrate 10' has the coated deep trench structure 30 buried therein, i.e. has the buried deep trench structure 50. The buried deep trench structure 50 may be configured to form a barrier to optical and electronic signals. In step 160, dopants of the doped layer 32 are out-diffused into the thickened substrate 10', the out-diffused dopants providing a trench doping region 60 that extends from the doped layer 32 into the thickened substrate 10'.

    [0016] Thus, embodiments describe a process for manufacturing a sensor device with a buried deep trench structure 50, so that the buried deep trench structure 50 may be etched from a front side of a wafer. The etching 120 of the deep trench structure 20 from the main surface region 12 provides an efficient way to arrange the deep trench structure 20 close by the sensing region 14 which also extends vertically below the main surface region 12. Still, after burying the deep trench structure, the main surface region 12', including regions vertically above the buried deep trench structure 50, is available to be used in the further process steps. This efficiently solves the problem of surface consumption of deep trench structures in sensor devices. In other words, trenches may be etched from the front side, what is an established process, but without any front side area consumption due to an overgrowth, for example with silicon epitaxy. The avoidance of surface area consumption by the deep trenches may be beneficial for a further process flow. For example, electronic circuitry, such as readout circuitry, may be arranged, e.g. placed or manufactured directly, on the main surface region 12' vertically above the buried deep trench structure 50, for example readout circuitry of pixels on the surface, for example of pixel devices forming a part of a sensor device. At the same time, maximizing the amount of available surface area is favorable to the luminous efficacy of an optical sensor. In other words, the presented disclosure uses deep trenches, for example empty deep trenches, with a doping profile and solves the space problem. After closing the deep trenches, an arbitrary semiconductor process flow may be carried out to further process the obtained substrate 10'. The trenches, e.g. of the buried deep trench structure, are closed at the top but may be still empty in the depth, what may give a good characteristic for an optical component of a crosstalk behavior of the sensor device to be manufactured.

    [0017] For example, the sensing region 14 and a neighboring sensing region within the substrate each form a part of different pixel devices of a sensor device. The deep trench structure may prevent optical and/or electronic crosstalk between the different pixel devices. That is, the deep trench structure 20 may attenuate or prohibit a transfer of an electronic or an optical signal out of the sensing region 14 and/or may attenuate or prohibit a transfer of an electronic or an optical signal into a neighboring region of the substrate, for example a neighboring further sensing region. For example, an electromagnetic signal to be detected in the sensing region 14 may be reflected at the interface between the substrate 10 and the deep trench structure 50. Thus, the electromagnetic signal may remain within the sensing region 14, thus increasing the probability of the electromagnetic signal to be detected in the sensing region 14. Further, due to the reflection of the electromagnetic signal, the electromagnetic signal may be prevented from entering neighboring regions of the substrate. For example, the electromagnetic signal may be prevented from entering a neighboring sensing region, preventing an erroneous or undesirable detection of the electromagnetic signal in another sensing region than the sensing region 14. For example, the reflection of an electromagnetic signal at the interface between the substrate 10 and the deep trench structure 50 may occur due to total internal reflection, such that the electromagnetic signal may be reflected entirely or almost entirely. Further, the deep trench structure 20 may hinder charge carries to move into neighboring regions of the substrate 10. Thus, the deep trench structure 20 increases the probability that a charge carrier is detected within the sensing region 14 within which the charge carrier was generated by conversion of an electromagnetic signal. Thus, the deep trench structure 20 may prevent the charge carrier to be detected erroneously or undesirably in another sensing region than the sensing region 14. Thus, the deep trench structure 20 may increase the yield of an electromagnetic signal entering into the sensing region 14 through a region of the main surface region 12 vertically above the sensing region 14 to be detected in the sensing region 14.

    [0018] By depositing the doped layer 32 on the surface region 22, such as walls, of the deep trench structure 30, tunable doping profiles for drift field generation can be created in the sensing region 14. Based on the out-diffusing 160 of dopants of the doped layer 32 into the thickened substrate 10', the resulting doping profile can be tuned to provide electric drift fields in the substrate 10' and/or in the sensing region 14, 14'. Thus, the method 100 allows a very precisely reproducible generation of doping profiles with a low complexity process sequence by using a selective epitaxial deposition, for example a high doped selective silicon epitaxy deposition on the trenches, for example on the sidewall of the trenches, and by controlling a doping profile with an annealing process, such as a temperature process.

    [0019] Thus, the proposed method 100 is an effective method on the way to small pixels, for example small pixels with high resolution which may be part of a sensor device.

    [0020] In the following, referring to Figs. 2a-g an exemplary embodiment of the process flow of the method 100 is described. Figs. 2a-g show schematic cross-sectional views of the substrate along a vertical plane. Figs. 2a-g show the (at the respective process stage) manufactured elements at several process stages of the method 100 for manufacturing the sensor device.

    [0021] Fig. 2a - Provided substrate: Fig. 2a shows an exemplary embodiment of the substrate 10 as provided in step 110 of method 100. The substrate 10 may have a rectangular cross-section along a vertical axis (i.e. in the depth direction or z direction). The substrate 10 may comprise silicon, germanium or any other semiconductor material. The substrate 10 may comprise a bulk or epitaxially (EPI) grown semiconductor material. The substrate 10 may comprise dopants with a doping concentration and a doping type being either n-type or p-type.

    [0022] The main surface region 12 may be a planar surface and may form a top surface of the substrate 10. The vertical dimension of the sensing region 14 may cover the complete vertical dimension of the substrate 10, or only part of it. The sensing region 14 has a lateral dimension, which may be smaller than the lateral dimension of the substrate 10.

    [0023] According to an embodiment, the sensing region 14 forms a conversion region of an optical sensor to be manufactured, wherein the conversion region converts an electromagnetic signal into photo-generated charge carriers. A sensing region 14 of such an optical sensor may form part of a device known as pixel, which may comprise further components, e.g. processing circuitry. This pixel itself may form part of a two-dimensional integrated pixel array for receiving electromagnetic radiation, for example optical visible or infrared radiation, wherein the respective pixels provide an electrical output signal according to a parameter to be measured by the optical sensor. The optical sensor may for example be an imaging array or a time of flight sensor.

    [0024] The revealed areas 18 of the masking layer 16 expose the main surface region 12 of the substrate 10. The lateral structure (i.e. the lateral dimension and the lateral form) of the revealed areas 18 of the masking layer 16 provide a lateral structure for a deep trench structure formed in following process steps. The revealed areas 18 of the masking layer 16 may have been formed by partially removing the masking layer 16. This partial removal of the masking layer 16 may have been performed by a lithographic process.

    [0025] Fig 2b - trench etching: In step 120 of the method 100, parts of the substrate 10 are removed by etching, starting from the revealed areas 18 of the masking layer 16 and etching into the substrate 10 to form the deep trench structure 20, as shown in Fig. 2b. During the etching process 120, the masking layer 16 may be partially removed. The trench etching process 120 is configured to remove material of the substrate 10 at a faster rate than material of the masking layer 16.

    [0026] After step 120, the substrate 10 comprises the deep trench structure 20. The lateral structure of the deep trench structure 20 emanates from the lateral structure of the revealed areas 18 of the masking layer 16.

    [0027] The deep trench structure may have a depth 27. The depth 27 of the deep trench structure 20 may be a vertical dimension of the deep trench structure 20.

    [0028] According to an embodiment, the depth 27 may be in the range between 1µm and 100 µm, or in another embodiment, in the range between 2 µm and 20 µm.

    [0029] The deep trench structure 20 comprises a surface region 22. The surface region 22 of the deep trench structure 20 may be a boundary between the deep trench structure 20 and the substrate 10. The surface region 22 of the deep trench structure 20 may comprise a wall 24, which may be a boundary that confines the deep trench structure 20 in a lateral direction. The surface region 22 of the deep trench structure 20 may also comprise a bottom 26, which may be a boundary that confines the deep trench structure 20 in the vertical direction.

    [0030] The deep trench structure 20 has a width 25. This width 25 may be a lateral distance between two immediately opposing walls 24, or a lateral distance between two opposite regions of the surface region 22, the lateral distance being measured perpendicular to a longitudinal direction of a trench or a trench portion of the deep trench structure 25.

    [0031] According to an embodiment, the width 25 is large enough that an evanescent wave of a total internal reflection of an electromagnetic signal at the interface between the substrate 10 and the deep trench structure 20 may be hindered to interact with neighboring regions of the substrate 10. Thus, the reflection may be a frustrated total internal reflection.

    [0032] According to an embodiment, the width 25 is larger than a few wavelengths of the electromagnetic signal to be detected, such that the reflection of an electromagnetic signal at the interface between the substrate 10 and the deep trench structure 20 may be a frustrated total internal reflection.

    [0033] A trench aspect ratio of the deep trench structure 20 may be defined as a ratio of the trench height 27 and the width 25. According to an embodiment, the trench aspect ratio of the deep trench structure 20 is in a range between 1 and 100 or between 5 and 60.

    [0034] The trench etching process 120 may have different etching rates for different etching directions regarding substrate 10. For example, the trench etching process 120 may primarily etch a vertical surface of the substrate 10. Thus, deep trench structures 20 with a high trench aspect ratio may be etched by the trench etching process 120.

    [0035] The deep trench structure 20 is arranged laterally relative to the sensing region 14 of the substrate 10. The deep trench structure 20 does not necessarily adjoin the sensing region 14, but may also be spaced apart from the sensing region 14 by a region of the substrate 10 which is not part of the sensing region 14.

    [0036] The deep trench structure 20 may surround, e.g. enclose entirely or only partly the sensing region 14. Optionally, thus, the deep trench structure 20 may enclose the sensing region 14 entirely.

    [0037] According to an embodiment, the deep trench structure 20 may comprise deep trench portions (not shown in Figs. 2a-g, see in Fig. 3a for example) which may be arranged to laterally confine the sensing region 14. In such a case, the above described properties of the deep trench structure 20 apply equally to the individual deep trench portions and the arrangement of the plurality of deep trench portions forms the deep trench structure 50.

    [0038] Fig 2c - doped EPI deposition: In step 130 of the method 100, a doped layer 32 is deposited on the surface region 22 of the deep trench structure 20 by a selective epitaxy (EPI) deposition, as shown in Fig. 2c. The doped layer 32 and the deep trench structure 20 form a coated deep trench structure 30.

    [0039] The selective epitaxial deposition is configured to selectively deposit a doped semiconductor material primarily on the surface region 22 of the deep trench structure 20.

    [0040] The deposition of the doped layer 32 on the surface of the deep trench structure 20 is an efficient way to introduce a doping concentration or a doping profile in the substrate. Very reproducible results can be obtained with the control of the thickness and the doping concentration of the doped layer 32.

    [0041] The selective epitaxial deposition may comprise exposing the substrate 10 to one or more of the following gases: dichlorosilane, HCI, B2H2, and H2. The selective epitaxial deposition may be performed at a temperature between 600°C and 1000°C, for example at a temperature around 760°C. The selective epitaxial deposition may be configured to achieve a specific doping concentration of the doped layer 32.

    [0042] During the selective epitaxial deposition of the doped layer 32, the main surface region 12 of the substrate 10 is still covered by the masking layer 16 to prevent the doped layer 32 from forming thereon.

    [0043] The doped layer 32 may cover the entire surface region 22 of the deep trench structure 20. The doped layer 32 may comprise a thickness 34. The thickness 34 of the doped layer 32 may be a distance between a surface region 36 of the doped layer 32 and a surface region 22 of the deep trench structure 20. The surface region 36 of the doped layer 32 may be a boundary between the coated deep trench structure 30 and the doped layer 32. The thickness 34 of the doped layer 32 may be in a range between 1 nm and 1 µm.

    [0044] The doped layer 32 may comprise a semiconducting material, for example silicon. A doping type of the doped layer 32 may be n-type or p-type. A doping concentration of the doped layer 32 may be in a range between 1016 cm-3 and 1020 cm-3.

    [0045] According to an embodiment, the doping inside the trenches, that is the deposition of the doped layer 32, is done with a selective high doped silicon epitaxial deposition with the masking layer 16, which may be a capping layer, on the main surface region 12.

    [0046] According to an embodiment, the material deposited by the selective epitaxial deposition is primarily in the deep trench structure 20 and not on the main surface region 12 of the substrate 10.

    [0047] According to an embodiment, the doped layer 32 is deposited on the trench wall by a selective epitaxial deposition and the doped layer 32 is a thin layer and has a high doping concentration. Thus, the width 25 remains almost unaltered after deposition of the doped layer 32, so that the deep trench structure 20 keeps its beneficial properties regarding crosstalk prevention, and at the same time, an efficient drift field generation is granted.

    [0048] Fig. 2d - pad etching: In step 140 of the method 100, the masking layer 16 is at least partially removed for revealing the main surface region 12 of the substrate 10. The removing 140 of the masking layer 16 may comprise an etching process, wherein the etching process is adapted to etch primarily the masking layer 16 and to etch less efficiently or not at all the substrate 10. The removing 140 of the masking layer 16 may be applied to the entire masking layer 16 or only to parts of the masking layer 16, referring to a lateral dimension of the masking layer 16. The removing 140 of the masking layer 16 removes at least parts of the masking layer 16 in its entire vertical dimension, so that the underlying main surface region 12 of the substrate 10 is exposed. Thus, the removing 140 of the masking layer 16 at least partially exposes the main surface region 12 of the substrate 10.

    [0049] According to an embodiment, the removing 140 of the masking layer 16 exposes those parts of the main surface region 12 of the substrate 10, which are arranged adjacent to the coated deep trench structure 30.

    [0050] According to a further embodiment, the removing 140 of the masking layer 16 exposes the entire main surface region 12 of the substrate 10.

    [0051] After step 140, the main surface region 12 of the substrate 10 is at least partially exposed as shown in Fig. 2d.

    [0052] After step 140 and before step 150, the method 100 may optionally comprise filling the coated deep trench structure 30 with a gas or with a dielectric material. The optional gas or dielectric material filling the coated deep trench structure 30 may be a material which is opaque for an optical radiation, in particular for an optical radiation to be detected in the sensing region 14. In other words, the gas or the dielectric material filling the coated deep trench structure 30 may be adapted to absorb or attenuate optical radiation, i.e. electromagnetic radiation, or may be chosen so that the optical radiation is refracted at least partially to not pass through the material. Alternatively, the optional gas or dielectric material filling the coated deep trench structure 30 may have a dielectric function adapted to achieve a total internal reflection or a frustrated total internal reflection of an electromagnetic signal at an interface between the coated deep trench structure 30 and the substrate 10.

    [0053] Fig. 2e: capping layer deposition: In step 150 of method 100, the capping layer 52 is deposited on the main surface region 12, as shown in Fig. 2e. The capping layer 52 is also deposited adjacent to the coated deep trench structure 30, more specifically in a region located vertically above the coated deep trench structure 30. Thus, the capping layer 52 covers and closes the coated deep trench structure 30, which is thus buried in the substrate 10 during step 150. The deposition 150 of the capping layer 52 may comprise an epitaxial (EPI) process, such as an epitaxial (EPI) overgrow. In one embodiment, the deposition of the semiconducting capping layer 52 comprises an epitaxial (EPI) overgrow process at atmospheric pressure.

    [0054] The capping layer 52 may comprise silicon, germanium or any other semiconducting material. In one embodiment, the capping layer 52 has the same material as the substrate 10. The capping layer 52 may comprise a doping concentration and a doping type, which may be n-type or p-type. The doping type of the capping layer 52 may have the same or a different doping type as the substrate 10.

    [0055] The capping layer 52 and the substrate 10 form a thickened substrate 10' comprising a surface region 12', which may form a top surface of the thickened substrate 10'.

    [0056] The capping layer 52 has a thickness 54, which may be a vertical distance between the surface region 12' of the thickened substrate 10' and the main surface region 12 of the substrate 10. In other words, the thickness 54 may be a depth of the capping layer 52. Thus, the thickness 54 may also be a depth of the buried deep trench structure 50 below the main surface region 12' of the thickened substrate 10'. The capping layer 52 may cover the main surface region 12 of the substrate 10 partially or completely. The capping layer 52 may comprise a region, which extends vertically above the sensing region 14 into the capping layer 52, and which may extend the sensing region 14 to form together with it a sensing region 14'. The sensing region 14' extends vertically below the main surface region 12' into the thickened substrate 10'.

    [0057] The depth of bury 54, that is the thickness of the capping layer 52, may have a chosen value. A thin value of the depth of bury 54 may improve the crosstalk suppression of the buried deep trench structure 50. A thick value of the depth of bury 54 may provide more space for processing electronic circuitry vertically above the buried deep trench structure 50.

    [0058] According to an embodiment, the thickness 54 of the capping layer 52 may be in a range between 100 nm and 10µm.

    [0059] According to an embodiment, the buried deep trench structure 50 may be empty or filled with gas or it may be partially filled with a dielectric material or with any other material. In this context, empty may refer to a filling with any gas, for example air or a process gas, or empty may refer to a gaseous environment at a pressure lower than ambient pressure. Alternatively, the buried deep trench structure 50 may be filled or partially filled with a solid material, for example a dielectric material.

    [0060] According to an embodiment, the buried deep trench structure 50 is filled with a process gas of the epitaxial overgrow process.

    [0061] According to an embodiment, the deposition of the capping layer 52 may comprise depositing semiconducting material on the surface region 36 of the doped layer 32, so that the capping layer 52 may at least partially cover the doped layer 32.

    [0062] The buried deep trench structure 50 emanates from the coated deep trench structure 30 which itself results from the deep trench structure 20. Thus, properties and functions of the deep trench structure 20 discussed above equally apply to the buried deep trench structure 50. Properties and functions discussed in the context of the interface between the deep trench structure 20 or the coated deep trench structure 30 and the substrate 10 equally apply regarding the interface between the buried deep trench structure 50 and the substrate 10.

    [0063] According to an embodiment, and resulting from what is indicated above, the buried deep trench structure 50 may comprise multiple deep trench portions (not shown in Fig. 2, shown in Figs. 3b-d, Figs. 4a-f, Fig. 5) to which, the above described properties of the buried deep trench structure 50 apply equally.

    [0064] Fig. 2f - dopant out-diffusion: In step 160 of method 100, dopants of the doped layer 32 are out-diffused into the thickened substrate 10'. The step of out-diffusing may comprise an annealing process, which may be a temperature process, which may comprise exposing the device with the substrate 10 to a high temperature. The out-diffusing of dopants comprises a drift or a movement of dopants from the doped layer 32 into the thickened substrate 10'. The region, within which the dopants are distributed forms a trench doping region 60, as shown in Fig. 2f. The out-diffusion 160 of dopants establishes a doping profile 74 that extends from the doped layer 32 into the thickened substrate 10'.

    [0065] The doping profile 74 describes the local distribution of dopants in the trench doping region 60. The trench doping region 60 may be laterally adjacent to the sensing region 14', but the trench doping region may also overlap with the sensing region 14'. The trench doping region 60 may also laterally confine the sensing region 14'.

    [0066] The out-diffusing 160 may be adapted to control the drift or the movement of dopants, such that after the step 160, the trench doping region 60 comprises a specific dimension and/or form with a specific doping profile 74. The doping profile 74 may be changed to reach an optimum adjustment of the electric fields. A maximum doping concentration may be in a range between 1014 and 1018 cm-3, or between 1015 and 1017 cm-3.

    [0067] According to an embodiment, the doping profile 74 is configured to efficiently separate charge carriers of opposite charge, such as electrons and holes, which were generated by converting an electromagnetic signal into charge carriers.

    [0068] According to an embodiment, the doping profile 74 is configured to optimize the path of charge carriers towards an electronic contact configured for collecting the charge carrier, so that a readout-speed can be enhanced.

    [0069] According to an embodiment, the doping profile 74 is configured to efficiently accelerate charge carriers away from the interface between the buried deep trench structure 50 and the substrate 10', so that a leakage is reduced. The leakage may for example be a recombination of charge carriers at interface between the buried deep trench structure 50 and the substrate 10'.

    [0070] Fig. 2g - optional electronic circuitry: As shown in Fig. 2g, in an optional step 170, an electronic circuitry 70, such as a readout circuitry, for the sensing region 14' may be created at least partially vertically above the buried deep trench structure 50. The circuitry may at least in part be located within a capping region 72 of the thickened substrate 10', or alternatively, may be located on the top surface of the thickened substrate 10'. The creation of the circuitry 70 may comprise a sequence of process steps, including, for example, one or several of depositing a material, removing a material, doping a material or treating a material chemically or mechanically. During creation of the electronic circuitry 70, the thickened substrate 10' may be changed or affected by a process step.

    [0071] The capping region 72 extends vertically above the buried deep trench structure 50 into the thickened substrate 10' and to the main surface region 12' and it may exceed the main surface region 12' to extend vertically above the main surface region 12'.Creating the electronic circuitry 70 affects the capping region 72, in particular a part of the main surface region 12' within the capping region 72. The electronic circuitry 70 may extend vertically above and/or below the main surface region 12' of the thickened substrate 10'. The electronic circuitry 70 may extend into the capping region 72 and/or into the sensing region 14'. The electronic circuitry may also extend into the trench doping region 60.

    [0072] According to an embodiment, the electronic circuitry is arranged partially within the thickened substrate 10'. Such an arrangement facilitates the fabrication of common semiconductor circuitry, for example doping regions for read-out contacts.

    [0073] According to an embodiment, the electronic circuitry 70 may comprise contact regions within the thickened substrate 10'. The contact region may for example comprise a higher doping concentration of the same doping type as the sensing regions 14'so that charge carriers from the sensing regions 14'-1, 14'-2 may be collected in the contact regions.

    [0074] According to an embodiment, the electronic circuitry 70 is a readout circuitry to collect electronic charges from the sensing region 14'.

    [0075] According to an embodiment, the sensing region 14' and the electronic circuitry 70 form parts of a pixel device which is part of a sensor device comprising multiple pixel devices. The multiple pixel devices may be separated from each other by the buried deep trench structure 50. More specifically, an individual pixel device of the multiple pixel devices may be separated from its neighboring pixel devices by one ore multiple deep trench portions of the buried deep trench structure 50.

    [0076] According to an embodiment, electronic circuit paths are placed in regions located vertically above the buried deep trench structure.

    [0077] In the following, a number of different possible implementations of the method 100 are exemplarily described.

    [0078] In the present description of embodiments of the method 100, the same or similar elements having the same structure and/or function are provided with the same reference numbers or the same name, wherein a detailed description of such elements will not be repeated for every embodiment. Thus, the above description with respect to Figs. 1a and 2a-g is equally applicable to the further embodiments as described below. In the following description, essentially the differences, e.g. additional elements, to the embodiment as shown in Fig. 1a and Figs. 2a-g and the technical effect(s) resulting therefrom are discussed in detail.

    [0079] Figs. 3a-d show schematic top views (schematic snapshots) of substrates 10, 10' and manufactured elements of sensor devices at two different stages of the method 100 according to embodiments.

    [0080] Fig. 3a refers to the step 120 of etching the deep trench structure 20 into the substrate 10, as also described in the description of Fig. 2b.

    [0081] According to an embodiment, the deep trench structure 20 may comprise a plurality of deep trench portions 20-1, 20-2, ..., 20-n, e.g. four deep trench portions 20-1, 20-2, ..., 20-4 as shown in Fig. 3a. Each of the deep trench portions 20-1, 20-2, ..., 20-n may comprise an individual width and depth. For example, the deep trench portions 20-1, 20-2, ... 20-4 may have a common width 25, which is referred to as the width 25 of the deep trench structure 20. According to the embodiment, the individual deep trench portions 20-1, 20-2, ..., 20-4 may have a common depth, which is referred to as the depth 27 of the deep trench structure (cf. Fig. 2b). A deep trench portion 20-1, 20-2, ..., 20-n may have a length 21-1, 21-2, ..., 21-n, which is a longitudinal dimension of the deep trench portion 20-1, 20-2, ..., 20-n perpendicular to the width 25 of the respective deep trench portion 20-1, 20-2, ..., 20-n. Each deep trench portion 20-1, 20-2, ... 20-n may comprise an individual length 21-1, 21-2, ...,21-n. For example, as shown in Fig. 3a, the deep trench portions 20-1, 20-2 may comprise the lengths 21-1, 21-2. The deep trench portions 20-1, 20-2, ... 20-n may be arranged to partially or completely laterally surround the sensing region 14, as indicated above. For example, as shown in Fig. 3a, the four deep trench portions 20-1, 20-2, ... 20-4 may partially surround the sensing region 14. According to the embodiment, two neighboring deep trench portions of the deep trench portions 20-1, 20-2, ... 20-4 are arranged at an angle of 90°, the four deep trench portions 20-1, 20-2, ... 20-4 being arranged in a rectangle configuration.

    [0082] According to an embodiment, the deep trench portions 20-1, 20-2, ... 20-n may be arranged in an equiangular polygon configuration, so that two of the n deep trench portions 20-1, 20-2, ... 20-n may be arranged at an angle of 360°/n.

    [0083] According to an embodiment, the deep trench portions 20-1, 20-2, ... 20-n may be arranged in arbitrary sequence at arbitrary angles to partially or completely laterally surround the sensing region 14.

    [0084] The sensing region 14 may have an arbitrary lateral form. The lateral dimension of the sensing region 14 may be defined by one ore multiple lateral sensing region dimensions. For example, according to the embodiment shown in Fig. 3b, the lateral form of the sensing region 14 is rectangular and is defined by two lateral sensing region dimensions 15-1, 15-2.

    [0085] Figs. 3b-d refer to step 150 of depositing the capping layer 52 for forming the thickened substrate 10' having the buried deep trench structure 50, as also described in the description of Fig. 2e.

    [0086] According to an embodiment, the buried deep trench structure 50 may comprise a plurality of deep trench portions 50-1, 50-2, ..., 50-n, which emanate from the deep trench portions 20-1, 20-2, ..., 20-n etched in step 120.

    [0087] For example, according to the embodiments shown in Figs. 3b-c, the buried deep trench structure 50 comprises four deep trench portions 50-1, 50-2, ...,50-4, which emanate from the deep trench portions 20-1, 20-2, ..., 20-4 etched in step 120 (cf. Fig. 3a). The deep trench portions 50-1, 50-2, ...,50-4 may be arranged to partially or completely laterally surround the sensing region 14' which may be defined by two lateral sensing region dimensions 15-1, 15-2.

    [0088] Fig. 3d shows a further embodiment of an arrangement of eight deep trench portions 50-1, 50-2, ...,50-8 which are arranged in an octagonal arrangement to partially surround a sensing region 14', wherein the sensing region 14' may have an octagonal form which may be defined by a lateral sensing region dimension 15-1.

    [0089] As shown in Figs. 3a-d, the sensing region 14, 14' does not necessarily extend over the entire lateral region between individual deep trench portions 20-1, 20-2, ..., 20-n, 50-1, 50-2, ...,50-n. Thus, the sensing region 14, 14' does not necessarily adjoin the deep trench structure 20 or the buried deep trench structure 50.

    [0090] According to an embodiment, the sensing region 14' may have an arbitrary form.

    [0091] According to embodiments, for example embodiments shown in Figs. 3b-d, an electronic circuitry 70, such as a readout circuitry, may be created for a sensing region 14' at least partially vertically above the buried deep trench structure 50, as described in the description of Fig. 2g.

    [0092] Figs. 4a-f show schematic top views of substrates 10' and manufactured elements of sensors device according to different embodiments.

    [0093] According to the embodiments, the thickened substrate 10' comprises a plurality of sensing regions 14'-1, 14'-2, ..., 14'-n and the buried deep trench structure 50 comprises a plurality of deep trench portions 50-1, 50-2, ..., 50-n. The deep trench portions 50-1, 50-2, ... 50-n may be arranged to partially (Figs. 4a-c, 4e) or completely (Figs. 4d, 4f) laterally surround multiple sensing regions 14'-1, 14'-2, ..., 14'-n individually, i.e. each of multiple parts of the plurality of deep trench portions 50-1, 50-2, ..., 50-n may be arranged to at least partially surround one of the single sensing regions 14'-1, 14'-2, ..., 14'-n, respectively. For example, in the exemplary arrangements shown in Figs. 4a-c, the deep trench portions 50-1, 50-2, ..., 50-4 partially enclose the sensing region 14'-4.

    [0094] According to an embodiment, for example the embodiment shown in Fig. 4d, the deep trench portions 50-1, 50-2, ..., 50-8 are arranged to completely laterally surround multiple sensing regions 14'-1, 14'-2 individually.

    [0095] According to an embodiment, for example the embodiment shown in Fig. 4f, the deep trench portions 50-1, 50-2, ... 50-8 are arranged to completely laterally surround the sensing region 14'-2 individually.

    [0096] According to an embodiment, a plurality of deep trench portions 50-1, 50-2, ... 50-n may be arranged to separate individual sensing regions 14'-1, 14'-2, ... 14'-n from each other.

    [0097] According to an embodiment, a plurality of sensing regions 14'-1, 14'-2, ... 14'-n may be arranged in an array.

    [0098] According to an embodiment, each of a plurality of sensing regions 14'-1, 14'-2, ... 14'-n forms a part of an individual pixel device, the individual pixel devices being part of an imaging array or a sensor array.

    [0099] Fig. 5 shows a schematic cross sectional view of an exemplary embodiment of a thickened substrate 10' and elements of a sensor device manufactured by the method 100 according to an embodiment. The thickened substrate 10' comprises sensing regions 14'-1, 14'-2 to convert an electromagnetic signal S1 into charge carriers, i.e. into electrons and holes. The thickened substrate 10' comprises the buried deep trench structure 50 comprising deep trench portions 50-1, 50-2, 50-3 which are arranged to separate the neighboring sensing regions 14'-1, 14'-2. The deep trench portions 50-1, 50-2, 50-3 are surrounded by the trench doping region 60. The trench doping region 60 comprises a doping profile which may be optimized to accelerate charge carriers away from the interface between the buried deep trench portions 50-1, 50-2, 50-3, efficiently reducing leakage or noise of the manufactured sensor device during operation.

    [0100] The electronic circuitry 70 is partially arranged vertically above the deep trench portions 50-1, 50-2, 50-3 so that the buried deep trench structure 50 does not consume surface area.

    [0101] According to an embodiment, additional readout circuitry 502 is arranged on a main surface region 12' of the thickened substrate 10' vertically above the sensing regions 14'. The additional readout circuitry 502 may be adapted to perform time of flight measurements.

    [0102] According to an embodiment, the thickened substrate 10' comprises a buried doping region 501 which extends vertically below the sensing regions 14'-1, 14'-2 into the substrate 10'. In an embodiment, the buried doping region 501 extends vertically below the sensing regions 14'-1, 14'-2 to an opposite surface region 503 of the thickened substrate 10' opposite to the main surface region 12'.

    [0103] According to an embodiment, the buried doping region 501 comprises an opposite doping type compared to the sensing region 14, i.e. the buried doping region 501 may comprise a p-type doping and the sensing region 14 may comprise a n-type doping or vice versa. Such an embodiment may be beneficial for efficiently separating electrons and holes.

    [0104] According to an embodiment, the trench doping region 60 comprises the same doping type as the buried doping region 501 of the substrate 10, so that a specific kind of charge carriers is efficiently accelerated towards the main surface region 12' or an electronic circuitry 70.

    [0105] According to an embodiment, the trench doping region 60 comprises a higher doping concentration than the buried doping region 501.

    [0106] According to an embodiment, the trench doping region 60 and the buried doping region 501 are p-doped and the sensing region is n-doped, the embodiment being beneficial for an efficient drift of electrons towards the main surface area 12 of the substrate and in particular for an efficient drift of electrons towards the electronic circuitry 70 and/or the additional readout circuitry 502.

    [0107] In an embodiment, the etching 120 of the deep trench structure 20 may comprise arranging the deep trench structure 20 vertically from the main surface region 12 into the substrate 10 and into a buried doping region 501 of the substrate 10.

    [0108] According to an embodiment, the doped layer 32 (see for example Figs. 2c-g) may comprise the same doping type as the buried doping region 501 of the substrate 10.

    [0109] According to an embodiment, the doped layer 32 (see for example Figs. 2c-g) further comprises a higher doping concentration than the buried doping region 501.

    [0110] According to an embodiment, the doped layer 32 (see for example Figs. 2c-g) and the buried doping region 501 are p-doped and the sensing region is n-doped.

    [0111] Fig. 6 shows schematic cross-sectional views (schematic snapshots) of a substrate 10 and manufactured elements of a sensor device at different stages of the method 100 according to a further embodiment. Fig. 6 refers to the optional steps 105 and 106 and the steps 110 and 120 of an embodiment of the method 100. Equal elements shown in different panels of the figure should be referred to with the same references if not indicated otherwise.

    [0112] The optional step 105 may be part of the step 110. In step 105, the substrate 10 is provided with the sensing region 14, and with the masking layer 16 arranged on the main surface region 12. In the shown embodiment, the masking layer 16 comprises a pad layer 16-1 arranged adjacent to or on top of the main surface region 12. According to an embodiment, the pad layer 16-1 may be a silicon nitride layer. In the shown embodiment, the masking layer 16 further comprises a hard mask layer 16-2 arranged adjacent to or on top of the pad layer 16-1. The hard mask layer 16-2 may comprise a composition of materials, which is less sensitive to a specific etch process than a composition of material of the substrate 10. Thus, an etch process may be configured to remove material of the substrate 10 at a faster rate than material from the hard mask layer 16-2. In the shown embodiment, a resist layer 601 is arranged on top of the hard mask layer 16-2. The resist layer 601 comprises a revealed resist region 602 which exposes a top surface region 603 of the hard mask layer 16-2, as shown in the left panel of Fig. 6. For the providing 110 of the substrate 10, in this embodiment, the method 100 comprises an additional step 106 of etching revealed areas 18 into the masking layer 16 through the revealed resist region 602 of the resist layer 601. Thus, the lateral structure of the revealed areas 18 of the masking layer 16 emanate from the revealed region 602 of the resist layer 601. The step 106 of etching the masking layer 16 may be followed by or may comprise removing the resist layer 601, so as to provide the substrate 10 with the masking layer 16 comprising the revealed areas 18, as shown in the center panel of Fig. 6. The right panel of Fig. 6 shows the result of the etching 120 of the deep trench structure 20..

    [0113] According to an embodiment, the optional pad layer 16-1 has a thickness, which is a vertical dimension, in the range between 1 nm and 10 µm or in another embodiment in the range between 10 nm and 1 µm.

    [0114] According to an embodiment, the masking layer 16 comprises a pad layer 16-1 and a hard mask layer 16-2, wherein the hard mask layer 16-2 is configured to be less sensitive to a trench etch process than the substrate 10, so that the trench etch process primarily affects regions of the substrate 10 which are not covered with the masking layer 16.

    [0115] Although, the embodiment shown in Fig. 6 comprises the buried doping region 501, as introduced in Fig. 5, this feature is independent from the features introduced in Fig. 6.

    [0116] Figs. 7a-e show cross-sectional electron microscopy images and typical dimensions of a substrate 10, 10' at different stages of the method 100 according to an embodiment.

    [0117] Fig. 7a shows a show cross-sectional view of a substrate 10 with the masking layer 16 after the etching 120. The deep trench structure 20 comprises a depth 27 which is a vertical dimension from the main surface region 12 into the substrate 10. The depth 27 may be in the range as described in the context of Fig. 2b. For example, the depth 27 may be around 15 µm.

    [0118] Fig. 7b shows an enlarged view of the rectangle in Fig. 7a. According to the shown embodiment, the masking layer 16 comprises a pad layer 16-1 and a hard mask layer 16-2, the pad layer 16-1 having a thickness 701. The thickness 701 of the pad layer 16-1 may be in a range as described in the context of Fig. 2a. For example, the pad layer thickness 701 may be around 130 nm. The deep trench structure 20 may have a width 25 which may be in the range as described in the context of Fig. 2b. For example, the width may be around 370 nm.

    [0119] Fig. 7c shows a cross-sectional view of a thickened substrate 10' having the buried deep trench structure 50 after step 150. The buried deep trench structure 50 comprises the deep trench portions 50-1, 50-2, 50-3.

    [0120] Fig. 7d shows an enlarged view of the rectangle 710 in Fig. 7c, showing the deep trench portion 50-3 comprising a depth 27. The depth 27 may be in the range as described in the context of Fig. 2b. For example, the depth 27 may be around 13 µm.

    [0121] Fig. 7e shows an enlarged view of the center rectangle 720 in Fig. 7c, showing the depth of bury 54 of the buried deep trench structure 50 below the main surface region 12' o. The depth of bury 54 may be in the range as described in the context of Fig. 2e. For example, the depth of bury 54 may be around 2 µm.

    [0122] Fig. 8 shows an example of a lateral distribution of dopants in the trench doping region 60 of a sensor device manufactured according to an embodiment of the method 100. The plot shows a concentration of dopants along a lateral direction from a doped layer 32 into the thickened substrate 10'. Other distributions can however be obtained as desired.

    [0123] Fig. 9 shows schematic cross-sectional views (schematic snapshots) of a substrate and elements of the sensor device at different stages of the manufacturing according to a further embodiment, which comprises an additional step 132 of depositing 132 a trench coating layer 90 on a surface region 36 of the doped layer 32, wherein the selective depositing 130 of the doped layer 32 and the depositing 132 of the trench coating layer 90 together provide the coated deep trench structure 30.

    [0124] Fig. 9 shows the stages of the manufacturing process after the steps 130, 132, 140 and 150. After step 130, the substrate 10, which may optionally comprise the buried doping region 501, still has the masking layer 16 and the deep trench structure is coated with the doped layer 32 having the thickness 34 and the surface region 36.

    [0125] The additional depositing step 132 follows the step 130 of depositing the doped layer 32. The depositing 132 of the trench coating layer 90 may for example be an epitaxy process. For example, the depositing 132 may be a selective epitaxy process which is configured to deposit a semiconducting material primarily on the doped layer 32, such that the masking layer 16 may remain free of this material. The trench coating layer 90 may comprise an undoped semiconductor material, such as undoped silicon, but the trench coating layer 90 may also comprise a low-doped semiconductor material with a doping concentration less than the doping concentration of the doped layer 32. For example, the doping concentration of the trench coating layer 90 may be smaller than the doping concentration of the substrate 10. For example, the doping concentration of the trench coating layer 90 may be lower than 1015 cm-3. The trench coating layer 90 may have a thickness 38, which may be lower than 1 µm. Alternatively, the trench coating layer 90 may comprise an insulating material, for example silicon nitride, for example in combination with the thickness 38 of the trench coating layer 90 being below 100 nm.

    [0126] The trench coating layer 90 may cover the surface region 36 of the doped layer 32. At least, the trench coating layer 90 covers a top surface region 37 of the doped layer 32. For example, the top surface region 37 of the doped layer 32 may be a surface region of the doped layer 32 which extends vertically above the main surface region 12 of the substrate and which is adjacent to the masking layer 16.

    [0127] The selective depositing 130 of the doped layer 32 and the depositing 132 of the trench coating layer 90 together provide the coated deep trench structure 30 which may comprise the dimensions and the functionality as described above. After the deposition 132 of the trench coating layer 90, the method 100 may be pursued with the removal 140 of the masking layer 16 and the deposition 150 of the semiconductor capping layer as described with respect to Figs 1-8.

    [0128] By covering at least the top surface region 37 of the doped layer 32, the extent of the contact region between the doped layer 32 and the capping layer 52 may be reduced. In other words, the trench coating layer 90 is then configured to reduce the surface of the doped layer 32 which will be in contact with the capping layer 52 once it is formed. As a consequence, the amount of dopants that may diffuse from the doped layer 32 into the capping layer 52 during the depositing 150 of the capping layer 52 or during the subsequent step of out-diffusing 160 of dopants may be reduced. Reducing this diffusion may prevent the diffused dopants from interfering with elements in or on the capping layer 52, such as circuitry 70, during an operation of the sensor device.

    [0129] Fig. 10 shows schematic cross-sectional views (schematic snapshots) of the substrate 10 and elements of the sensor device after the steps 130, 140 and 150 of the manufacturing according to a further embodiment of the method 100. Steps 130 and 140 correspond to the steps 130 and 140 as described with respect to Figs. 1-9. Optionally, the method may also comprise the deposition 132 as described above. According to the embodiment shown in Fig. 10, the step 150 of depositing the capping layer 52 comprises a step of depositing a first semiconductor capping layer 55 on the main surface region 12. Further, the depositing 150 comprises a step of depositing a second semiconductor capping layer 57 on the first semiconductor capping layer 55, the first semiconductor capping layer 55 and the second semiconductor capping layer 57 forming together the capping layer 52. During this step, the depositing 155 of the first semiconductor capping layer 55 is performed at a lower temperature than the depositing 157 of the second semiconductor capping layer 57.

    [0130] The deposition of the first semiconductor capping layer 55 may be a deposition process like the deposition 150 of the capping layer 52 described with respect to Figs. 1-9, but the deposition of the first semiconductor capping layer 55 may be performed at a lower temperature or process temperature as the deposition process described with respect to the deposition 150 in the description of the Figs. 1-9. The deposition of the first semiconductor capping layer 55 closes the coated deep trench structure 30 as described with respect to the deposition 150 of the capping layer 52 in the description of the Figs. 1-9.

    [0131] The deposition of the second semiconductor capping layer 57 may for example be a growing of the second semiconductor capping layer 57 on top of the first semiconductor capping layer 55. The deposition of the second semiconductor capping layer 57 may be a deposition process like the deposition 150 described with respect to the Figs. 1-9 and the deposition of the second semiconductor capping layer 57 may be performed at a temperature as described with respect to the deposition 150.

    [0132] The temperature of the deposition of the first semiconductor capping layer 55 is for instance lower by more than 50°C than the temperature of deposition of the deposition of the second semiconductor capping layer 57. For instance, the temperature difference may be more than 100 °C, or more than 200 °C.

    [0133] Depositing the first semiconductor capping layer 55 at a lower temperature may help to reduce diffusion of dopants of the doped layer 32 into the capping layer 52.

    [0134] Fig. 11 shows schematic cross-sectional views (schematic snapshots) of a substrate and elements of the sensor device at different stages of the manufacturing process according to an embodiment. Between the steps 120 and 130, the embodiment comprises an additional step 122 of widening the deep trench structure 20, the steps of etching 120 and widening 122 together providing the deep trench structure 20.

    [0135] The widening 122 of the deep trench structure 20 corresponds to a removal of matter of the substrate 10 from the surface 22 of the deep trench structure 20 over all or part of the height of the deep trench structure 20.

    [0136] The widening 122 may be carried out using an isotropic etching process, for example a dry etch process. Alternatively, it may be carried out using an anisotropic etch process, such as a wet etch process.

    [0137] The widening 122 may laterally remove material of the substrate 10 from a surface region of the deep trench structure 20 located adjacent or vertically below the masking layer 16 for providing an undercut 29 of the deep trench structure 20 with respect to the masking layer 16. In other words, in a region vertically below the masking layer 16, the deep trench structure 20 may have a larger lateral dimension than the revealed areas 18 (c.f. Figs. 2a- b) of the masking layer 16, the excess of the lateral dimension of the deep trench structure regarding the revealed areas 18 of the masking layer 16 defining the undercut 29. The undercut 29 may also be regarded as an overhang of the masking layer 16 over the deep trench structure 20.

    [0138] The dimension of the undercut 29 may be at least as large as the thickness 34 of the doped layer 32 which is deposited in the subsequent step 130. The undercut 29 of the deep trench structure 20 leads to a configuration in which the masking layer 16 caps the top surface region 37, as introduced with respect to Fig. 9, of the doped layer 32 after the doped layer 32 has been deposited in the subsequent step 130. However, in this embodiment, the top surface region 37 does not extend beyond the main surface region 12. In other words, the top surface region 37 of the doped layer 32 may be arranged vertically below the masking layer 16.

    [0139] This configuration helps prevent lateral contacts between the doped layer 32 and the capping layer 52, reducing diffusion of dopants from the doped layer 32 into the capping layer 52, e.g. during the deposition 150 of the capping layer 52.

    [0140] As indicated above, the steps of etching 120 and widening 122 together provide the deep trench structure 20. Following step 122, the subsequent process steps may be performed in accordance to the embodiments of Figure 1 to 9.

    [0141] The embodiments of Figure 9 to Figure 11 may be combined, whether two of them according to all possible combinations, or all three of them.

    [0142] Fig. 12 shows a schematic cross-sectional view of a sensor device with a buried deep trench structure according to an embodiment. The sensor device comprises the substrate 10' having the sensing region 14', the capping layer 52, the buried deep trench structure 50 comprising the doped layer 32, the trench doping region 60, and the electronic circuitry 70 for the sensing region 14' in the capping region 72 vertically above the buried deep trench structure 50.

    [0143] The sensor device provides the functionalities and advantages as described with respect to the method 100 for manufacturing a sensor device.

    [0144] In the foregoing Detailed Description, it can be seen that various features are grouped together in examples for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter may lie in less than all features of a single disclosed example. Thus the following claims are hereby incorporated into the Detailed Description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that, although a dependent claim may refer in the claims to a specific combination with one or more other claims, other examples may also include a combination of the dependent claim with the subject matter of each other dependent claim or a combination of each feature with other dependent or independent claims. Such combinations are proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.

    [0145] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present embodiments. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the embodiments be limited only by the claims and the equivalents thereof.


    Claims

    1. Method (100) for manufacturing a sensor device with a buried deep trench structure (50), comprising:

    providing (110) a semiconductor substrate (10) having a sensing region (14), which extends vertically below a main surface region (12) of the semiconductor substrate (10) into the semiconductor substrate (10), wherein a masking layer (16) is arranged on the main surface region (12) of the semiconductor substrate (10),

    etching (120) a deep trench structure (20) into the semiconductor substrate (10) through revealed areas (18) of the masking layer (16) for arranging the deep trench structure (20) laterally relative to the sensing region (14) and vertically from the main surface region (12) into the semiconductor substrate (10),

    selectively depositing by epitaxy (130) a doped semiconductor layer (32) on a surface region (22) of the deep trench structure (20) for providing a coated deep trench structure (30),

    at least partially removing (140) the masking layer (16) for revealing the main surface region (12) of the semiconductor substrate (10),

    depositing (150) a semiconductor capping layer (52) on the main surface region (12) of the semiconductor substrate (10), wherein the semiconductor capping layer (52) covers and closes the coated deep trench structure (30) and forms together with the semiconductor substrate (10) a thickened semiconductor substrate (10') having the buried deep trench structure (50), and

    out-diffusing (160) dopants of the doped semiconductor layer (32) into the thickened semiconductor substrate (10') wherein the out-diffused dopants provide a trench doping region (60) that extends from the doped semiconductor layer (32) into the thickened semiconductor substrate (10').


     
    2. The method (100) of claim 1, wherein the doped semiconductor layer (32) is deposited to have a doping concentration between 1016 and 1020 cm-3 and a thickness in a range between 1 nm and 100 nm.
     
    3. The method (100) of claim 1 or 2, wherein the step (150) of depositing the semiconductor capping layer (52) on the main surface region (12) of the semiconductor substrate (10) comprises an epitaxial (EPI) overgrow process, wherein a capping layer thickness (54) of the deposited semiconductor capping layer (52) defines a depth of bury of the buried deep trench structure (50) below a main surface region (12') of the thickened semiconductor substrate (10').
     
    4. The method (100) of any of the preceding claims, further comprising:

    depositing (132) a trench coating layer (90) on a surface region (36) of the doped semiconductor layer (32),

    wherein the selective depositing (130) of the doped semiconductor layer (32) and the depositing (132) of the trench coating layer (90) together provide the coated deep trench structure (30).


     
    5. The method (100) of any of the preceding claims, wherein the step of depositing (150) the semiconductor capping layer (52) comprises:

    depositing a first semiconductor capping layer (55) on the main surface region (12) of the semiconductor substrate (10);

    depositing a second semiconductor capping layer (57) on the first semiconductor capping layer (55);

    wherein the first semiconductor capping layer (55) and the second semiconductor capping layer (57) together form the semiconductor capping layer (52); and

    wherein the depositing of the first semiconductor capping layer (55) is performed at a lower temperature than the depositing of the second semiconductor capping layer (57).


     
    6. The method (100) of any of the preceding claims, further comprising:

    widening (122) the deep trench structure (20);

    wherein the steps of etching (120) and widening (122) together provide the deep trench structure (20).


     
    7. The method (100) of any of the preceding claims, further comprising:
    filling the coated deep trench structure (30) with a gas or with a dielectric material before performing the step (150) of depositing the semiconductor capping layer (52).
     
    8. The method (100) of claim 6, wherein the dielectric material filling the coated deep trench structure (30) is optically opaque for an optical radiation to be detected in the sensing region (14).
     
    9. The method (100) of any of the preceding claims, wherein, during the step (120) of etching a deep trench structure (20), a plurality of deep trench portions (20-1, 20-2, ... 20-n) are etched into the semiconductor substrate (10) to form the deep trench structure (20), wherein the deep trench portions (20-1, 20-2, ... 20-n) are formed to at least partially or completely laterally surround the sensing region (14) in the semiconductor substrate (10).
     
    10. The method (100) of any of the preceding claims, wherein the deep trench structure (20) has a depth (27) in a range between 2 µm and 50 µm and has a width (25) in a range between 50 nm and 2 µm.
     
    11. The method (100) of any of the preceding claims,

    wherein the semiconductor substrate (10) comprises a buried doping region (501), which is arranged vertically below the sensing region (14) in the semiconductor substrate (10), and

    wherein the sensing region (14) and the buried doping region (501) are arranged to have complimentary doping types, and

    wherein the deep trench structure (20) extends vertically from the main surface region (12) of the semiconductor substrate (10) into the buried doping region (501).


     
    12. The method (100) of any of the preceding claims, further comprising
    arranging an electronic circuitry (70) for the sensing region (14, 14') in a capping region (72) of the thickened semiconductor substrate vertically above the buried deep trench structure (50).
     
    13. The method (100) of any of the preceding claims, wherein the sensor device is manufactured to comprise optical operative sensing regions (14, 14'), wherein the buried deep trench structure (50) at least partially or completely laterally enclose separate optical operative sensing regions individually.
     
    14. The method (100) of any of the preceding claims, wherein the trench doping region (60) is arranged to provide, in an operative condition of the sensor device, a defined electrical drift field distribution in the sensing regions (14') of the thickened semiconductor substrate (10').
     
    15. Sensor device with a buried deep trench structure, the sensor device comprising:

    a semiconductor substrate (10') having a sensing region (14'), which extends vertically below a main surface region (12') of the semiconductor substrate (10') into the semiconductor substrate (10');

    a semiconductor capping layer (52) that extends vertically below the main surface region (12') of the semiconductor substrate (10') into the semiconductor substrate (10');

    a buried deep trench structure (50) that extends vertically below the capping layer (52) into the semiconductor substrate (10') and laterally relative to the sensing region (14'),

    wherein the buried deep trench structure (50) comprises a doped semiconductor layer (32), the doped semiconductor layer (32) extending from a surface region (36) of the buried deep trench structure (50) into the semiconductor substrate (10');

    a trench doping region (60) that extends from the doped semiconductor layer (32) of the buried deep trench structure (50) into the semiconductor substrate (10');

    electronic circuitry (70) for the sensing region (14') in a capping region (72) of the semiconductor substrate (10') vertically above the buried deep trench structure (50).


     
    16. Sensor device according to claim 15, configured to detect an electromagnetic signal (S1) entering into the sensing region (14') through a region of the main surface region (12') vertically above the sensing region (14').
     


    Ansprüche

    1. Verfahren (100) zum Herstellen eines Sensorbauelements mit einer vergrabenen Tiefgrabenstruktur (50), das folgende Schritte aufweist:

    Bereitstellen (110) eines Halbleitersubstrats (10) mit einer Erfassungsregion (14), die sich unterhalb einer Hauptoberflächenregion (12) des Halbleitersubstrats (10) vertikal in das Halbleitersubstrat (10) erstreckt, wobei eine Maskierungsschicht (16) auf der Hauptoberflächenregion (12) des Halbleitersubstrats (10) angeordnet ist,

    Ätzen (120) einer Tiefgrabenstruktur (20) in das Halbleitersubstrat (10) durch freiliegende Bereiche (18) der Maskierungsschicht (16) zum Anordnen der Tiefgrabenstruktur (20) seitlich relativ zu der Erfassungsregion (14) und vertikal von der Hauptoberflächenregion (12) in das Halbleitersubstrat (10),

    selektives Auftragen, durch Epitaxie (130), einer dotierten Halbleiterschicht (32) auf eine Oberflächenregion (22) der Tiefgrabenstruktur (20) zum Bereitstellen einer beschichteten Tiefgrabenstruktur (30),

    zumindest teilweise Entfernen (140) der Maskierungsschicht (16) zum Freilegen der Hauptoberflächenregion (12) des Halbleitersubstrats (10),

    Auftragen (150) einer Halbleiterverkappungsschicht (52) auf der Hauptoberflächenregion (12) des Halbleitersubstrats (10), wobei die Halbleiterverkappungsschicht (52) die beschichtete Tiefgrabenstruktur (30) bedeckt und schließt und zusammen mit dem Halbleitersubstrat (10) ein verdicktes Halbleitersubstrat (10') mit der vergrabenen Tiefgrabenstruktur (50) bildet, und

    Ausdiffundieren (160) von Dotiermitteln der dotierten Halbeiterschicht (32) in das verdickte Halbleitersubstrat (10'), wobei die ausdiffundierten Dotiermittel eine Grabendotierregion (60) bereitstellen, die sich von der dotierten Halbleiterschicht (32) in das verdickte Halbleitersubstrat (10') erstreckt.


     
    2. Das Verfahren (100) gemäß Anspruch 1, bei dem die dotierte Halbleiterschicht (32) so aufgetragen wird, dass sie eine Dotierkonzentration zwischen 1016 und 1020 cm-3 und eine Dicke in einem Bereich zwischen 1 nm und 100 nm aufweist.
     
    3. Das Verfahren (100) gemäß Anspruch 1 oder 2, bei dem der Schritt (150) des Auftragens der Halbleiterverkappungsschicht (52) auf der Hauptoberflächenregion (12) des Halbleitersubstrats (10) einen Epitaxie(EPI)-Überwachs-Vorgang aufweist, wobei eine Verkappungsschichtdicke (54) der aufgetragenen Halbleiterverkappungsschicht (52) eine Tiefe eines Vergrabens der vergrabenen Tiefgrabenstruktur (50) unterhalb einer Hauptoberflächenregion (12') des verdickten Halbleitersubstrats (10') definiert.
     
    4. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, das ferner folgenden Schritt aufweist:

    Auftragen (132) einer Grabenbeschichtungsschicht (90) auf einer Oberflächenregion (36) der dotierten Halbleiterschicht (32),

    wobei das selektive Auftragen (130) der dotierten Halbleiterschicht (32) und das Auftragen (132) der Grabenbeschichtungsschicht (90) zusammen die beschichtete Tiefgrabenstruktur (30) bereitstellen.


     
    5. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, bei dem der Schritt des Auftragens (150) der Halbleiterverkappungsschicht (52) folgende Schritte aufweist:

    Auftragen einer ersten Halbleiterverkappungsschicht (55) auf der Hauptoberflächenregion (12) des Halbleitersubstrats (10);

    Auftragen einer zweiten Halbleiterverkappungsschicht (57) auf der ersten Halbleiterverkappungsschicht (55);

    wobei die erste Halbleiterverkappungsschicht (55) und die zweite Halbleiterverkappungsschicht (57) zusammen die Halbleiterverkappungsschicht (52) bilden; und wobei das Auftragen der ersten Halbleiterverkappungsschicht (55) bei einer niedrigeren Temperatur durchgeführt wird als das Auftragen der zweiten Halbleiterverkappungsschicht (57).


     
    6. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, das ferner folgenden Schritt aufweist:

    Verbreitern (122) der Tiefgrabenstruktur (20);

    wobei die Schritte des Ätzens (120) und Verbreiterns (122) zusammen die Tiefgrabenstruktur (20) bereitstellen.


     
    7. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, das ferner folgenden Schritt aufweist:
    Füllen der beschichteten Tiefgrabenstruktur (30) mit einem Gas oder mit einem dielektrischen Material, bevor der Schritt (150) des Auftragens der Halbleiterverkappungsschicht (52) durchgeführt wird.
     
    8. Das Verfahren (100) gemäß Anspruch 6, bei dem das dielektrische Material, das die beschichtete Tiefgrabenstruktur (30) füllt, optisch undurchlässig für eine optische Strahlung ist, die in der Erfassungsregion (14) erfasst werden soll.
     
    9. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, bei dem während des Schritts (120) des Ätzens einer Tiefgrabenstruktur (20) eine Mehrzahl von Tiefgrabenabschnitten (20-1, 20-2, ... 20-n) in das Halbleitersubstrat (10) geätzt wird, um die Tiefgrabenstruktur (20) zu bilden, wobei die Tiefgrabenabschnitte (20-1, 20-2, .. 20-n) so gebildet sind, dass sie die Erfassungsregion (14) in dem Halbleitersubstrat (10) zumindest teilweise oder vollständig seitlich umgeben.
     
    10. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, bei dem die Tiefgrabenstruktur (20) eine Tiefe (27) in einem Bereich zwischen 2 µm und 50 µm aufweist und eine Breite (25) in einem Bereich zwischen 50 nm und 2 µm aufweist.
     
    11. Das Verfahren (100) gemäß einem der vorherigen Ansprüche,

    bei dem das Halbleitersubstrat (10) eine vergrabene Dotierregion (501) aufweist, die unterhalb der Erfassungsregion (14) in dem Halbleitersubstrat (10) vertikal angeordnet ist, und

    wobei die Erfassungsregion (14) und die vergrabene Dotierregion (501) so angeordnet sind, dass sie komplementäre Dotiertypen aufweisen, und

    wobei die Tiefgrabenstruktur (20) sich von der Hauptoberflächenregion (12) des Halbleitersubstrats (10) vertikal in die vergrabene Dotierregion (501) erstreckt.


     
    12. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, das ferner folgenden Schritt aufweist:
    Anordnen eines elektronischen Schaltungsaufbaus (70) für die Erfassungsregion (14, 14') in einer Verkappungsregion (72) des verdickten Halbleitersubstrats vertikal oberhalb der vergrabenen Tiefgrabenstruktur (50).
     
    13. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, bei dem das Sensorbauelement so hergestellt ist, dass es optische wirksame Erfassungsregionen (14, 14') aufweist, wobei die vergrabene Tiefgrabenstruktur (50) separate optische wirksame Erfassungsregionen einzeln zumindest teilweise oder vollständig seitlich umschließt.
     
    14. Das Verfahren (100) gemäß einem der vorherigen Ansprüche, bei dem die Grabendotierregion (60) angeordnet ist, um in einem wirksamen Zustand des Sensorbauelements eine definierte Elektrisches-Driftfeld-Verteilung in den Erfassungsregionen (14') des verdickten Halbleitersubstrats (10') bereitzustellen.
     
    15. Sensorbauelement mit einer vergrabenen Tiefgrabenstruktur, wobei das Sensorbauelement folgende Merkmale aufweist:

    ein Halbleitersubstrat (10') mit einer Erfassungsregion (14'), die sich unterhalb einer Hauptoberflächenregion (12') des Halbleitersubstrats (10') vertikal in das Halbleitersubstrat (10') erstreckt;

    eine Halbleiterverkappungsschicht (52), die sich unterhalb der Hauptoberflächenregion (12') des Halbleitersubstrats (10') vertikal in das Halbleitersubstrat (10') erstreckt;

    eine vergrabene Tiefgrabenstruktur (50), die sich unterhalb der Verkappungsschicht (52) vertikal in das Halbleitersubstrat (10') und seitlich relativ zu der Erfassungsregion (14') erstreckt,

    wobei die vergrabene Tiefgrabenstruktur (50) eine dotierte Halbleiterschicht (32) aufweist, wobei sich die dotierte Halbleiterschicht (32) von einer Oberflächenregion (36) der vergrabenen Tiefgrabenstruktur (50) in das Halbleitersubstrat (10') erstreckt;

    eine Grabendotierregion (60), die sich von der dotierten Halbleiterschicht (32) der vergrabenen Tiefgrabenstruktur (50) in das Halbleitersubstrat (10') erstreckt;

    einen elektronischen Schaltungsaufbau (70) für die Erfassungsregion (14') in einer Verkappungsregion (72) des Halbleitersubstrats (10') vertikal oberhalb der vergrabenen Tiefgrabenstruktur (50).


     
    16. Sensorbauelement gemäß Anspruch 15, das dazu ausgebildet ist, ein elektromagnetisches Signal (S1) zu erfassen, das durch eine Region der Hauptoberflächenregion (12') vertikal oberhalb der Erfassungsregion (14') in die Erfassungsregion (14') eintritt.
     


    Revendications

    1. Procédé (100) de fabrication d'un dispositif de capteur ayant une structure (50) enterrée en tranchées profondes, dans lequel :

    on se procure (110) un substrat (10) à semiconducteur ayant une région (14) de détection, qui s'étend verticalement en-dessous d'une région (12) de surface principale du substrat (10) à semiconducteur dans le substrat (10) à semiconducteur, une couche (16) de masquage étant disposée sur la région (12) de surface principale du substrat (10) à semiconducteur,

    on produit (120), par attaque chimique, une structure (20) à tranchées profondes dans le substrat (10) à semiconducteur à travers des zones (18) à découvert de la couche (16) de masquage pour mettre la structure (20) en tranchées profondes latéralement par rapport à la région (14) de détection et verticalement à distance de la région (12) de surface principale dans le substrat (10) à semiconducteur,

    on dépose sélectivement par épitaxie (130) une couche (32) semiconductrice dopée sur une région (22) de surface de la structure (20) en tranchées profondes pour obtenir une structure (30) revêtue en tranchées profondes,

    on retire (140), au moins en partie, la couche (16) de masquage pour mettre à découvert la région (12) de surface principale du substrat (10) à semiconducteur,

    on dépose (150) une couche (52) semiconductrice de recouvrement sur la région (12) de surface principale du substrat (10) à semiconducteur, la couche (52) semiconductrice de recouvrement recouvrant et fermant la structure (30) revêtue en tranchées profondes et formant, ensemble avec le substrat (10) à semiconducteur, un substrat (10') à semiconducteur épaissi ayant la structure (50) enterrée en tranchées profondes, et

    on diffuse (160) des agents de dopage de la couche (32) semiconductrice dopée dans le substrat (10') à semiconducteur épaissi, les agents de dopage diffusés donnant une région (60) de dopage de tranchée, qui s'étend de la couche (32) semiconductrice dopée au substrat (10') à semiconducteur épaissi.


     
    2. Procédé (100) suivant la revendication 1, dans lequel la couche (32) semiconductrice dopée est déposée de manière à avoir une concentration de dopage entre 1016 et 1020 cm-3 et une épaisseur dans une plage comprise entre 1 nm et 100 nm.
     
    3. Procédé (100) suivant la revendication 1 ou 2, dans lequel le stade (150) de dépôt de la couche (52) semiconductrice de recouvrement sur la région (12) de surface principale du substrat (10) à semiconducteur comprend un processus de croissance épitaxiale (EPI), une épaisseur (54) de la couche de recouvrement de la couche (52) semiconductrice de recouvrement déposée définissant une profondeur d'enterrement de la structure (50) enterrée en tranchées profondes en-dessous d'une région (12') de surface principale du substrat (10') à semiconducteur épaissi.
     
    4. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel en outre :

    on dépose (132) une couche (90) de revêtement de tranchée sur une région (36) de surface de la couche (32) semiconductrice dopée,

    dans lequel le dépôt (130) sélectif de la couche (32) semiconductrice dopée et le dépôt (132) de la couche (90) de revêtement de tranchée donnent ensemble la structure (30) revêtue en tranchées profondes.


     
    5. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel le stade de dépôt (150) de la couche (52) semiconductrice de recouvrement comprend :

    déposer une première couche (55) semiconductrice de recouvrement sur la région (12) de surface principale du substrat (10) à semiconducteur,

    déposer une deuxième couche (57) semiconductrice de recouvrement sur la première couche (55) semiconductrice de recouvrement ;

    dans lequel la première couche (55) semiconductrice de recouvrement et la deuxième couche (57) semiconductrice de recouvrement forment ensemble la couche (52) semiconductrice de recouvrement ; et

    dans lequel le dépôt de la première couche (55) semiconductrice de recouvrement est effectuée à une température plus basse que le dépôt de la deuxième couche (57) semiconductrice de recouvrement.


     
    6. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel en outre :

    on élargit (122) la structure (20) en tranchées profondes ;

    dans lequel les stades d'attaque (120) chimique et d'élargissement (122) donnent ensemble la structure (20) en tranchées profondes.


     
    7. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel en outre :
    on remplit la structure (30) revêtue en tranchées profondes d'un gaz ou d'un matériau diélectrique, avant d'effectuer le stade (150) de dépôt de la couche (52) semiconductrice de recouvrement.
     
    8. Procédé (100) suivant la revendication 6, dans lequel le matériau diélectrique remplissant la structure (30) revêtue en tranchées profondes est opaque optiquement à un rayonnement optique à détecter dans la région (14) de détection.
     
    9. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel, pendant le stade (120) de production par attaque chimique d'une structure (20) en tranchées profondes, on produit, par attaque chimique, une pluralité de parties (20-1, 20-2, ..., 20-n) en tranchées profondes dans le substrat (10) à semiconducteur pour former la structure (20) en tranchées profondes, les parties (20-1, 20-2, ..., 20-n) en tranchées profondes étant formées pour entourer au moins partiellement ou complètement latéralement la région (14) de détection du substrat (10) à semiconducteur.
     
    10. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel la structure (20) en tranchées profondes a une profondeur (27) dans une plage comprise entre 2 µm et 50 µm et a une largeur (25) dans une plage comprise entre 50 nm et 2 µm.
     
    11. Procédé (100) suivant l'une quelconque des revendications précédentes,

    dans lequel le substrat (10) à semiconducteur comprend une région (501) de dopage enterrée, qui est disposée verticalement en-dessous de la région (14) de détection du substrat (10) à semiconducteur, et

    dans lequel la région (14) de détection et la région (501) de dopage enterrée sont agencées de manière à avoir des types de dopages complémentaires, et

    dans lequel la structure (20) en tranchées profondes s'étend verticalement de la région (12) de surface principale du substrat (10) à semiconducteur à la région (501) de dopage enterrée.


     
    12. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel en outre
    on met un circuit (70) électronique pour la région (14, 14') de détection dans une région (72) de recouvrement du substrat à semiconducteur épaissi verticalement au-dessus de la structure (50) enterrée en tranchées profondes.
     
    13. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel le dispositif de capteur est fabriqué pour comprendre des régions (14, 14') de détection opératoires d'un point de vue optique, dans lequel la structure (50) enterrée en tranchées profondes entoure au moins partiellement ou complètement latéralement des régions individuellement distinctes de détection opératoires optiquement.
     
    14. Procédé (100) suivant l'une quelconque des revendications précédentes, dans lequel la région (60) de dopage de tranchée est disposée de manière à donner, dans un état de fonctionnement du dispositif de capteur, une distribution définie de champ de migration électrique dans les régions (14') de détection du substrat (10') à semiconducteur épaissi.
     
    15. Dispositif de capteur ayant une structure enterrée en tranchées profondes, le dispositif de capteur comprenant :

    un substrat (10') à semiconducteur ayant une région (14') de détection, qui s'étend verticalement au-dessous d'une région (12') de surface principale du substrat (10') à semiconducteur dans le substrat (10') à semiconducteur ;

    une couche (52) semiconductrice de recouvrement, qui s'étend verticalement au-dessous de la région (12') de surface principale du substrat (10') à semiconducteur dans le substrat (10') à semiconducteur,

    une structure (50) enterrée en tranchées profondes, qui s'étend verticalement en-dessous de la couche (52) de recouvrement dans le substrat (10') à semiconducteur et latéralement par rapport à la région (14') de détection,

    dans lequel la structure (50) enterrée en tranchées profondes comprend une couche (32) semiconductrice dopée, la couche (32) semiconductrice dopée s'étendant d'une région (36) de surface de la structure (50) enterrée en tranchées profondes dans le substrat (10') à semiconducteur ;

    une région (60) de dopage de tranchée, qui s'étend de la couche (32) semiconductrice dopée de la structure (50) enterrée en tranchées profondes dans le substrat (10') à semiconducteur ;

    un circuit (70) électronique pour la région (14') de détection dans une région (72) de recouvrement du substrat (10') à semiconducteur verticalement au-dessus de la structure (50) enterrée en tranchées profondes.


     
    16. Dispositif de capteur suivant la revendication 15, configuré pour détecter un signal (S1) électromagnétique entrant dans la région (14') de détection en traversant une région de la région (12') de surface principale verticalement au-dessus de la région (14') de détection.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description