(19)
(11)EP 3 855 481 A1

(12)EUROPEAN PATENT APPLICATION

(43)Date of publication:
28.07.2021 Bulletin 2021/30

(21)Application number: 21153342.7

(22)Date of filing:  25.01.2021
(51)International Patent Classification (IPC): 
H01L 23/00(2006.01)
H01L 23/31(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 23.01.2020 US 202016750382
10.09.2020 US 202017017462

(71)Applicant: Rockwell Collins, Inc.
Cedar Rapids, IA 52498 (US)

(72)Inventors:
  • Korneisel, Richard
    Cedar Rapids, IA Iowa 52402 (US)
  • Wyckoff, Nathaniel P.
    Marion, IA Iowa 52302 (US)
  • Hamilton, Brandon C.
    Marion, IA Iowa 52302 (US)
  • Mauermann, Jacob R.
    Marion, IA Iowa 52302 (US)
  • Welty, Carlen R.
    Solon, IA Iowa 52333 (US)

(74)Representative: Dehns 
St. Bride's House 10 Salisbury Square
London EC4Y 8JD
London EC4Y 8JD (GB)

  


(54)CONTROLLED INDUCED WARPING OF ELECTRONIC SUBSTRATES VIA ELECTROPLATING


(57) An integrated circuit (IC) package (100;100a-d;600;600a-b;700) incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate (102) having an active side (104) upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers (112) may be deposited to the opposing, or inactive, side (114) of the semiconducting die via electroplating in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.




Description

CROSS-REFERENCE TO RELATED APPLICATIONS



[0001] The present application claims priority under 35 U.S.C. § 120 as a continuation-in-part of co-pending U.S. Patent Application Serial No. 16/750,382, filed January 23, 2020, entitled CONTROLLED INDUCED WARPING OF ELECTRONIC SUBSTRATES.

TECHNICAL FIELD



[0002] The subject matter disclosed herein is directed generally to electronic circuitry and more particularly to semiconducting dies upon which functional circuits are fabricated.

BACKGROUND



[0003] Integrated circuit (IC) packages are small blocks of semiconducting material upon which semiconducting dies and/or functional circuits are fabricated, e.g., via lithography, additive manufacturing, etc. For example, when a functional circuit is built on the active side of the package, remnant internal stresses will be induced in the substrate causing warping in the direction of the active layer. Warping of up to 25% of the package thickness has been observed. Warping in the package or its components may lead to further manufacturability issues, e.g., during lithography or spin-on operations. Additionally, warped packages integrated into end products may experience opens, head-on-pillow defects, and other die interconnect issues which may lead to electrical failures. Finally, package warping may complicate or prevent z-height miniaturization efforts by requiring mechanical designs to accommodate the warping. There is currently no method for addressing these challenges via the flattening of warped packages.

SUMMARY



[0004] An integrated circuit (IC) package is disclosed. In embodiments, the IC package includes one or more electronic substrate layers having an active side (e.g., face) and an inactive side opposite the active side, one or more semiconducting dues and/or functional circuitry fabricated on the active side. The IC package is subject to a degree of inherent warping toward the active side, the warping associated with the fabrication of the die and functional circuitry. To induce a desired degree of counter-warping of the electronic substrates toward the inactive side, the inactive side (e.g., face) may have one or more corrective layers deposited thereon via electroplating or other like electrodeposition techniques.

[0005] In some embodiments, a conductive seed layer or layers is deposited over the inactive side, and the corrective layers deposited over the seed layer.

[0006] In some embodiments, the electrodeposition of the corrective layers is dependent on one or more predetermined parameters.

[0007] In some embodiments, the thickness of the corrective layer or layers is based on the predetermined parameters.

[0008] In some embodiments, the rate of electrodeposition of the corrective layer or layers is based on the predetermined parameters.

[0009] In some embodiments, the predetermined parameters are associated with the semiconducting die, the electronic substrate, and the determined degree of inherent warping therein.

[0010] In some embodiments, the predetermined parameters are associated with the corrective layers (e.g., material composition) or the desired degree of induced warping.

[0011] In some embodiments, the corrective layers include one or more of substantially elemental metallic components and metallic alloy components.

[0012] In some embodiments, the desired degree of induced warping is a temporary warping, and the corrective layers are fully or partially removable.

[0013] In some embodiments, the inherent warping is detected or identified within selected portions of the surface area of the electronic substrate, and the corrective layers applied to the selected warped portions.

[0014] A method for induced warping of an IC package or its components is also disclosed. In embodiments, the method includes determining a degree of inherent warping toward an active side of an electronic substrate of the IC package, the inherent warping associated with the fabrication of semiconducting die/s and functional circuitry upon the active side. The method includes determining a degree of desired induced warping stress (e.g., counter-warping) toward an inactive side of the electronic substrate, the inactive side opposite the active side. The method includes applying one or more conductive seed layers to the inactive side. The method includes implementing the desired induced warping stress by applying, via electroplating or electrodeposition, at least one corrective layer over the seed layers on the inactive side.

[0015] In some embodiments, the method includes determining one or more parameters based on the semiconducting die, the electronic substrate, the determined degree of inherent warping therein, the corrective layer or layers, and the desired warping stress to be induced within the electronic substrate. The corrective layer or layers are applied over the seed layers based on these determined parameters.

[0016] In some embodiments, the method includes applying the corrective layer or layers at a predetermined rate based on the determined parameters.

[0017] In some embodiments, the method includes applying the corrective layer or layers to a predetermined thickness based on the determined parameters.

[0018] In some embodiments, the method includes determining the degree of inherent warping with respect to selected portions of the electronic substrate, and applying the seed layers over the selected portions.

[0019] In some embodiments, the method further includes partially or fully restoring the inherent warping by removing the corrective layer or layers, e.g., via electropolishing.

[0020] This Summary is provided solely as an introduction to subject matter that is fully described in the Detailed Description and Drawings. The Summary should not be considered to describe essential features nor be used to determine the scope of the Claims. Moreover, it is to be understood that both the foregoing Summary and the following Detailed Description are example and explanatory only and are not necessarily restrictive of the subject matter claimed.

BRIEF DESCRIPTION OF THE DRAWINGS



[0021] The detailed description is described with reference to the accompanying figures. The use of the same reference numbers in different instances in the description and the figures may indicate similar or identical items. Various embodiments or examples ("examples") of the present disclosure are disclosed in the following detailed description and the accompanying drawings. The drawings are not necessarily to scale. In general, operations of disclosed processes may be performed in an arbitrary order, unless otherwise provided in the claims. In the drawings:

FIG. 1 is a diagrammatic cross section illustrating an integrated circuit (IC) package in accordance with example embodiments of this disclosure;

FIG. 2 is a diagrammatic cross section illustrating the IC package of FIG. 1;

FIGS. 3A through 3C are diagrammatic cross sections illustrating induced warping operations of the IC package of FIG. 1;

FIG. 4 is a diagrammatic cross section illustrating operations on the IC package of FIG. 1;

FIG. 5 is a flow diagram illustrating a method for induced warping of an IC package in accordance with example embodiments of this disclosure;

FIGS. 6A through 6C are diagrammatic cross sections illustrating an IC package configured for corrective warping via electrodeposition in accordance with example embodiments of this disclosure;

FIGS. 7A and 7B are diagrammatic overhead views of an IC package configured for portional corrective warping in accordance with example embodiments of this disclosure;

and FIG. 8 is a flow diagram illustrating a method for induced warping of an IC package in accordance with example embodiments of this disclosure.


DETAILED DESCRIPTION



[0022] Before explaining one or more embodiments of the disclosure in detail, it is to be understood that the embodiments are not limited in their application to the details of construction and the arrangement of the components or steps or methodologies set forth in the following description or illustrated in the drawings. In the following detailed description of embodiments, numerous specific details may be set forth in order to provide a more thorough understanding of the disclosure. However, it will be apparent to one of ordinary skill in the art having the benefit of the instant disclosure that the embodiments disclosed herein may be practiced without some of these specific details. In other instances, well-known features may not be described in detail to avoid unnecessarily complicating the instant disclosure.

[0023] As used herein a letter following a reference numeral is intended to reference an embodiment of the feature or element that may be similar, but not necessarily identical, to a previously described element or feature bearing the same reference numeral (e.g., 1, 1a, 1b). Such shorthand notations are used for purposes of convenience only and should not be construed to limit the disclosure in any way unless expressly stated to the contrary.

[0024] Further, unless expressly stated to the contrary, "or" refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).

[0025] In addition, use of "a" or "an" may be employed to describe elements and components of embodiments disclosed herein. This is done merely for convenience and "a" and "an" are intended to include "one" or "at least one," and the singular also includes the plural unless it is obvious that it is meant otherwise.

[0026] Finally, as used herein any reference to "one embodiment" or "some embodiments" means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment disclosed herein. The appearances of the phrase "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, and embodiments may include one or more of the features expressly described or inherently present herein, or any combination or sub-combination of two or more such features, along with any other features which may not necessarily be expressly described or inherently present in the instant disclosure.

[0027] Referring to FIG. 1, an integrated circuit (IC) package 100 is disclosed. The IC package 100 may include electronic substrates 102 and an active layer 104 upon which one or more semiconducting dies 106 and/or additional functional circuitry may be fabricated.

[0028] In embodiments, the electronic substrates 102 may be fashioned of silicon or any other appropriate semiconducting material. The active layer 104 may include, for example, additive layers or other functional circuitry fabricated upon the electronic substrates 102 (e.g., onto an active side of the electronic substrate) or upon any additive layers deposited thereon, resulting in an inherent warping 108 toward the active layer (e.g., due to internal compressive stressed within the active layer). An induced warping stress may be imparted to the IC package 100 by utilizing thin film deposition (TFD) instrumentation to deposit (110) or bond one or more corrective layers 112 on the inactive side (114) of the electronic substrates 102 (e.g., the side opposite the active layer/active side 104). As the corrective layers 112 are applied to the inactive side 114 of the electronic substrates 102 (e.g., and condense thereon as thin films), the functionality of the active layer 104 is unaffected. For example, depending on the desired degree of induced warping (and, e.g., the corresponding amount of compressive or tensile stress to induce within the active layer 104), the corrective layers 112 may be deposited via physical vapor deposition (PVD), sputtering deposition, electroplating, or any other like instrumentation and process.

[0029] Referring also to FIG. 2, the IC package 100a may be implemented and may function similarly to the IC package 100 of FIG. 1, except that residual stresses within the corrective layers 112 bonded to the inactive side 114 may induce compressive stresses (116a) and/or tensile stresses (116b) contributing to correctively warp (116) the electronic substrates 102 of the IC package 100 of FIG. 1 in the direction of the inactive side 114, such that the electronic substrates 102 and/or semiconducting die 106 are warped into a horizontal or near-horizontal orientation (as shown by the IC package 100a of FIG. 2).

[0030] In embodiments, the precise direction and amount of induced warping necessary to achieve the substantially horizontal IC package 100a may depend on a variety of parameters. For example, the material composition as well as the thickness and dimensions (e.g., x/y) of the electronic substrates 102 and/or semiconducting die 106 may affect the necessary direction and degree of induced warping 116 to correct the inherent warping (108, FIG. 1). Similarly, parameters may also be determined for optimal deposition of the corrective layers 112. For example, the corrective layers 112 may include copper or other metallic elements, alloys, or compounds. In some embodiments, the corrective layers 112 may include ceramic layers, metalloids, amorphous (e.g., glassy) semiconducting materials, or any appropriate combinations thereof. By selecting corrective layers 112 of a particular thickness and depositing the corrective layers to the inactive side 114 at a particular deposition rate (e.g., between 5 Angstroms per second (Å/s) and 120 Å/s), significant corrective deflections of the electronic substrates 102 may be achieved. For example, higher deposition rates of corrective layers 112 primarily comprising copper may be associated with higher residual stresses and therefore higher degrees of induced warping 116. Similarly, the number of corrective layers 112 deposited may be selected with a particular degree of induced warping 116 in mind, as described below.

[0031] In some embodiments, determination of the optimal deposition parameters and deposition of the corrective layers 112 may occur during the active layer manufacturing phase of the production process of the IC package 100a. In other embodiments, parameter determination and deposition of the corrective layers 112 may occur during other phases of the production process or based on other types of IC package 100a, e.g., during reflow soldering or in response to warping issues associated with flip-chip packages and thin ball grid arrays.

[0032] Referring also to FIGS. 3A through 3C, the IC packages 100b-c may be implemented and may function similarly to the IC packages 100, 100a of FIGS. 1 and 2, except that the IC packages 100b-c may incorporate multiple corrective layers 112a-n deposited on the inactive side 114 via TFD (e.g., at lower deposition rates (e.g., 5 Å/s or less) so as to minimize impact stress). For example, referring in particular to FIG. 3A, a first corrective layer 112a may be bonded (110a) to the inactive side 114 of the IC package 100b at a particular deposition rate. Referring in particular to FIG. 3B, a second corrective layer 112b may be deposited upon (110b) or bonded to the first corrective layer 112a, inducing a further warping 116a-b of the IC package 100b. Referring in particular to FIG. 3C, the continued deposition of multiple corrective layers 112a-n may provide, through each successive corrective layer, additional induced warping (116a-b) toward the inactive layer 114 such that the inherent warping (108, FIG. 1) of the IC package 100b may be reduced or even reversed, resulting in the substantially horizontal IC package 100c shown by FIG. 3C.

[0033] Referring to FIG. 4, the IC package 100d may be implemented and may function similarly to the IC packages 100, 100a-c of FIGS. 1 through 3C, except that one or more corrective layers 112a-n may be removable layers configured for temporary induced warping. For example, an outer corrective layer 112n may be partially or fully removed (402) from the electronic substrate 102, fully or partially relieving the corresponding internal compressive and tensile stresses and thereby relieving the corresponding induced warping (116a-b, FIGS. 3B-C).

[0034] Referring to FIG. 5, the method 500 for induced warping of an integrated circuit (IC) package may be implemented with respect to the IC packages 100, 100-d of FIGS. 1 through 4, and may incorporate the following steps.

[0035] At a step 502, the degree of inherent warping toward the active side of an electronic substrate of the IC package due to the fabrication of a semiconducting die and/or functional circuitry on the active side is determined. For example, parameters associated with the semiconducting die or with the electronic substrates may be determined, e.g., the dimensions of the substrate, the thickness of the substrate, or the material composition of the substrate.

[0036] At a step 504, a desired degree of induced warping stress toward the inactive side (e.g., opposite the active side) of the electronic substrate is determined. For example, the desired material composition of corrective layers applicable to the inactive side to correctively warp the substrate to the desired degree may be determined, as well as the desired number of layers to be applied (if more than one corrective layer is to be applied).

[0037] At a step 506, the desired degree of induced warping stress is implemented by applying at least one corrective layer to the active side via thin film deposition (TFD). For example, the corrective layer/s may be applied at a predetermined deposition rate, or to a predetermined thickness, based on the determined parameters.

[0038] The method 500 may include an additional step 508. At the step 508, a portion (partial or full) of the at least one applied corrective layer is partially or fully removed from the inactive side upon which it was deposited to remove the corresponding induced warping stress.

[0039] Referring now to FIG. 6A, the IC package 600 may be implemented and may function similarly to the IC packages 100, 100a-d of FIGS. 1 through 4, except that the IC package 600 may be configured for corrective warping via electroplating or any appropriate like means of electrophoretic deposition (EPD). The IC package 600 may include electronic substrates 102, active layer 104, and one or more semiconducting dies 106.

[0040] In embodiments, one or more conductive seed layers 602 may be applied to the electronic substrates 102 on its inactive side 114. For example, the inactive side 114 may not incorporate conductive materials sufficient to support EPD.

[0041] Referring also to FIG. 6B, the IC package 600a may be implemented and may function similarly to the IC package 600 of FIG. 6A.

[0042] In embodiments, the IC package 600a may have one or more corrective layers 112 deposited thereon via electroplating or EPD. By way of a non-limiting example, the IC package 600a may be immersed in an electrolytic solution 604 along with a consumable metal anode 606 (e.g., copper, gold, nickel, or any other substantially elemental metal or metallic alloy suitable for EPD). A direct current 608 directed to the anode 606 may cause its component metal/s to dissolve into the electrolytic solution 604. The seed layer 602 may serve as a cathode upon which the dissolved metal ions plate, or deposit onto (610), at a desired rate (and/or, e.g., to a desired thickness) based on predetermined parameters as described above.

[0043] Referring also to FIG. 6C, the IC package 600b may be implemented and may function similarly to the IC packages 600, 600a of FIGS. 6A-B, except that the IC package 600b may undergo corrective warping (116) due to the application of the corrective layer/s 112. For example, the IC package 600b may be correctively warped 116 to a horizontal or near-horizontal orientation, or to a greater or lesser degree based on predetermined parameters as described above.

[0044] Referring to FIGS. 7A and 7B, the IC package 700 may be implemented and may function similarly to the IC packages 100, 600 of FIGS. 1 through 6C, except that the IC package 700 may experience interconnect defects 702 (e.g., inherent warping, opens, head-on-pillows) within determinable defective portions 704 of the electronic substrates 102 (as opposed to throughout the entire substrate).

[0045] In embodiments, the IC package 700 may be correctively warped on a portional bases to counteract interconnect defects 702 on a targeted or selective basis. For example, warping parameters may be determined (e.g., with respect to one or more of the composition of the electronic substrates 102 or the semiconducting die 104, the nature and magnitude of the observed interconnect defects 702, the composition of the corrective layer/s 112, or the desired degree of corrective warping 116 and, per the determined parameters, seed layers 602 applied to the defective portions/s 704 on their inactive side 114.

[0046] In embodiments, the corrective layers 112 may be electrophorically deposited over the seed layers 602 to selectively induce corrective warping 116 within the defective portions 704 of the IC package 700. In some embodiments, the defective portions 704 may be correctively warped 116 via the application of corrective layers 112 via TFD as described above. Similarly, in some embodiments the corrective layers 112, or some portion thereof, may be removed (e.g., via electropolishing) to restore some or all of the inherent warping stress (108, FIG. 1).

[0047] Referring to FIG. 8, the method 800 for induced warping of an integrated circuit (IC) package may be implemented with respect to the IC packages 600, 700 of FIGS. 6A through 7B, and may incorporate the following steps.

[0048] At a step 802, a degree of inherent warping (or, more generally, interconnect defect) is determined. For example, the inherent warp or interconnect defect may orient toward, an active side of an electronic substrate and may result from the fabrication of at least one of a semiconducting die and functional circuitry upon the active side. In some embodiments, the inherent warping may be present in only a portion of the electronic substrate.

[0049] At a step 804, a desired degree of corrective warping stress to induce is determined based on one or more parameters. For example, the desired degree of corrective warping may be based on one or more of the composition of the semiconducting die, the electronic substrate, or the corrective layers; the degree of inherent warping or interconnect defect; or the desired induced warping stress.

[0050] At a step 806, one or more conductive seed layers are applied to the inactive side of the IC package.

[0051] At a step 808, the desired warping stress is implemented by applying the corresponding corrective layers via electrodeposition upon the seed layers. For example, the corrective layers may be applied according to one or more predetermined parameters, e.g., the rate at which the corrective layers are applied, or the thickness of the corrective layers. In some embodiments, the corrective layers (as well as the conductive seed layers) may be applied only to selected portions of the inactive side.

[0052] The method 800 may include an additional step 810. At the step 810, the inherent warping may be partially or fully restored by removing the corrective layers via electropolishing or any like appropriate means of removal.

CONCLUSION



[0053] It is to be understood that embodiments of the methods disclosed herein may include one or more of the steps described herein. Further, such steps may be carried out in any desired order and two or more of the steps may be carried out simultaneously with one another. Two or more of the steps disclosed herein may be combined in a single step, and in some embodiments, one or more of the steps may be carried out as two or more sub-steps. Further, other steps or sub-steps may be carried in addition to, or as substitutes to one or more of the steps disclosed herein.

[0054] Although inventive concepts have been described with reference to the embodiments illustrated in the attached drawing figures, equivalents may be employed and substitutions made herein without departing from the scope of the claims. Components illustrated and described herein are merely examples of a system/device and components that may be used to implement embodiments of the inventive concepts and may be replaced with other devices and components without departing from the scope of the claims. Furthermore, any dimensions, degrees, and/or numerical ranges provided herein are to be understood as non-limiting examples unless otherwise specified in the claims.


Claims

1. An integrated circuit (IC) package (100;100a-d;600;600a-b;700), comprising:

at least one semiconducting die (106);

an electronic substrate (102) having an active side (104) and an inactive side (114) opposite the active side, at least one of the semiconducting die and functional circuitry fabricated on the active side,

at least one of the semiconducting die and the electronic substrate associated with an inherent warping toward the active side,
and

the inactive side having at least one corrective layer (112) deposited thereupon via electrodeposition, the at least one corrective layer configured for desired induced warping (116) of the electronic substrate toward the inactive side.


 
2. The IC package of claim 1, wherein:

at least one conductive seed layer (602) is deposited over the inactive side; and

the at least one corrective layer is deposited upon the at least one seed layer.


 
3. The IC package of claim 1 or 2, wherein the at least one corrective layer is deposited based on at least one predetermined parameter.
 
4. The IC package of claim 3, wherein the at least one corrective layer is deposited to a predetermined thickness based on the at least one predetermined parameter.
 
5. The IC package of claim 3 or 4, wherein the at least one corrective layer is deposited at a predetermined rate based on the at least one predetermined parameter.
 
6. The IC package of claim 3, 4, or 5, wherein the at least one predetermined parameter corresponds to at least one of the semiconducting die, the electronic substrate, and the inherent warping.
 
7. The IC package of claim 3, 4, or 5, wherein the at least one predetermined parameter corresponds to at least one of the corrective layer and the desired induced warping.
 
8. The IC package of any preceding claim, wherein the at least one corrective layer is selected from a metallic layer and a metallic alloy layer.
 
9. The IC package of any preceding claim, wherein:

the desired induced warping includes a temporary induced warping:
and

the at least one corrective layer is at least partially removable.


 
10. The IC package of any preceding claim, wherein:

the inactive side corresponds to a surface area;

the inherent warping of the electronic substrate corresponds to one or more warped portions of the surface area;
and

the at least one corrective layer is applied to the one or more warped portions.


 
11. A method for induced warping of an integrated circuit (IC) package (100;100a-d;600;600a-b;700), the method comprising:

determining (502;802) a degree of inherent warping toward an active side (104) of an electronic substrate, the inherent warping associated with a fabrication of at least one of a semiconducting die (106) and functional circuitry upon the active side;

determining (504;804) a degree of desired induced warping stress toward an inactive side (114) of the electronic substrate, the inactive side opposite the active side;

applying (806) at least one conductive seed layer to the inactive side;
and

implementing (506;808) the desired induced warping stress by applying, via electrodeposition, at least one corrective layer to the seed layer.


 
12. The method of claim 11, wherein:

determining a degree of desired induced warping stress toward an inactive side of the electronic substrate, the inactive side opposite the active side, includes: determining at least one parameter corresponding to at least one of the semiconducting die, the electronic substrate, the degree of inherent warping, the corrective layer, and the desired induced warping stress;
and

implementing the desired induced warping stress by applying, via electrodeposition, at least one corrective layer to the seed layer includes: applying the at least one corrective layer to the seed layer based on the at least one determined parameter.


 
13. The method of claim 12, wherein implementing the desired induced warping stress by applying, via electrodeposition, at least one corrective layer to the seed layer includes:
applying the at least one corrective layer at a predetermined rate based on the at least one determined parameter.
 
14. The method of claim 12 or 13, wherein implementing the desired induced warping stress by applying, via electrodeposition, at least one corrective layer to the seed layer includes:
applying the at least one corrective layer to a predetermined thickness based on the at least one determined parameter.
 
15. The method of claim 11, 12, 13, or 14, wherein:

determining a degree of inherent warping toward an active side of an electronic substrate includes determining the degree of inherent warping within one or more warped portions of the electronic substrate;
and

applying at least one conductive seed layer to the inactive side includes applying the conductive seed layer to the one or more warped portions; and/or

at least partially restoring the inherent warping by at least partially removing (508;810) the at least one corrective layer via electropolishing.


 




Drawing

























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Search report




Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description