(19)
(11)EP 4 071 257 A1

(12)EUROPEAN PATENT APPLICATION
published in accordance with Art. 153(4) EPC

(43)Date of publication:
12.10.2022 Bulletin 2022/41

(21)Application number: 21776955.3

(22)Date of filing:  19.03.2021
(51)International Patent Classification (IPC): 
C22C 9/00(2006.01)
C22C 27/04(2006.01)
B23K 35/14(2006.01)
H01L 21/52(2006.01)
C22C 13/00(2006.01)
H01L 23/12(2006.01)
B23K 35/26(2006.01)
(52)Cooperative Patent Classification (CPC):
B23K 35/0205; C22C 27/04; C22C 9/00; H01L 21/52; H01L 25/07; H01L 25/18; C22C 13/00; H01L 23/12; B23K 35/26
(86)International application number:
PCT/JP2021/011341
(87)International publication number:
WO 2021/193420 (30.09.2021 Gazette  2021/39)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(30)Priority: 23.03.2020 JP 2020050674

(71)Applicant: Senju Metal Industry Co., Ltd.
Tokyo 120-8555 (JP)

(72)Inventors:
  • KAMEDA, Naoto
    Tokyo 120-8555 (JP)
  • TSUCHIYA, Masato
    Tokyo 120-8555 (JP)
  • NAKAMURA, Katsuji
    Tokyo 120-8555 (JP)
  • MUNEKATA, Osamu
    Tokyo 120-8555 (JP)
  • TSURUTA, Kaichi
    Tokyo 120-8555 (JP)

(74)Representative: Hoffmann Eitle 
Patent- und Rechtsanwälte PartmbB Arabellastraße 30
81925 München
81925 München (DE)

  


(54)LAYERED BONDING MATERIAL, SEMICONDUCTOR PACKAGE, AND POWER MODULE


(57) In a layered bonding material 10, a coefficient of linear expansion of a base material 11 is 5.5 to 15.5 ppm/K and a first surface and a second surface of the base material 11 are coated with pieces of lead-free solder 12a and 12b.




Description

Technical Field



[0001] The present disclosure relates to a layered bonding material, a semiconductor package, and a power module.

Background Art



[0002] Recently, required characteristics of semiconductor devices have become higher. SiC, GaAs, GaN, and the like are used in addition to Si, which has been used as a material of semiconductor devices. Semiconductor devices made of these materials have excellent characteristics including a rise in an operating temperature and expanded bandgaps. The semiconductor devices are applied to power semiconductor devices such as a power transistor.

[0003] The power semiconductor devices are capable of performing a high-temperature operation. The temperature of a solder joint in a bonding section sometimes reaches high temperature equal to or higher than 200°C. Under such a high-temperature environment, there is a problem in that a distortion due to a difference between CTEs (Coefficients of Thermal Expansion) of a semiconductor device and a substrate occurs in a bonding section between the semiconductor device and the substrate, a crack occurs from the distortion, and, as a result, the life of the power semiconductor product is reduced.

[0004] Japanese Patent Laid-Open No. 2009-269075 describes a manufacturing method for a layered solder material including soft Pb or Pb-based alloy as a stress relaxation layer. However, since the stress relaxation layer contains Pb, the manufacturing method does not conform to environmental regulations such as a RoHS (Restriction of Hazardous Substances).

[0005] Japanese Patent Laid-Open No. 2015-23183 describes a power module including a semiconductor device, a first metal layer formed with one surface bonded to the semiconductor device, an organic insulating film that is in contact with the semiconductor device and formed in an outer circumference peripheral section of the other surface of the first metal layer, a second metal layer that is in contact with the organic insulating film and is formed to be bonded to the center of the other surface of the first metal layer, and a bonding material formed to be bonded to the other surface of the first metal layer via the second metal layer.

[0006]  Japanese Patent Laid-Open No. 2009-147111 describes a bonding material obtained by stacking surface layers on upper and lower surfaces of a plate-like center layer, the center layer having a melting point higher than a melting point of the surface layers. As specific examples of the center layer, a single phase of bismuth or an alloy with silver, copper, antimony, indium, tin, nickel, germanium, tellurium, or phosphorus containing bismuth as a main component is described.

Summary of Invention



[0007] It is desired to provide a layered bonding material, a semiconductor package, and a power module that can relax a distortion that occurs in a bonding section, in particular, under a high-temperature environment.

[0008] In a layered bonding material according to an embodiment, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K and a first surface and a second surface of the base material are coated with lead-free solder.

Brief Description of Drawings



[0009] 

[Figure 1] Figure 1 is a longitudinal sectional view showing a schematic configuration of a layered bonding material according to an embodiment.

[Figure 2] Figure 2 is a longitudinal sectional view showing a schematic configuration of a semiconductor package according to the embodiment.

[Figure 3] Figure 3 is a table showing the configuration of a bonding member used in a cooling and heating cycle test.

[Figure 4] Figure 4 is a table showing the configuration of the bonding member used in the cooling and heating cycle test.

[Figure 5] Figure 5 is a bar graph showing defect part change ratios of examples 1 and 2 and comparative examples 1 and 2 in comparison.

[Figure 6] Figure 6 is a bar graph showing defect part change ratios of examples 3 and 4 and a comparative example 3 in comparison.

[Figure 7] Figure 7 is a bar graph showing defect part change ratios of examples 5 and 6 and comparative examples 4 and 5 in comparison.


Description of Embodiment



[0010] As a result of, while conforming to environmental regulations such as the RoHS, repeating intensive studies in order to find a technique that can relax a distortion that occurs in a bonding section, the present inventors came to know that a distortion that occurs in the bonding section due to a CTE difference between a semiconductor device and a substrate can be relaxed by using a material having a coefficient of thermal expansion within a predetermined range as a core material while adopting lead-free solder as solder of the bonding section. Further, the present inventors came to know that an excessive temperature rise of the bonding section can be suppressed and, as a result, the life of a product can be greatly extended compared with the related art by using, in particular, a Cu-W-based material or a Cu-Mo-based material (or a layered material or a composite material thereof) as the core material while adopting the lead-free solder as the solder of the bonding section. An embodiment explained below has been devised based on such knowledge.

[0011] In a layered bonding material according to a first aspect of the embodiment, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K, and a first surface and a second surface of the base material are coated with lead-free solder.

[0012] When the present inventors actually performed verification with a cooling and heating cycle test, it was found that, according to such an aspect, it is possible to relax a distortion that occurs in a bonding section, in particular, under a high-temperature environment and achieve high reliability. According to the idea of the present inventors, the coefficient of linear expansion of the base material is present in the middle between a coefficient of linear expansion of a semiconductor device and a coefficient of linear expansion of a material of a substrate and a heat radiating section and is balanced. Therefore, it is considered possible to relax a distortion that occurs in the bonding section due to a CTE difference between the semiconductor device and the substrate, in particular, under a high-temperature environment.

[0013] A layered bonding material according to a second aspect of the embodiment is the layered bonding material according to the first aspect, wherein the coefficient of linear expansion of the base material is 5.9 to 14.4 ppm/K.

[0014] When the present inventors actually performed verification with the cooling and heating cycle test, it was found that, according to such an aspect, it is possible to relax a distortion that occurs in a bonding section on the semiconductor device side, in particular, under a high-temperature environment and achieve high reliability.

[0015] A layered bonding material according to a third aspect of the embodiment is the layered bonding material according to the first or second aspect, wherein the coefficient of linear expansion of the base material is 7.0 to 11.6 ppm/K.

[0016] When the present inventors actually performed verification with the cooling and heating cycle test, it was found that, according to such an aspect, an effect of relaxing a distortion that occurs in a bonding section on the substrate side is higher and it is possible to achieve higher reliability.

[0017] A layered bonding material according to a fourth aspect of the embodiment is the layered bonding material according to any one of the first to third aspects, wherein the base material is made of any one of a Cu-W-based material, a Cu-Mo-based material, a layered material of the Cu-W-based material and the Cu-Mo-based material, a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu-W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu-Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu-W-based material and the Cu-Mo-based material.

[0018] According to such an aspect, since the base material has high thermal conductivity, it is possible to prevent an excessive temperature rise in the bonding section, a thermal distortion itself that occurs in the bonding section is reduced, and, as a result, this more advantageously acts on the extension of the life of a product.

[0019] A layered bonding material according to a fifth aspect of the embodiment is the layered bonding material according to any one of the first to fourth aspects, wherein a Cu content of the base material is 60% or lower.

[0020] According to such an aspect, since the coefficient of linear expansion of the base material is lower, it is possible to further relax a distortion that occurs in the bonding section due to the CTE difference, in particular, under a high-temperature environment.

[0021] A layered bonding material according to a sixth aspect of the embodiment is the layered bonding material according to any one of the first to fifth aspects, wherein a Cu content of the base material is 15% or higher.

[0022] According to such an aspect, since the thermal conductivity of the base material is further improved, a thermal distortion itself that occurs in the bonding section can be further reduced.

[0023] A layered bonding material according to a seventh aspect of the embodiment is the layered bonding material according to any one of the first to sixth aspects, wherein an interface between at least one of the first surface and the second surface of the base material and the lead-free solder is undercoated with Ni and Sn in order from the base material side.

[0024] According to such an aspect, it is possible to improve adhesion of the base material and the lead-free solder.

[0025] A layered bonding material according to an eighth aspect of the embodiment is the layered bonding material according to any one of the first to seventh aspects, wherein at least one of a thickness of the lead-free solder with which the first surface is coated and a thickness of the lead-free solder with which the second surface is coated is 20 to 100 µm.

[0026]  A layered bonding material according to a ninth aspect of the embodiment is the layered bonding material according to any one of the first to eighth aspects, wherein at least one of a ratio of thicknesses of the base material and the lead-free solder with which the first surface is coated and a ratio of thicknesses of the base material and the lead-free solder with which the second surface is coated is 2:1 to 10:1.

[0027] A layered bonding material according to a tenth aspect of the embodiment is the layered bonding material according to any one of the first to ninth aspects, wherein a melting point of the lead-free solder is 210°C or higher. The melting point of the lead-free solder may be 230°C or higher.

[0028] According to such an aspect, even when the temperature of the layered bonding material reaches high temperature equal to or higher than 200°C because of a rise in an operating temperature of the semiconductor device, the lead-free solder included in the layered bonding material can be prevented from melting to cause a breakdown.

[0029] A semiconductor package according to an eleventh aspect of the embodiment includes: a substrate; a semiconductor device disposed on the substrate; and a layered bonding material disposed between the substrate and the semiconductor device and bonding the substrate and the semiconductor device, wherein, in the layered bonding material, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K, and a first surface and a second surface of the base material are coated with lead-free solder.

[0030] When the present inventors actually performed verification with a cooling and heating cycle test, it was found that, according to such an aspect, it is possible to relax a distortion that occurs in a bonding section, in particular, under a high-temperature environment and achieve high reliability. According to the idea of the present inventors, the coefficient of linear expansion of the base material included in the layered bonding material is present in the middle between a coefficient of linear expansion of a material of the semiconductor device and a coefficient of linear expansion of the substrate and is balanced. Therefore, it is considered possible to relax a distortion that occurs in the bonding section due to a CTE difference between the semiconductor device and the substrate, in particular, under a high-temperature environment.

[0031] A semiconductor package according to a twelfth aspect of the embodiment includes: a substrate; a semiconductor device disposed on the substrate; a first layered bonding material disposed between the substrate and the semiconductor device and bonding the substrate and the semiconductor device; a heat radiating section disposed on an opposite side of the semiconductor device on the substrate; and a second layered bonding material disposed between the substrate and the heat radiating section and bonding the substrate and the heat radiating section, wherein, in at least one of the first layered bonding material and the second layered bonding material, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K, and a first surface and a second surface of the base material are coated with lead-free solder.

[0032] When the present inventors actually performed verification with a cooling and heating cycle test, it was found that, according to such an aspect, it is possible to relax a distortion that occurs in a bonding section, in particular, under a high-temperature environment and achieve high reliability. According to the idea of the present inventors, the coefficient of linear expansion of the base material included in the layered bonding material is present in the middle between a coefficient of linear expansion of the semiconductor device and a coefficient of linear expansion of a material of the substrate and the heat radiating section and is balanced. Therefore, it is considered possible to relax a distortion that occurs in the bonding section due to a CTE difference between the semiconductor device and the substrate, in particular, under a high-temperature environment.

[0033] A semiconductor package according to a thirteenth aspect of the embodiment is the semiconductor package according to the eleventh or twelfth aspect, wherein the coefficient of linear expansion of the base material is 5.9 to 14.4 ppm/K.

[0034] When the present inventors actually performed verification with a cooling and heating cycle test, it was found that, according to such an aspect, it is possible to relax a distortion that occurs in the bonding section on the semiconductor device side, in particular, under a high-temperature environment and achieve high reliability.

[0035] A semiconductor package according to a fourteenth aspect of the embodiment is the semiconductor package according to any one of the eleventh to thirteenth aspects, wherein the coefficient of linear expansion of the base material is 7.0 to 11.6 ppm/K.

[0036]  When the present inventors actually performed verification with the cooling and heating cycle test, it was found that, according to such an aspect, an effect of relaxing a distortion that occurs in a bonding section on the substrate side is higher and it is possible to achieve higher reliability.

[0037] A semiconductor package according to a fifteenth aspect of the embodiment is the semiconductor package according to any one of the eleventh to fourteenth aspects, wherein the base material is made of any one of a Cu-W-based material, a Cu-Mo-based material, a layered material of the Cu-W-based material and the Cu-Mo-based material, a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu-W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu-Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu-W-based material and the Cu-Mo-based material.

[0038] According to such an aspect, since the base material has high thermal conductivity, it is possible to prevent an excessive temperature rise in the bonding section, a thermal distortion itself that occurs in the bonding section is reduced, and, as a result, this more advantageously acts on the extension of the life of a product.

[0039] A semiconductor package according to a sixteenth aspect of the embodiment is the semiconductor package according to any one of the eleventh to fifteenth aspects, wherein a Cu content of the base material is 60% or lower.

[0040] According to such an aspect, since the coefficient of linear expansion of the base material included in the layered bonding material is lower, it is possible to further relax a distortion that occurs in the bonding section due to the CTE difference, in particular, under a high-temperature environment.

[0041] A semiconductor package according to a seventeenth aspect of the embodiment is the semiconductor package according to any one of the eleventh to sixteenth aspects, wherein a Cu content of the base material is 15% or higher.

[0042] According to such an aspect, since the thermal conductivity of the base material included in the layered bonding material is further improved, a thermal distortion itself that occurs in the bonding section can be further reduced.

[0043] A semiconductor package according to an eighteenth aspect of the embodiment is the semiconductor package according to any one of the eleventh to seventeenth aspects, wherein an interface between at least one of the first surface and the second surface of the base material and the lead-free solder is undercoated with Ni and Sn in order from the base material side.

[0044] According to such an aspect, it is possible to improve adhesion of the base material included in the layered bonding material and the lead-free solder.

[0045] A semiconductor package according to a nineteenth aspect of the embodiment is the semiconductor package according to any one of the eleventh to eighteenth aspects, wherein at least one of a thickness of the lead-free solder with which the first surface is coated and a thickness of the lead-free solder with which the second surface is coated is 20 to 100 µm.

[0046] A semiconductor package according to a twentieth aspect of the embodiment is the semiconductor package according to any one of the eleventh to nineteenth aspects, wherein at least one of a ratio of thicknesses of the base material and the lead-free solder with which the first surface is coated and a ratio of thicknesses of the base material and the lead-free solder with which the second surface is coated is 2:1 to 10:1.

[0047] A semiconductor package according to a twenty-first aspect of the embodiment is the semiconductor package according to any one of the eleventh to twentieth aspects, wherein a melting point of the lead-free solder is 210°C or higher. The melting point of the lead-free solder may be 230°C or higher.

[0048] According to such an aspect, even when the temperature of the layered bonding material reaches high temperature equal to or higher than 200°C because of a rise in an operating temperature of the semiconductor device, the lead-free solder included in the layered bonding material can be prevented from melting to cause a breakdown.

[0049] A power module according to a twenty-second aspect of the embodiment includes: a substrate; a power semiconductor device disposed on the substrate; and a layered bonding material disposed between the substrate and the power semiconductor device and bonding the substrate and the power semiconductor device, wherein, in the layered bonding material, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K or less, and a first surface and a second surface of the base material are coated with lead-free solder.

[0050] When the present inventors actually performed verification with a cooling and heating cycle test, it was found that, according to such an aspect, it is possible to relax a distortion that occurs in a bonding section, in particular, under a high-temperature environment and achieve high reliability. According to the idea of the present inventors, the coefficient of linear expansion of the base material included in the layered bonding material is present in the middle between a coefficient of linear expansion of the semiconductor device and a coefficient of linear expansion of the substrate and is balanced. Therefore, it is considered possible to relax a distortion that occurs in the bonding section due to a CTE difference between the semiconductor device and the substrate, in particular, under a high-temperature environment.

[0051] A power module according to a twenty-third aspect of the embodiment includes: a substrate; a power semiconductor device disposed on the substrate; a first layered bonding material disposed between the substrate and the power semiconductor device and bonding the substrate and the power semiconductor device; a heat radiating section disposed on an opposite side of the power semiconductor device on the substrate; and a second layered bonding material disposed between the substrate and the heat radiating section and bonding the substrate and the heat radiating section, wherein, in at least one of the first layered bonding material and the second layered bonding material, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K or less, and a first surface and a second surface of the base material are coated with lead-free solder.

[0052] When the present inventors actually performed verification with a cooling and heating cycle test, it was found that, according to such an aspect, it is possible to relax a distortion that occurs in a bonding section, in particular, under a high-temperature environment and achieve high reliability. According to the idea of the present inventors, the coefficient of linear expansion of the base material included in the layered bonding material is present in the middle between a coefficient of linear expansion of the semiconductor device and a coefficient of linear expansion of a material of the substrate and the heat radiating section and is balanced. Therefore, it is considered possible to relax a distortion that occurs in the bonding section due to a CTE difference between the semiconductor device and the substrate, in particular, under a high-temperature environment.

[0053] A power module according to a twenty-fourth aspect of the embodiment is the power module according to the twenty-second or twenty-third aspect, wherein the coefficient of linear expansion of the base material is 5.9 to 14.4 ppm/K.

[0054] When the present inventors actually performed verification with a cooling and heating cycle test, it was found that, according to such an aspect, it is possible to relax a distortion that occurs in a bonding section on the semiconductor device side, in particular, under a high-temperature environment and achieve high reliability.

[0055] A power module according to a twenty-fifth aspect of the embodiment is the power module according to any one of the twenty-second to twenty-fourth aspects, wherein the coefficient of linear expansion of the base material is 7.0 to 11.6 ppm/K.

[0056] When the present inventors actually performed verification with the cooling and heating cycle test, it was found that, according to such an aspect, an effect of relaxing a distortion that occurs in a bonding section on the substrate side is higher and it is possible to achieve higher reliability.

[0057] A power module according to a twenty-sixth aspect of the embodiment is the power module according to any one of the twenty-second to twenty-fifth aspects, wherein the base material is made of any one of a Cu-W-based material, a Cu-Mo-based material, a layered material of the Cu-W-based material and the Cu-Mo-based material, a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu-W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu-Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu-W-based material and the Cu-Mo-based material.

[0058] According to such an aspect, since the base material has high thermal conductivity, it is possible to prevent an excessive temperature rise in the bonding section, a thermal distortion itself that occurs in the bonding section is reduced, and, as a result, this more advantageously acts on the extension of the life of a product.

[0059] A power module according to a twenty-seventh aspect of the embodiment is the power module according to any one of the twenty-second to twenty-sixth aspects, wherein a Cu content of the base material is 60% or lower.

[0060] According to such an aspect, since the coefficient of linear expansion of the base material included in the layered bonding material is lower, it is possible to further relax a distortion that occurs in the bonding section due to the CTE difference, in particular, under a high-temperature environment.

[0061] A power module according to a twenty-eighth aspect of the embodiment is the power module according to any one of the twenty-second to twenty-seventh aspects, wherein a Cu content of the base material is 15% or higher.

[0062] According to such an aspect, since the thermal conductivity of the base material included in the layered bonding material is further improved, a thermal distortion itself that occurs in the bonding section can be further reduced.

[0063] A power module according to a twenty-ninth aspect of the embodiment is the power module according to any one of the twenty-second to twenty-eighth aspects, wherein an interface between at least one of the first surface and the second surface of the base material and the lead-free solder is undercoated with Ni and Sn in order from the base material side.

[0064] According to such an aspect, it is possible to improve adhesion of the base material included in the layered bonding material and the lead-free solder.

[0065] A power module according to a thirtieth aspect of the embodiment is the power module according to any one of the twenty-second to twenty-ninth aspects, wherein at least one of a thickness of the lead-free solder with which the first surface is coated and a thickness of the lead-free solder with which the second surface is coated is 20 to 100 µm.

[0066] A power module according to a thirty-first aspect of the embodiment is the power module according to any one of the twenty-second to thirtieth aspects, wherein at least one of a ratio of thicknesses of the base material and the lead-free solder with which the first surface is coated and a ratio of thicknesses of the base material and the lead-free solder with which the second surface is coated is 2:1 to 10:1.

[0067] A power module according to a thirty-second aspect of the embodiment is the power module according to any one of the twenty-second to thirty-first aspects, wherein a melting point of the lead-free solder is 210°C or higher. The melting point of the lead-free solder may be 230°C or higher.

[0068] According to such an aspect, even when the temperature of the layered bonding material reaches high temperature equal to or higher than 200°C because of a rise in an operating temperature of the power semiconductor device, the lead-free solder included in the layered bonding material can be prevented from melting to cause a breakdown.

[0069] A specific example of the embodiment is explained in detail below with reference to the accompanying drawings. Note that, in the following explanation and the drawings referred to in the following explanation, the same reference numerals and signs are used for portions that can be configured the same. Redundant explanation of the portions is omitted.

(Layered bonding material)



[0070] Figure 1 is a longitudinal sectional view showing a schematic configuration of a layered bonding material 10 according to the embodiment.

[0071] As shown in Figure 1, the layered bonding material 10 includes a base material 11 and pieces of lead-free solder 12a and 12b with which a first surface and a second surface of the base material 11 are coated.

[0072] Of the layered bonding material 10, the base material 11 is made of a material having a coefficient of linear expansion of 5.5 to 15.5 ppm/K. The base material 11 more preferably has a coefficient of linear expansion of 5.9 to 14.4 ppm/K and particularly preferably has a coefficient of linear expansion of 7.0 to 11.6 ppm/K. Specifically, for example, a Cu-W-based material or a Cu-Mo-based material is used as the base material 11. A layered material of the Cu-W-based material and the Cu-Mo-based material may be used as the base material 11. As the base material 11, any one of a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu-W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu-Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu-W-based material and the Cu-Mo-based material may be used. When the base material 11 is made of the composite material, a ratio of thicknesses of the Cu-Mo-based material, the Cu-W-based material, or the layered material of the Cu-W-based material and the Cu-Mo-based material located in the center and the Cu-based material stacked on one surface thereof may be, for example, 4:1 to 1:2.

[0073] Note that, in this specification, the Cu-W-based material means a material having the largest contents of Cu and W in a mass ratio among elements constituting the material. A total of the contents of Cu and W is preferably 50% or higher in a mass ratio with respect to the entire material. The Cu-W-based material may include elements other than Cu and W as impurities. The Cu-Mo-based material means a material having the largest contents of Cu and Mo in a mass ratio among elements constituting the material. A total of the contents of Cu and Mo is preferably 50% or higher in a mass ratio with respect to the entire material. The Cu-Mo-based material may include elements other than Cu and Mo as impurities.

[0074] Since a coefficient of thermal expansion increases when the Cu content of the base material 11 increases, the Cu content of the base material 11 is preferably 60% or lower in a mass ratio.

[0075] Since thermal conductivity is improved when the Cu content of the base material 11 increases, the Cu content of the base material 11 is preferably 15% or higher in a mass ratio.

[0076]  As shown in Figure 1, a first surface (in an illustrated example, the upper surface) and a second surface (in the illustrated example, the lower surface) of the base material 11 are coated with the pieces of lead-free solder 12a and 12b, respectively.

[0077] The material of the pieces of lead-free solder 12a and 12b is not particularly limited. For example, an SnAgCu-based alloy or the like may be used. Note that the SnAgCu-based alloy means an alloy having the largest contents of Sn, Ag, and Cu in a mass ratio among elements constituting the alloy. A total of contents of Sn, Ag, and Cu is preferably 50% or higher in a mass ratio with respect to the entire alloy. The SnAgCu-based alloy may include elements other than Sn, Ag, and Cu as impurities. Specifically, for example, SAC305 (Sn3.0Ag0.5Cu) may be used as the pieces of lead-free solder 12a and 12b.

[0078] The lead-free solder 12a with which the first surface is coated and the lead-free solder 12b with which the second surface is coated may have the same composition or may have compositions different from each other.

[0079] A melting point of the pieces of lead-free solder 12a and 12b is preferably 210°C or higher and may be 230°C or higher, may be 240°C or higher, or may be 250°C or higher.

[0080] At least one of the thickness of the lead-free solder 12a with which the first surface is coated and the thickness of the lead-free solder 12b with which the second surface is coated is preferably 20 to 100 µm. Both of the thickness of the lead-free solder 12a with which the first surface is coated and the thickness of the lead-free solder 12b with which the second surface is coated may be 20 to 100 µm.

[0081] At least one of a ratio of the thicknesses of the base material 11 and the lead-free solder 12a with which the first surface is coated and a ratio of the thicknesses of the base material 11 and the lead-free solder 12b with which the second surface is coated is preferably 2:1 to 10:1. Both of the ratio of the thicknesses of the base material 11 and the lead-free solder 12a with which the first surface is coated and the ratio of the thicknesses of the base material 11 and the lead-free solder 12b with which the second surface is coated may be 2:1 to 10:1.

[0082] The coating of the pieces of lead-free solder 12a and 12b is performed by an existing method such as plating. The thicknesses of the coating may be adjusted by cladding.

[0083] As shown in Figure 1, an interface between at least one of the first surface and the second surface of the base material 11 and the lead-free solder 12a or 12b is preferably undercoated (for example, plating) with Ni and Sn in order from the base material 11 side. Since an interface between the base material 11 and Sn is undercoated with Ni, diffusion of Sn to the base material 11 side can be suppressed. Since Sn is undercoated on Ni, it is easy to perform the coating of the pieces of lead-free solder 12a and 12b. Therefore, adhesion of the base material 11 and the pieces of lead-free solder 12a and 12b is improved. Interfaces between both of the first surface and the second surface of the base material 11 and the pieces of lead-free solder 12a and 12b may be undercoated (for example, plating) with Ni and Sn in order from the base material 11 side.

[0084] In the illustrated example, a first undercoat layer 13a by the undercoat treatment is formed between the first surface of the base material 11 and the lead-free solder 12a. A second undercoat layer 13b by the undercoat treatment is formed between the second surface of the base material 11 and the lead-free solder 12b.

(Semiconductor package, power module)



[0085] Subsequently, a semiconductor package 20 according to the embodiment is explained with reference to Figure 2. Note that, in this specification, when a semiconductor device 22 included in the semiconductor package 20 is a power semiconductor device, such a semiconductor package 20 (that is, the power semiconductor package) is sometimes referred to as power module.

[0086] Figure 2 is a longitudinal sectional view showing a schematic configuration of the semiconductor package 20 according to the embodiment.

[0087] As shown in Figure 2, the semiconductor package 20 includes a substrate 21, a semiconductor device 22 disposed on the substrate 21, and a first layered bonding material 10a that bonds the substrate 21 and the semiconductor device 22.

[0088] The configuration of the first layered bonding material 10a is the same as the configuration of the layered bonding material 10 according to the embodiment explained above. Explanation of the configuration of the first layered bonding material 10a is omitted.

[0089] A type of the substrate 21 is not particularly limited. For example, a DBC (Direct Bonded Copper) substrate or a DBA (Direct Bonded Aluminum) substrate is used.

[0090] As shown in Figure 2, the semiconductor device 22 is disposed on the substrate 21 via the first layered bonding material 10a. The substrate 21 and the semiconductor device 22 are bonded by the first layered bonding material 10a.

[0091] A type of the semiconductor device 22 is not particularly limited. For example, a power semiconductor device such as a power transistor or a power diode is used. In this case, even if the temperature of the first layered bonding material 10a reaches high temperature equal to or higher than 200°C because of a rise in an operating temperature of the semiconductor device 22, if a melting point of the pieces of lead-free solder 12a and 12b is 210°C or higher in the first layered bonding material 10a, the pieces of lead-free solder 12a and 12b can be prevented from melting to cause a breakdown.

[0092] In this embodiment, as shown in Figure 2, the semiconductor package 20 further includes a heat radiating section 23 disposed on the substrate 21 and a second layered bonding material 10b that bonds the substrate 21 and the heat radiating section 23.

[0093]  The configuration of the second layered bonding material 10b is the same as the configuration of the layered bonding material 10 according to the embodiment explained above. Explanation of the configuration of the second layered bonding material 10b is omitted.

[0094] As shown in Figure 2, the heat radiating section 23 is disposed on the opposite side of the semiconductor device 22 on the substrate 21 via the second layered bonding material 10b. The substrate 21 and the heat radiating section 23 are bonded by the second layered bonding material 10b.

[0095] In an example shown in Figure 2, the heat radiating section 23 includes a heat radiating plate 23a and a heat radiating fin 23b closely attached and fixed to one surface (in the illustrated example, the lower surface) of the heat radiating plate 23a. The other surface (in the illustrated example, the upper surface) of the heat radiating plate 23a is closely attached and fixed to the second layered bonding material 10b. As the material of the heat radiating section 23, a material having high thermal conductivity is used. For example, CuMo or CuW is used.

[0096] When the present inventors actually performed verification with a cooling and heating cycle test explained below, it was found that, according to this embodiment explained above, it is possible to relax a distortion that occurs in a bonding section, in particular, under a high-temperature environment and achieve high reliability. According to the idea of the present inventors, a coefficient of linear expansion of the base material 11 included in the first layered bonding material 10a and the second layered bonding material 10b is present in the middle between a coefficient of linear expansion of the semiconductor device 22 and a coefficient of linear expansion of the material of the substrate 21 and the heat radiating section 23 and is balanced. Therefore, it is considered possible to relax a distortion that occurs in a bonding section between the semiconductor device 22 and the substrate 21 and a bonding section between the substrate 21 and the heat radiating section 23 because of a CTE difference between the semiconductor device 22 and the substrate 21 and the heat radiating section 23, in particular, under a high-temperature environment.

[0097] According to this embodiment, the base material 11 included in the first layered bonding material 10a and the second layered bonding material 10b is made of any one of a Cu-W-based material, a Cu-Mo-based material, a layered material of the Cu-W-based material and the Cu-Mo-based material, a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu-W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu-Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu-W-based material and the Cu-Mo-based material. Since the base material 11 has high thermal conductivity, it is possible to prevent an excessive temperature rise in the bonding section, a thermal distortion itself that occurs in the bonding section is reduced, and, as a result, this more advantageously acts on the extension of the life of a product of the semiconductor package 20.

[0098] According to this embodiment, a Cu content of the base material 11 included in the first layered bonding material 10a and the second layered bonding material 10b is 60% or lower. Therefore, the coefficient of linear expansion of the base material 11 is lower. It is possible to further relax a distortion that occurs in the bonding section due to the CTE difference, in particular, under a high-temperature environment.

[0099] According to this embodiment, a Cu content of the base material 11 included in the first layered bonding material 10a and the second layered bonding material 10b is 15% or higher. Therefore, the thermal conductivity of the base material 11 is improved and a thermal distortion itself that occurs in the bonding section can be further reduced.

[0100] According to this embodiment, in the first layered bonding material 10a and the second layered bonding material 10b, the interface between at least one of the first surface and the second surface of the base material 11 and the lead-free solder 12a or 12b is undercoated with Ni and Sn in order from the base material 11 side. Therefore, it is possible to improve adhesion of the base material 11 and the pieces of lead-free solder 12a and 12b.

[0101] According to this embodiment, in the first layered bonding material 10a and the second layered bonding material 10b, the melting point of the pieces of lead-free solder 12a and 12b is 210°C or higher. Therefore, even when the temperature of the first layered bonding material 10a and the second layered bonding material 10b reaches high temperature equal to or higher than 200°C because of a rise in an operating temperature of the semiconductor device 22, the pieces of lead-free solder 12a and 12b included in the first layered bonding material 10a and the second layered bonding material 10b can be prevented from melting to cause a breakdown.

(Examples)



[0102] Specific examples according to this embodiment are explained.

[0103] As shown in Figure 3 and Figure 4, the present inventors prepared bonding materials (6.5 mm square) of examples 1 to 20 and comparative examples 1 to 7 and created samples obtained by bonding a substrate (20 mm square; a Cu block having a thickness of 2 mm) and a semiconductor device (5.5 mm square; an Si chip having a thickness of 0.4 mm) using the bonding materials. Subsequently, the present inventors carried out a cooling and heating cycle test for the samples using a cold impact device TSA-71L-A (manufactured by Espec Corporation) under a test condition of -40°C to +150°C (exposure times of 0.5 h). The present inventors performed SAT observation for the samples at points in time before the cooling and heating cycle test, after 250 cycles, after 500 cycles, and after 1000 cycles from each of an Si chip side and a Cu base side using an ultrasonic video device FineSAT FAS200II (manufactured by Hitachi Kenki Fine Tech Co., Ltd.), calculated a defect part area ratio of a bonding section from an SAT observation image, and evaluated a change ratio of the defect part area ratio (a defect part change ratio). The defect part change ratio was calculated by the following Expression (1) .

[0104] Defect part change ratio (%) = {(defect part area ratio after 1000 cycles - defect part area ratio before the cooling and heating cycle test) / defect part area ratio after 1000 cycles} × 100 Expression (1)

[0105] A row of the "defect part change ratio" in Figure 3 and Figure 4 indicates a test result. In Figure 3 and Figure 4, the defect part change ratio of "" indicates that the defect part change ratio on the Si chip side is lower than 50% and the defect part change ratio on the Cu base side is lower than 99.5%. The defect part change ratio of "∘" indicates that the defect part change ratio on the Si chip side is lower than 50% but the defect part change ratio on the Cu base side is 99.5% or higher. The defect part change ratio of "×" indicates that the defect part change ratio on the Si chip side is 50% or higher.

[0106] Figure 5 is a bar graph showing the defect part change ratios of the examples 1 and 2 and the comparative examples 1 and 2 in comparison. Figure 6 is a bar graph showing the defect part change ratios of the examples 3 and 4 and the comparative example 3 in comparison. Figure 7 is a bar graph showing the defect part change ratios of the examples 5 and 6 and the comparative examples 4 to 5 in comparison.

[0107] As shown in Figure 3 to Figure 7, in all of the examples 1 to 20, it was confirmed that the defect part change ratio on the Si chip side after 1000 cycles was lower than 50%, a distortion that occurred in a bonding section on the Si chip side, in particular, under a high-temperature environment was successfully relaxed, and reliability was high. On the other hand, as shown in Figure 4, in the comparative examples 1 to 7, it was confirmed that the defect part change ratio on the Si chip side after 1000 cycles was 50% or higher (in the comparative examples 1 to 5, 80% or higher), a distortion that occurred in the bonding section on the Si chip side, in particular, under a high-temperature environment was not successfully relaxed, and reliability was low. In the examples 1 to 20, a coefficient of linear expansion of a base material is 5.9 to 14.4 ppm/K. On the other hand, in the comparative examples 1 and 4, the base material is absent, in the comparative examples 2, 3, and 5, the coefficient of linear expansion of the base material is as high as 17.1 ppm/K, and, in the comparative examples 6 and 7, the coefficient of linear expansion of the base material is as low as 4.6 to 5.2 ppm/K. Therefore, in a layered bonding material in which a first surface and a second surface of a base material are coated with lead-free solder, if a coefficient of linear expansion of the base material is 5.5 (the middle of 5.9 and 4.6) to 15.5 (the middle of 14.4 and 17.1) ppm/K, more preferably, 5.9 to 14.4 ppm/K, the defect part change ratio on the Si chip side after 1000 cycles is lower than 50%. It can be considered that it is possible to relax, in particular, a distortion that occurs in the bonding section on the Si chip side and achieve high reliability.

[0108] As shown in Figure 3 and Figure 4, in the examples 1 to 6, 9 to 10, and 12 to 18, it was confirmed that the defect part change ratio on the Cu base side was lower than 99.5% and a relaxing effect for a distortion that occurred in the bonding section on the Cu base side was higher. Whereas the coefficient of linear expansion of the base material is 7.0 to 11.6 ppm/K in the examples 1 to 6, 9 to 10, and 12 to 18, the coefficient of linear expansion of the base material is 5.9 to 6.8 ppm/K in the examples 7 to 8 and 11 and the coefficient of linear expansion of the base material is 13.8 to 14.4 ppm/K in the examples 19 and 20. Accordingly, in the layered bonding material in which the first surface and the second surface of the base material are coated with the lead-free solder, in order to have a higher relaxing effect for a distortion that occurs in the bonding section and achieve higher reliability, the coefficient of linear expansion of the base material is considered to be more preferably 7.0 to 11.6 ppm/K.

[0109] The embodiment and the modifications are explained above by illustration. However, the scope of the present technique is not limited to the embodiment and the modifications and can be changed and modified according to a purpose within the scope described in claims. The embodiment and the modifications can be combined as appropriate in a range in which processing contents do not contradict.


Claims

1. A layered bonding material, wherein a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K, and a first surface and a second surface of the base material are coated with lead-free solder.
 
2. The layered bonding material according to claim 1,
wherein the coefficient of linear expansion of the base material is 5.9 to 14.4 ppm/K.
 
3. The layered bonding material according to claim 1 or 2, wherein the coefficient of linear expansion of the base material is 7.0 to 11.6 ppm/K.
 
4. The layered bonding material according to claim 1, wherein the base material is made of any one of a Cu-W-based material, a Cu-Mo-based material, a layered material of the Cu-W-based material and the Cu-Mo-based material, a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu-W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu-Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu-W-based material and the Cu-Mo-based material.
 
5. The layered bonding material according to any one of claims 1 to 4, wherein a Cu content of the base material is 60% or lower.
 
6. The layered bonding material according to any one of claims 1 to 5, wherein a Cu content of the base material is 15% or higher.
 
7. The layered bonding material according to any one of claims 1 to 6, wherein an interface between at least one of the first surface and the second surface of the base material and the lead-free solder is undercoated with Ni and Sn in order from the base material side.
 
8. The layered bonding material according to any one of claims 1 to 7, wherein at least one of a thickness of the lead-free solder with which the first surface is coated and a thickness of the lead-free solder with which the second surface is coated is 20 to 100 µm.
 
9. The layered bonding material according to any one of claims 1 to 8, wherein at least one of a ratio of thicknesses of the base material and the lead-free solder with which the first surface is coated and a ratio of thicknesses of the base material and the lead-free solder with which the second surface is coated is 2:1 to 10:1.
 
10. The layered bonding material according to any one of claims 1 to 9, wherein a melting point of the lead-free solder is 210°C or higher.
 
11. The layered bonding material according to claim 10, wherein the melting point of the lead-free solder is 230°C or higher.
 
12. A semiconductor package comprising:

a substrate;

a semiconductor device disposed on the substrate; and

a layered bonding material disposed between the substrate and the semiconductor device and bonding the substrate and the semiconductor device, wherein

in the layered bonding material, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K, and a first surface and a second surface of the base material are coated with lead-free solder.


 
13. A semiconductor package comprising:

a substrate;

a semiconductor device disposed on the substrate;

a first layered bonding material disposed between the substrate and the semiconductor device and bonding the substrate and the semiconductor device;

a heat radiating section disposed on an opposite side of the semiconductor device on the substrate; and

a second layered bonding material disposed between the substrate and the heat radiating section and bonding the substrate and the heat radiating section, wherein

in at least one of the first layered bonding material and the second layered bonding material, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K, and a first surface and a second surface of the base material are coated with lead-free solder.


 
14. The semiconductor package according to claim 12 or 13, wherein the coefficient of linear expansion of the base material is 5.9 to 14.4 ppm/K.
 
15. The semiconductor package according to any one of claims 12 to 14, wherein the coefficient of linear expansion of the base material is 7.0 to 11.6 ppm/K.
 
16. The semiconductor package according to any one of claims 12 to 15, wherein the base material is made of any one of a Cu-W-based material, a Cu-Mo-based material, a layered material of the Cu-W-based material and the Cu-Mo-based material, a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu-W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu-Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu-W-based material and the Cu-Mo-based material.
 
17. The semiconductor package according to any one of claims 12 to 16, wherein a Cu content of the base material is 60% or lower.
 
18. The semiconductor package according to any one of claims 12 to 17, wherein a Cu content of the base material is 15% or higher.
 
19. The semiconductor package according to any one of claims 12 to 18, wherein an interface between at least one of the first surface and the second surface of the base material and the lead-free solder is undercoated with Ni and Sn in order from the base material side.
 
20. The semiconductor package according to any one of claims 12 to 19, wherein at least one of a thickness of the lead-free solder with which the first surface is coated and a thickness of the lead-free solder with which the second surface is coated is 20 to 100 µm.
 
21. The semiconductor package according to any one of claims 12 to 20, wherein at least one of a ratio of thicknesses of the base material and the lead-free solder with which the first surface is coated and a ratio of thicknesses of the base material and the lead-free solder with which the second surface is coated is 2:1 to 10:1.
 
22. The semiconductor package according to any one of claims 12 to 21, wherein a melting point of the lead-free solder is 210°C or higher.
 
23. The semiconductor package according to claim 22, wherein the melting point of the lead-free solder is 230°C or higher.
 
24. A power module comprising:

a substrate;

a power semiconductor device disposed on the substrate; and

a layered bonding material disposed between the substrate and the power semiconductor device and bonding the substrate and the power semiconductor device, wherein

in the layered bonding material, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K, and a first surface and a second surface of the base material are coated with lead-free solder.


 
25. A power module comprising:

a substrate;

a power semiconductor device disposed on the substrate;

a first layered bonding material disposed between the substrate and the power semiconductor device and bonding the substrate and the power semiconductor device;

a heat radiating section disposed on an opposite side of the power semiconductor device on the substrate; and

a second layered bonding material disposed between the substrate and the heat radiating section and bonding the substrate and the heat radiating section, wherein

in at least one of the first layered bonding material and the second layered bonding material, a coefficient of linear expansion of a base material is 5.5 to 15.5 ppm/K, and a first surface and a second surface of the base material are coated with lead-free solder.


 
26. The power module according to claim 24 or 25, wherein the coefficient of linear expansion of the base material is 5.9 to 14.4 ppm/K.
 
27.  The power module according to any one of claims 24 to 26, wherein the coefficient of linear expansion of the base material is 7.0 to 11.6 ppm/K.
 
28. The power module according to any one of claims 24 to 27, wherein the base material is made of any one of a Cu-W-based material, a Cu-Mo-based material, a layered material of the Cu-W-based material and the Cu-Mo-based material, a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu-W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu-Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu-W-based material and the Cu-Mo-based material.
 
29. The power module according to any one of claims 24 to 28, wherein a Cu content of the base material is 60% or lower.
 
30. The power module according to any one of claims 24 to 29, wherein a Cu content of the base material is 15% or higher.
 
31.  The power module according to any one of claims 24 to 30, wherein an interface between at least one of the first surface and the second surface of the base material and the lead-free solder is undercoated with Ni and Sn in order from the base material side.
 
32. The power module according to any one of claims 24 to 31, wherein at least one of a thickness of the lead-free solder with which the first surface is coated and a thickness of the lead-free solder with which the second surface is coated is 20 to 100 µm.
 
33. The power module according to any one of claims 24 to 32, wherein at least one of a ratio of thicknesses of the base material and the lead-free solder with which the first surface is coated and a ratio of thicknesses of the base material and the lead-free solder with which the second surface is coated is 2:1 to 10:1.
 
34. The power module according to any one of claims 24 to 33, wherein a melting point of the lead-free solder is 210°C or higher.
 
35. The power module according to claim 34, wherein the melting point of the lead-free solder is 230°C or higher.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description