SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

(19)

(11)

EP 4 187 538 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	13.09.2023 Bulletin 2023/37

(43)	Date of publication A2:
	31.05.2023 Bulletin 2023/22

(21)	Application number: 22208785.0

(22)	Date of filing: 22.11.2022

(51)

International Patent Classification (IPC):

G11C 7/10^(2006.01)

G11C 7/22^(2006.01)

(52)	Cooperative Patent Classification (CPC):
	G11C 7/1051; G11C 7/1066; G11C 7/1063; G11C 7/1078; G11C 7/1093; G11C 7/109; G11C 7/222; G11C 7/22; G11C 7/1015; G11C 7/1045; G11C 7/1084; G11C 7/1057; G11C 5/04

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA
	Designated Validation States:
	KH MA MD TN

(30)

Priority:

25.11.2021 KR 20210164104
03.03.2022 KR 20220027356

(71)	Applicant: Samsung Electronics Co., Ltd.
	Gyeonggi-do 16677 (KR)

(72)	Inventors:
	JO, Youngmin 16677 Suwon-si, Gyeonggi-do (KR) KIM, Tongsung 16677 Suwon-si, Gyeonggi-do (KR) YOON, Chiweon 16677 Suwon-si, Gyeonggi-do (KR) JEONG, Byunghoon 16677 Suwon-si, Gyeonggi-do (KR)

(74)	Representative: Kuhnen & Wacker Patent- und Rechtsanwaltsbüro PartG mbB
	Prinz-Ludwig-Straße 40A 85354 Freising 85354 Freising (DE)

(54)	SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

(57) A memory system (10) includes a plurality of memory devices (NVM11-NVM14, NVM21-NVM24), each connected to one of a plurality of internal channels (CHI1, CHI2) respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller (110) connected to an external channel (CHO) including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit (130) connecting the external channel (CHO) to each of the internal channels (CHI1, CHI2). The interface circuit (130) is configured to perform channel conversion by serializing a parallel data signal received from the controller (110) through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

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