%PDF-1.4
%
59 0 obj
<>/PageMode/UseOutlines/Outlines 79 0 R/Metadata 54 0 R/Pages 53 0 R/OpenAction 60 0 R/StructTreeRoot 4 0 R/Type/Catalog/OutputIntents 55 0 R>>
endobj
79 0 obj
<>
endobj
54 0 obj
<>stream
2010-12-01T14:18:08+01:00
2010-10-24T06:54:49+01:00
2010-12-01T14:18:08+01:00
Jouve S.A., EPO - Publication - KB, TaggedPDF v1.27
EP-0463978-A3-19920617
uuid:3e659c32-1dd2-11b2-0a00-844e50080100
uuid:63cb1a50-1dd2-11b2-0a00-88ef33093600
application/pdf
EP-0463978-A3-19920617
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a --> field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a --> field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.
en
European Patent Office
EP0463978
EP 0463978
G06F 12/10
Granularity hint for translation buffer in high performance processor
Granularity hint for translation buffer in high performance processor - European Patent Office - EP 0463978 A3
Granularity hint for translation buffer in high performance processor - European Patent Office - EP 0463978 A3
Adobe PDF Library 8.0
"EP0463978"; "EP 0463978"; "G06F 12/10"; "Granularity hint for translation buffer in high performance processor"
1.4
1
B
2
EP
0463978
A3
1992-06-17
91401784
1991-06-28
US
547600
1990-06-29
G06F 12/10
DIGITAL EQUIPMENT CORPORATION
Sites, Richard L.
Witek, Richard T.
Lhoste, Catherine et al
Granularity hint for translation buffer in high performance processor
Granularitätshinweis in Übersetzungspuffer eines Prozessors
Granularity hint for translation buffer in high performance processor
Indicateur de granularité pour tampon de traduction dans un processeur
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a --> field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.
bibliography
1
1
search-report
2
1
abstract
1
1
http://www.epo.org/patent-bibliographic-data/1.0/
patent
Patent Bibliographic Data Schema V. 1.0
external
Publication
DocId
Contains country code, publication number/date, correction code, and kind of the published
patent document
external
InternationalPublication
DocId
Contains country code, publication number/date, and kind of the international published patent
document
external
Application
DocId
Contains number and filing date of the patent document
external
InternationalApplication
DocId
Contains number and filing date of the international patent document
external
Priority
Bag DocId
Contains list of priorities (country code, publication number and date) of the patent
document
external
Classification
Bag Text
Contains list of Patent Classification symbols of the patent document - XML ST36 element:
classification-ipcr/text, or B511, B512 - See WIPO ST8 for content structure description
external
Applicant
Bag Text
Contains list of applicants of the patent document
external
Inventor
Bag Text
Contains list of inventors of the patent document
external
Proprietor
Bag Text
Contains list of proprietors of the patent document
external
Representative
Bag Text
Contains list of representatives of the patent document
external
Title
Lang Alt
Contains title or an alternative list of titles of the patent document - XML ST36 element: B541
(title language) and B542 - default value depends on the value of the attribute @lang in the element ep-patentdocument
external
Abstract
Seq Text
Contains abstract or an ordered list of abstracts of the patent document - XML ST36 element:
abstract/@lang and abstract/p - first abstract in the ordered list depends on the value of the attribute @lang in the element ep-patent-document
external
TotalNumberOfPages
Real
Total number of pages
external
DocumentStructure
Seq Bookmark
Contains an ordered list of bookmark-related data (name, number of the first page, number of
pages)
DocId
http://www.epo.org/patent-bibliographic-data/1.0/
patent
Provides a structure for document identification related data
CountryCode
Text
Country Code - XML ST36 element:
- B190 for a publication or B871/ctry for an international publication
- B330/ctry for a priority
Number
Text
Publication or Application or Priority Number - XML ST36 element:
- B110 for a publication or B871/dnum/pnum for an international publication
- B210 for an application or B861/dnum/anum for an international application
- B310 for a priority
KindCode
Text
Kind Code - XML ST36 element: B130 for a publication or B871/kind for an international publication
CorrectionCode
Text
Correction Code - XML ST36 element: B151+B132EP - See WIPO ST50 for correction code definition
Date
Date
Publication or Application or Priority Date - XML ST36 element:
- B140/date for a publication or B871/date for an international publication
- B220/date for an application or B861/date for an international application
- B320/date for a priority
Bookmark
http://www.epo.org/patent-bibliographic-data/1.0/
patent
Provides a structure for describing bookmarks of a patent document
DocumentSection
Text
Possible values are: bibliography, abstract, description, claims, drawings, search-report, amendment
StartPage
Real
Number of the first page of a given DocumentSection
NumberOfPages
Real
Number of pages of a given DocumentSection
http://ns.adobe.com/xap/1.0/mm/
xapMM
xapMM Schema
internal
InstanceID
URI
InstanceID Property
endstream
endobj
53 0 obj
<>
endobj
60 0 obj
<>
endobj
4 0 obj
<>
endobj
55 0 obj
[<>]
endobj
56 0 obj
<>stream
HyTSwoɞc
[5laQIBHADED2mtFOE.c}088GNg9w߽ '0 ֠Jb
2y.-;!KZ ^i"L0-
@8(r;q7Ly&Qq4j|9
V)gB0iW8#8wթ8_٥ʨQQj@&A)/g>'K t;\
ӥ$պFZUn(4T%)뫔0C&Zi8bxEB;Pӓ̹Aom?W=
x- [ 0}y)7ta>jT7@tܛ`q2ʀ&6ZLĄ?_yxg)˔zçLU*uSkSeO4?c. R
߁-25 S>ӣVd`rn~Y&+`;A4 A9 =-tl`;~p Gp| [`L`< "AYA+Cb(R, *T2B-
ꇆnQt}MA0alSx k&^>0|>_',G!"F$H:R!zFQd?r9\A&GrQhE]a4zBgE#H *B=0HIpp0MxJ$D1D, VĭKĻYdE"EI2EBGt4MzNr!YK ?%_(0J:EAiQ(()ӔWT6U@P+!~mDeԴ!hӦh/']B/ҏӿ?a0nhF!X8܌kc&5S6lIa2cKMA!E#ƒdV(kel
}}Cq9
N')].uJr
wG xR^[oƜchg`>b$*~ :Eb~,m,-ݖ,Y¬*6X[ݱF=3뭷Y~dó tizf6~`{v.Ng#{}}jc1X6fm;'_9 r:8q:˜O:ϸ8uJqnv=MmR 4
n3ܣkGݯz=[==<=GTB(/S,]6*-W:#7*e^YDY}UjAyT`#D="b{ų+ʯ:!kJ4Gmt}uC%K7YVfFY.=b?SƕƩȺy
چk5%4m7lqlioZlG+Zzmzy]?uuw|"űNwW&e֥ﺱ*|j5kyݭǯg^ykEklD_p߶7Dmo꿻1ml{Mś
nLl<9O [$h՛BdҞ@iءG&vVǥ8nRĩ7u\ЭD- u`ֲK³8%yhYѹJº;.!
zpg_XQKFAǿ=ȼ:ɹ8ʷ6˶5̵5͵6ζ7ϸ9к<Ѿ?DINU\dlvۀ܊ݖޢ)߯6DScs
2F[p(@Xr4Pm8Ww)Km
endstream
endobj
5 0 obj
<>
endobj
6 0 obj
<>
endobj
7 0 obj
<>/K 7/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
8 0 obj
<>/K 8/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
9 0 obj
<>/K 9/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
10 0 obj
<>/K 10/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
11 0 obj
<>/K 11/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
12 0 obj
<>/K 12/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
13 0 obj
<>/K 13/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
14 0 obj
<>/K 0/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
15 0 obj
<>/P 50 0 R/S/P/Type/StructElem>>
endobj
16 0 obj
<>/K 0/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
17 0 obj
<>/K 1/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
18 0 obj
<>/K 2/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
19 0 obj
<>/K 3/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
20 0 obj
<>/K 4/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
21 0 obj
<>/K 5/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
22 0 obj
<>/K 6/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
23 0 obj
<>/K 7/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
24 0 obj
<>/K 8/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
25 0 obj
<>/K 9/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
26 0 obj
<>/K 10/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
27 0 obj
<>/P 49 0 R/S/P/Type/StructElem>>
endobj
28 0 obj
<>/K 11/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
29 0 obj
<>/K 12/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
30 0 obj
<>/K 13/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
31 0 obj
<>/K 14/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
32 0 obj
<>/K 15/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
33 0 obj
<>/K 16/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
34 0 obj
<>/K 17/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
35 0 obj
<>/K 18/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
36 0 obj
<>/K 19/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
37 0 obj
<>/K 20/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
38 0 obj
<>/K 1/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
39 0 obj
<>/K 21/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
40 0 obj
<>/K 22/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
41 0 obj
<>/K 23/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
42 0 obj
<>/K 24/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
43 0 obj
<>/K 25/P 50 0 R/S/P/Pg 1 0 R/Type/StructElem>>
endobj
44 0 obj
<>/K 2/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
45 0 obj
<>/K 3/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
46 0 obj
<>/K 4/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
47 0 obj
<>/K 5/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
48 0 obj
<>/K 6/P 49 0 R/S/P/Pg 61 0 R/Type/StructElem>>
endobj
49 0 obj
<>
endobj
50 0 obj
<>
endobj
61 0 obj
<>/Font<>/ProcSet[/PDF/Text/ImageB]>>/Type/Page>>
endobj
85 0 obj
<>stream
HWˎG+h t.|adY̬K0v
4Ԟb2Ɉ`_˗ln}|pwn~
?[m{[~<_w2
/%>#\OOOt0:`_