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2010-12-10T16:58:13+01:00
2010-11-02T02:39:03Z
2010-12-10T16:58:13+01:00
Jouve S.A., EPO - Publication - KB, TaggedPDF v1.27
EP-0334510-A2-19890927
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EP-0334510-A2-19890927
Methods and apparatus are set forth which facilitate continuous bit error rate monitoring at the physical (PHY) management layer in a Fiber Distributed Data Interface (FDDI), duel token ring network. The monitoring is performed using existing line status information from PHY. Simple error detection logic, in combination with an error counter and a timer, is used to detect errors during active or idle line state conditions, independent of Media Access Control (MAC) layer support.
Methods and apparatus are set forth which facilitate continuous bit error rate monitoring at the physical (PHY) management layer in a Fiber Distributed Data Interface (FDDI), duel token ring network. The monitoring is performed using existing line status information from PHY. Simple error detection logic, in combination with an error counter and a timer, is used to detect errors during active or idle line state conditions, independent of Media Access Control (MAC) layer support.
en
European Patent Office
EP0334510
EP 0334510
H04L 01/20
H04L 11/08
H04L 11/16
FDDI bit error rate tester
FDDI bit error rate tester - European Patent Office - EP 0334510 A2
FDDI bit error rate tester - European Patent Office - EP 0334510 A2
Adobe PDF Library 8.0
"EP0334510"; "EP 0334510"; "H04L 01/20"; "H04L 11/08"; "H04L 11/16"; "FDDI bit error rate tester"
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EP
0334510
A2
1989-09-27
89302328
1989-03-09
US
173325
1988-03-25
H04L 01/20
H04L 11/08
H04L 11/16
ADVANCED MICRO DEVICES, INC.
Annamalai, Kadiresan
FDDI bit error rate tester
Gerät zur Prüfung der Bitfehlerrate in einem FDDI-Netz
FDDI bit error rate tester
Testeur de taux d'erreur de bits dans un réseau FDDI
Methods and apparatus are set forth which facilitate continuous bit error rate monitoring at the physical (PHY) management layer in a Fiber Distributed Data Interface (FDDI), duel token ring network. The monitoring is performed using existing line status information from PHY. Simple error detection logic, in combination with an error counter and a timer, is used to detect errors during active or idle line state conditions, independent of Media Access Control (MAC) layer support.
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