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2010-12-01T14:48:13+01:00
2010-10-25T00:27:43+01:00
2010-12-01T14:48:13+01:00
Jouve S.A., EPO - Publication - KB, TaggedPDF v1.27
EP-0490618-A1-19920617
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EP-0490618-A1-19920617
A scrambling/descrambling circuit that may be manufactured as a CMOS arrangement in LSI format and free of constraints on the degree of the generating polynomial involved. Scrambled (or descrambled) "m" bits of data output by registers are multiplied by multiplication circuits by a factor of the generating element αm of the generating polynomial. The multiplied data are input back to the registers. The scrambled "m" bits of data are supplied to "m" exclusive-OR gates for exclusive-OR operation with input data.
A scrambling/descrambling circuit that may be manufactured as a CMOS arrangement in LSI format and free of constraints on the degree of the generating polynomial involved. Scrambled (or descrambled) "m" bits of data output by registers are multiplied by multiplication circuits by a factor of the generating element αm of the generating polynomial. The multiplied data are input back to the registers. The scrambled "m" bits of data are supplied to "m" exclusive-OR gates for exclusive-OR operation with input data.
en
European Patent Office
EP0490618
EP 0490618
H04L 25/49
G06F 07/58
Scrambling/descrambling circuit
Scrambling/descrambling circuit - European Patent Office - EP 0490618 A1
Scrambling/descrambling circuit - European Patent Office - EP 0490618 A1
Adobe PDF Library 8.0
"EP0490618"; "EP 0490618"; "H04L 25/49"; "G06F 07/58"; "Scrambling/descrambling circuit"
1.4
1
B
18
EP
0490618
A1
1992-06-17
91311444
1991-12-09
JP
40977190
1990-12-10
H04L 25/49
G06F 07/58
SONY CORPORATION
Kojima, Yuichi
Nicholls, Michael John et al
Scrambling/descrambling circuit
Schaltung zur Verwürflung/Entwürflung
Scrambling/descrambling circuit
Circuit pour le brouillage/débrouillage
A scrambling/descrambling circuit that may be manufactured as a CMOS arrangement in LSI format and free of constraints on the degree of the generating polynomial involved. Scrambled (or descrambled) "m" bits of data output by registers are multiplied by multiplication circuits by a factor of the generating element αm of the generating polynomial. The multiplied data are input back to the registers. The scrambled "m" bits of data are supplied to "m" exclusive-OR gates for exclusive-OR operation with input data.
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