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2010-12-10T17:18:14+01:00
2010-12-02T03:22:40Z
2010-12-10T17:18:14+01:00
Jouve S.A., TaggedPDF v1.27
EP-0186773-A3-19881123
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EP-0186773-A3-19881123
A soft error protection circuit is disclosed for a storage cell, such as a latch (6) having a first input/output node (8') and a second input/output node (8) which are respectively connected to a charging source (10), the first node (8') being selectively charged at least during a write interval, to represent a stored, first binary logic state for the latch. The circuit includes an insulated gate, field effect capacitor (18) having a diffusion electrode (20) connected to the second node (8) and having a gate electrode (22), for selectively loading the second node (8) with an additional capacitance. An inverter circuit (24) has an input (26) connected to the second node (8) and an output (28) connected to the gate electrode (22) of the capacitor (18), for applying a capacitance enhancing bias to the gate electrode in at least a read interval following the write interval, when the first binary logic state has been stored in the latch, to apply the additional capacitance to the second node (8). The charging source (10) supplies charge to both the first node (8') and the second node (8) at least following a soft error event which has caused the first node (8') to become at least partially discharged during the read interval. In accordance with the invention, the additional capacitance applied to the second node (8) prevents the second node from recharging as fast as the first node (8') following the soft error event, by sinking a portion of the charge supplied from the charging source (10) to the second node. In this manner, the first node will resume its previously charged condition, thereby preserving the stored logic state.
A soft error protection circuit is disclosed for a storage cell, such as a latch (6) having a first input/output node (8') and a second input/output node (8) which are respectively connected to a charging source (10), the first node (8') being selectively charged at least during a write interval, to represent a stored, first binary logic state for the latch. The circuit includes an insulated gate, field effect capacitor (18) having a diffusion electrode (20) connected to the second node (8) and having a gate electrode (22), for selectively loading the second node (8) with an additional capacitance. An inverter circuit (24) has an input (26) connected to the second node (8) and an output (28) connected to the gate electrode (22) of the capacitor (18), for applying a capacitance enhancing bias to the gate electrode in at least a read interval following the write interval, when the first binary logic state has been stored in the latch, to apply the additional capacitance to the second node (8). The charging source (10) supplies charge to both the first node (8') and the second node (8) at least following a soft error event which has caused the first node (8') to become at least partially discharged during the read interval. In accordance with the invention, the additional capacitance applied to the second node (8) prevents the second node from recharging as fast as the first node (8') following the soft error event, by sinking a portion of the charge supplied from the charging source (10) to the second node. In this manner, the first node will resume its previously charged condition, thereby preserving the stored logic state.
en
European Patent Office
EP0186773
EP 0186773
H03K 03/356
G11C 07/00
G11C 11/24
A soft error protection circuit for a latch
A soft error protection circuit for a latch - European Patent Office - EP 0186773 A3
A soft error protection circuit for a latch - European Patent Office - EP 0186773 A3
Adobe PDF Library 8.0
"EP0186773"; "EP 0186773"; "H03K 03/356"; "G11C 07/00"; "G11C 11/24"; "A soft error protection circuit for a latch"
1.4
1
B
2
EP
0186773
A3
1988-11-23
85114818
1985-11-22
US
682120
1984-12-17
H03K 03/356
G11C 07/00
G11C 11/24
International Business Machines Corporation
Bialas, John Stanley, Jr.
Daniels, Richard Joseph
Yoder, Joseph Willard
DELETED Gaugel, Heinz (DE)R. 102(1)31.12.1992
A soft error protection circuit for a latch
Schutzschaltung für eine Kippschaltung gegen Fehler des "Soft error"-Typs
A soft error protection circuit for a latch
Circuit de protection pour une bascule contre les erreurs du type "soft error"
A soft error protection circuit is disclosed for a storage cell, such as a latch (6) having a first input/output node (8') and a second input/output node (8) which are respectively connected to a charging source (10), the first node (8') being selectively charged at least during a write interval, to represent a stored, first binary logic state for the latch. The circuit includes an insulated gate, field effect capacitor (18) having a diffusion electrode (20) connected to the second node (8) and having a gate electrode (22), for selectively loading the second node (8) with an additional capacitance. An inverter circuit (24) has an input (26) connected to the second node (8) and an output (28) connected to the gate electrode (22) of the capacitor (18), for applying a capacitance enhancing bias to the gate electrode in at least a read interval following the write interval, when the first binary logic state has been stored in the latch, to apply the additional capacitance to the second node (8). The charging source (10) supplies charge to both the first node (8') and the second node (8) at least following a soft error event which has caused the first node (8') to become at least partially discharged during the read interval. In accordance with the invention, the additional capacitance applied to the second node (8) prevents the second node from recharging as fast as the first node (8') following the soft error event, by sinking a portion of the charge supplied from the charging source (10) to the second node. In this manner, the first node will resume its previously charged condition, thereby preserving the stored logic state.
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