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2010-12-11T05:53:40+01:00
2010-11-01T21:35:26Z
2010-12-11T05:53:40+01:00
Jouve S.A., EPO - Publication - KB, TaggedPDF v1.27
EP-0348240-A2-19891227
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EP-0348240-A2-19891227
A microprocessor having a on-chip redundant control unit is disclosed. This processor includes a set of data terminals, an execution unit and a data bus buffer coupled between the set of data terminals and the execution unit, and the data bus buffer fetches data on the set of data terminals in response to a first timing signal and transfers the fetched data to the execution unit in response to a second timing signal. The on-chip redundant control unit receives the fetched data and redundant information and checks the validity of the fetched data in response to the redundant information before the generation of the second timing signal, so that an effective memory access time is not prolonged.
A microprocessor having a on-chip redundant control unit is disclosed. This processor includes a set of data terminals, an execution unit and a data bus buffer coupled between the set of data terminals and the execution unit, and the data bus buffer fetches data on the set of data terminals in response to a first timing signal and transfers the fetched data to the execution unit in response to a second timing signal. The on-chip redundant control unit receives the fetched data and redundant information and checks the validity of the fetched data in response to the redundant information before the generation of the second timing signal, so that an effective memory access time is not prolonged.
en
European Patent Office
EP0348240
EP 0348240
G06F 11/10
Microprocessor equipped with parity control unit on same chip
Microprocessor equipped with parity control unit on same chip - European Patent Office - EP 0348240 A2
Microprocessor equipped with parity control unit on same chip - European Patent Office - EP 0348240 A2
Adobe PDF Library 8.0
"EP0348240"; "EP 0348240"; "G06F 11/10"; "Microprocessor equipped with parity control unit on same chip"
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1
B
13
EP
0348240
A2
1989-12-27
89306424
1989-06-23
JP
15732888
1988-06-24
G06F 11/10
NEC CORPORATION
Sato, Yoshikuni c/o NEC Corporation
Moir, Michael Christopher et al
Microprocessor equipped with parity control unit on same chip
Mit einer Paritätsteuerungseinheit auf demselben Chip bestückter Mikroprozessor
Microprocessor equipped with parity control unit on same chip
Microprocesseur équipé d'une unité de contrôle de parité sur la même pastille
A microprocessor having a on-chip redundant control unit is disclosed. This processor includes a set of data terminals, an execution unit and a data bus buffer coupled between the set of data terminals and the execution unit, and the data bus buffer fetches data on the set of data terminals in response to a first timing signal and transfers the fetched data to the execution unit in response to a second timing signal. The on-chip redundant control unit receives the fetched data and redundant information and checks the validity of the fetched data in response to the redundant information before the generation of the second timing signal, so that an effective memory access time is not prolonged.
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