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2010-12-01T14:59:36+01:00
2010-10-23T20:30:07+01:00
2010-12-01T14:59:36+01:00
Jouve S.A., EPO - Publication - KB, TaggedPDF v1.27
EP-0420268-A3-19940223
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EP-0420268-A3-19940223
A function selection circuit includes a first signal generating circuit (2) for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit (5) for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.
A function selection circuit includes a first signal generating circuit (2) for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit (5) for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.
en
European Patent Office
EP0420268
EP 0420268
G11C 08/00
G11C 07/00
Function selector circuit
Function selector circuit - European Patent Office - EP 0420268 A3
Function selector circuit - European Patent Office - EP 0420268 A3
Adobe PDF Library 8.0
"EP0420268"; "EP 0420268"; "G11C 08/00"; "G11C 07/00"; "Function selector circuit"
1.4
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EP
0420268
A3
1994-02-23
90118680
1990-09-28
JP
25466889
1989-09-29
G11C 08/00
G11C 07/00
KABUSHIKI KAISHA TOSHIBA
TOSHIBA MICRO-ELECTRONICS CORPORATION
Toda, Haruki
Ohshima, Shigeo
Ikawa, Tatsuo
Lehn, Werner, Dipl.-Ing. et al
Function selector circuit
Betriebsartenwählerschaltung
Function selector circuit
Circuit de sélection de fonction
A function selection circuit includes a first signal generating circuit (2) for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit (5) for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.
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