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2010-11-21T17:51:43Z
2010-12-10T20:53:33+01:00
Jouve S.A., EPO - Publication - KB, TaggedPDF v1.27
EP-0052982-A2-19820602
uuid:92564ede-1dd2-11b2-0a00-74c0bd090100
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EP-0052982-A2-19820602
A semiconductor memory device having a MOS transistor with a floating gate (108a, 108b) capable of storing data.The MOS transistor has an erase gate (106) which overlaps part of the floating gate (108a, 108b) with an insulating film (110) interposed therebetween. Upon application of a high voltage on the erase gate (106), the field emission is caused between the floating gate (108a, 108b) and the erase gate (106) and the charge stored on the floating gate (108a, 108b) is removed.
A semiconductor memory device having a MOS transistor with a floating gate (108a, 108b) capable of storing data.The MOS transistor has an erase gate (106) which overlaps part of the floating gate (108a, 108b) with an insulating film (110) interposed therebetween. Upon application of a high voltage on the erase gate (106), the field emission is caused between the floating gate (108a, 108b) and the erase gate (106) and the charge stored on the floating gate (108a, 108b) is removed.
en
European Patent Office
EP0052982
EP 0052982
H01L 29/60
G11C 17/00
H01L 21/82
Semiconductor memory device and method for manufacturing the same
Semiconductor memory device and method for manufacturing the same - European Patent Office - EP 0052982 A2
Semiconductor memory device and method for manufacturing the same - European Patent Office - EP 0052982 A2
Adobe PDF Library 8.0
"EP0052982"; "EP 0052982"; "H01L 29/60"; "G11C 17/00"; "H01L 21/82"; "Semiconductor memory device and method for manufacturing the same"
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0052982
A2
1982-06-02
81305349
1981-11-11
JP
16393180
1980-11-20
JP
16393280
1980-11-20
JP
16393380
1980-11-20
JP
16861680
1980-11-29
JP
16861780
1980-11-29
JP
16861880
1980-11-29
JP
16861980
1980-11-29
JP
16862080
1980-11-29
JP
18095180
1980-12-20
JP
755881
1981-01-21
JP
11978281
1981-07-30
H01L 29/60
G11C 17/00
H01L 21/82
KABUSHIKI KAISHA TOSHIBA
Masuoka, Fujio
Freed, Arthur Woolf et al
Semiconductor memory device and method for manufacturing the same
Halbleiterspeicheranordnung und Herstellungsverfahren
Semiconductor memory device and method for manufacturing the same
Dispositif semiconducteur à mémoire et procédé de fabrication
A semiconductor memory device having a MOS transistor with a floating gate (108a, 108b) capable of storing data.The MOS transistor has an erase gate (106) which overlaps part of the floating gate (108a, 108b) with an insulating film (110) interposed therebetween. Upon application of a high voltage on the erase gate (106), the field emission is caused between the floating gate (108a, 108b) and the erase gate (106) and the charge stored on the floating gate (108a, 108b) is removed.
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