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2010-10-23T21:49:46+01:00
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Jouve S.A., EPO - Publication - KB, TaggedPDF v1.27
EP-0607474-A1-19940727
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EP-0607474-A1-19940727
By reverse biasing the PN junction formed around a semiconductor element (10), the semiconductor element (10) is isolated from other elements (10) The PN junction around the semiconductor element (10) is a junction between a layer (26) surrounding the semiconductor element (10) and a layer (28) disposed outside the layer (26). Jointly with the layer constituting the semiconductor (10), the layer (26) surrounding the semiconductor element (10) forms a parasitic diode (54). The potential of the layer (18) on the semiconductor element (10) to be connected to the layer (26) surrounding the semiconductor element (10) is detected, and based on this potential, the voltage to be applied to the parasitic diode (54) is controlled so as to be constant. When the voltage to be applied to the parasitic diode (54) is lower than a threshold, the parasitic diode (54) will be in cutoff status.
By reverse biasing the PN junction formed around a semiconductor element (10), the semiconductor element (10) is isolated from other elements (10) The PN junction around the semiconductor element (10) is a junction between a layer (26) surrounding the semiconductor element (10) and a layer (28) disposed outside the layer (26). Jointly with the layer constituting the semiconductor (10), the layer (26) surrounding the semiconductor element (10) forms a parasitic diode (54). The potential of the layer (18) on the semiconductor element (10) to be connected to the layer (26) surrounding the semiconductor element (10) is detected, and based on this potential, the voltage to be applied to the parasitic diode (54) is controlled so as to be constant. When the voltage to be applied to the parasitic diode (54) is lower than a threshold, the parasitic diode (54) will be in cutoff status.
en
European Patent Office
EP0607474
EP 0607474
H01L 27/02
Semiconductor integrated circuit with layer for isolating elements in substrate
Semiconductor integrated circuit with layer for isolating elements in substrate - European Patent Office - EP 0607474 A1
Semiconductor integrated circuit with layer for isolating elements in substrate - European Patent Office - EP 0607474 A1
Adobe PDF Library 8.0
"EP0607474"; "EP 0607474"; "H01L 27/02"; "Semiconductor integrated circuit with layer for isolating elements in substrate"
1.4
1
B
12
EP
0607474
A1
1994-07-27
93100392
1993-01-12
H01L 27/02
MITSUBISHI DENKI KABUSHIKI KAISHA
Fujii, Nobuo
Mizukawa, Yosuke, c/o Mitsubishi Denki Eng. K.K.
Mitsuhashi, Yasuo, c/o Mitsubishi Denki Eng. K.K.
Pfenning, Meinig & Partner
Semiconductor integrated circuit with layer for isolating elements in substrate
Integrierte Halbleiterschaltung mit einer Schicht zur Isolation der einzelnen Elemente auf einem Substrat
Semiconductor integrated circuit with layer for isolating elements in substrate
Circuit intégré semi-conducteur avec une couche pour l'isolation d'éléments dans un substrat
By reverse biasing the PN junction formed around a semiconductor element (10), the semiconductor element (10) is isolated from other elements (10) The PN junction around the semiconductor element (10) is a junction between a layer (26) surrounding the semiconductor element (10) and a layer (28) disposed outside the layer (26). Jointly with the layer constituting the semiconductor (10), the layer (26) surrounding the semiconductor element (10) forms a parasitic diode (54). The potential of the layer (18) on the semiconductor element (10) to be connected to the layer (26) surrounding the semiconductor element (10) is detected, and based on this potential, the voltage to be applied to the parasitic diode (54) is controlled so as to be constant. When the voltage to be applied to the parasitic diode (54) is lower than a threshold, the parasitic diode (54) will be in cutoff status.
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