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Jouve S.A., EPO - Publication - KB, TaggedPDF v1.27
EP-0469834-A3-19920617
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EP-0469834-A3-19920617
A BICMOS logic circuit (160) with self-boosting immunity comprises a resistor (162), first (161) and second (168) transistors, a switching portion (163, 164), and a discharge portion (165, 166, 167, 169). The resistor (162) and first transistor (161) bias the switching portion (163, 164) to first and second reference voltages, which may be equal. The second transistor (168) is a bipolar transistor providing an output signal to a load. The switching portion (163, 164) couples the bias voltage provided by the resistor (162) and the first transistor (161 ) to the base of the second transistor (168) in response to a true result of a logic operation on at least one input signal, and couples the base of the second transistor (168) to a second power supply voltage terminal in response to a false result of the logic operation. The discharge portion (165, 166, 167, 169) couples the output signal to a logic low or pulldown voltage in response to a false result of the logic operation.
A BICMOS logic circuit (160) with self-boosting immunity comprises a resistor (162), first (161) and second (168) transistors, a switching portion (163, 164), and a discharge portion (165, 166, 167, 169). The resistor (162) and first transistor (161) bias the switching portion (163, 164) to first and second reference voltages, which may be equal. The second transistor (168) is a bipolar transistor providing an output signal to a load. The switching portion (163, 164) couples the bias voltage provided by the resistor (162) and the first transistor (161 ) to the base of the second transistor (168) in response to a true result of a logic operation on at least one input signal, and couples the base of the second transistor (168) to a second power supply voltage terminal in response to a false result of the logic operation. The discharge portion (165, 166, 167, 169) couples the output signal to a logic low or pulldown voltage in response to a false result of the logic operation.
en
European Patent Office
EP0469834
EP 0469834
H03K 19/094
H03K 19/003
A BICMOS logic circuit with self-boosting immunity and a method therefor
A BICMOS logic circuit with self-boosting immunity and a method therefor - European Patent Office - EP 0469834 A3
A BICMOS logic circuit with self-boosting immunity and a method therefor - European Patent Office - EP 0469834 A3
Adobe PDF Library 8.0
"EP0469834"; "EP 0469834"; "H03K 19/094"; "H03K 19/003"; "A BICMOS logic circuit with self-boosting immunity and a method therefor"
1.4
1
B
2
EP
0469834
A3
1992-06-17
91306941
1991-07-29
US
561400
1990-08-01
H03K 19/094
H03K 19/003
MOTOROLA, INC.
Nogle, Scott George
Lupton, Frederick et al
A BICMOS logic circuit with self-boosting immunity and a method therefor
BICMOS-logische Schaltung mit Immunität gegen Eigenanhebung und Verfahren dafür
A BICMOS logic circuit with self-boosting immunity and a method therefor
Circuit logique BICMOS avec immunité à l'auto-survoltage et méthode adaptée
A BICMOS logic circuit (160) with self-boosting immunity comprises a resistor (162), first (161) and second (168) transistors, a switching portion (163, 164), and a discharge portion (165, 166, 167, 169). The resistor (162) and first transistor (161) bias the switching portion (163, 164) to first and second reference voltages, which may be equal. The second transistor (168) is a bipolar transistor providing an output signal to a load. The switching portion (163, 164) couples the bias voltage provided by the resistor (162) and the first transistor (161 ) to the base of the second transistor (168) in response to a true result of a logic operation on at least one input signal, and couples the base of the second transistor (168) to a second power supply voltage terminal in response to a false result of the logic operation. The discharge portion (165, 166, 167, 169) couples the output signal to a logic low or pulldown voltage in response to a false result of the logic operation.
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