[0001] This invention relates to selection switches for use in networks of digital devices
with shared components, which networks in turn may share components at a higher level.
Interconnections in networks are constructed from two kinds of speed independent switches
which are known as arbitration switches or arbiters, and selection switches or selectors.
[0002] U.S. Patent Specification No. 3 962 706 discloses a digital communication network
comprising a distribution network; a memory; and an arbitration network. The distribution
network and the memory are controlled by a central controller. The distribution network
contains a number of switch units which may be considered to be selection switches,
and which receive signals from a node of a digital communication network, and transmit
those signals to one of two other nodes of said network. The distribution network
includes address switch units which, in conjunction with value switch units, direct
the received data over one of two paths according to the most significant remaining
bit in the address bit signals. The address bit tested by the address switch is deleted
from the signals.
[0003] The network shown in the above mentioned U.S. Patent Specification requires a memory
and a controller, and it is an object of the present invention to provide a selector
for a network which does not require a central controller.
[0004] The invention consists in a selector switch for receiving data signals from a node
of a digital communication network and transmitting those data signals to one of two
other nodes, said selector switch comprising: a pair of switch and buffer circuits
each adapted to receive a set of said data signals; and an address circuit to receive
said data signals preceded by an address signal specifying which of two nodes is to
be selected for subsequent transmission and to signal the corresponding one of said
switch and buffer circuits, characterised in that said selector switch further includes
a pair of end of message circuits, one for each of said switch and buffer circuits
to receive an end of message signal subsequent to the receipt of a data signal; and
a clear circuit adapted to receive an acknowledge end of message signal from the selected
node and to transmit that signal to the original node.
[0005] Trees formed from selectors provide distribution to two or more devices from one
source.
[0006] Networks employing both selectors and arbiters can be formed for the transmission
of messages among a number of devices.
[0007] The above and other objects, advantages and features of the present invention will
become more readily apparent from a review of the following specifications when taken
in conjunction with the drawings, wherein:
Figures 1A-11 are schematic diagrams of various networks in which a selector switch
according to the present invention may be used;
Figure 12 is a schematic diagram of an arbiter switch for use in a network as illustrated
in any of Figures 1A-11;
Figures 13A-D are schematic diagrams of a selector switch in accordance with the invention;
and
Figures 14D-F and H-J are schematic diagrams of various circuits employed in the present
invention (Figures 14A-C and 14G have been cancelled).
[0008] Communications in networks connected by arbiter and selector switches are in the
form of serially transmitted meassages which in the general case consist of three
parts: destination address, body, and source address. The source address originates
on the path where it is determined by the arbiter switches from the destination to
the source. The destination address selects the path through the network to the destination
and is used bit-by-bit in the selector switches along that path. In general, as a
message moves through a network, an arbiter appends a bit to indicate through which
of its two inputs a message entered and a selector removes the leading bit and selects
through which of its two outputs the message leaves. A receiving device accepts first
the message body and then the source address.
[0009] A particular bidirectional communication pattern for a set of two-terminal devices
is describable by a net of oriented, directed graphs with ternary nodes. Such a graph
is realizable in circuit form with a net of arbiters and selectors isomorphic to the
graph.
[0010] The converse of an oriented directed graph is obtained by reversing all directions
while leaving orientations unchanged. For arbiter- selector nets this requires substituting
arbiters for selectors, selectors for arbiters, device inputs for outputs, and outputs
for inputs.
[0011] Figures 1 A and 1B show two nets each permitting bidirectional communication between
two sets of two devices. In each case the net is separable into two mutually converse
nets. (The net of Figure 1 B allows four concurrent paths between the groups while
the net of Figure 1A allows only two concurrent paths).
[0012] A net is said to be self-converse if for each directed path connecting a pair of
endpoints the converse path exists. The net then has the property that the source
address of each path endpoint is the destination address from the other endpoint.
[0013] In the case of particular interest for this invention, a two-terminal system component
(e.g., store, processor, 1-0 device, or system) can be shared by two or more devices
connected via structurally similar trees of arbiter and selector switches. Figure
2 illustrates the case of four sharing devices D
j, D
2r D
3 and D
4. Figure 3 shows the general interconnection using trees of arbiters and selectors
which have the property of being mutually converse networks.
[0014] Any number of devices can be connected in this fashion. Since device identifications
are generated internally in the arbiter trees and used internally in the selector
trees, the spanning tree need not be unique; indeed, it may be determined for convenience
in placement of the switches or for minimization of the total length of the interconnecting
wires. Figures 4A and 4B show two arrangements for five devices.
[0015] In this type of network dialogs occur between a shared and sharing devices with a
sharing device initiating each dialog. The messages to the shared device have null
destination address parts since no selection is required, there being only one destination.
The source address will arrive at the shared device appended to the message body.
The reply will then use the source address as a destination address. In this way each
dialog continues, and network addresses remain anonymous, thus permitting convenient
expansion or contraction of the network.
[0016] A typical application is a set of computer terminals sharing a central processor
or database. Messages may consist of one or more characters. The central system will
maintain a queue for each terminal in which messages from that terminal are assembled.
All conflicting requests for lines will be resolved by the arbiter trees. Ordering
of messages is automatic. Thus the central system has no need for a program to poll
terminals or to represent configurations, such functions being accommodated in a decentralized
manner in the switches.
[0017] A hierarchical network similar to that familiar from telephone switching can be constructed
by using a number of networks of the type shown in Figure 3. If each network is broken
at a device, the output and input connections can be used as the input and output
of the network. The resulting two-terminal network can then be used as one of the
devices of a similar network at a higher level, thus giving a hierarchical structure.
[0018] Another class of networks of interest is those networks where each device is connected
symmetrically to some of the other devices. The networks of this form which give the
maximum number of concurrent paths are those in which the device outputs are each
connected to the root node of a selector tree and the device inputs are each connected
to the root node of an arbiter tree with the leaf nodes of the trees connected to
each other in such a manner that the network is self-converse. An example of this
type of network where each of five devices is connected to the other four is shown
in Figure 5. When the trees are homogeneous, as in Figure 5, all paths have equal
priority, and all devices can be used concurrently if there is no conflict. This type
of network is similar to conventional crossbars. If the trees used are not homogeneous,
the shorter paths through the arbiter trees will have greater priority since under
heavy loading an arbiter accepts messages alternately from its two inputs.
[0019] There are several special cases of the above class of networks which are of interest.
The network of Figure 6 connects each device to its two neighbors giving a linear
array of devices. Figure 7 shows the network associated with a device which can communicate
with any of four neighbors. This interconnection gives a two dimensional array of
devices.
[0020] The case where each of three devices is connected to the other two is shown in Figure
8. This hexagonal connector is of special interest since a number of these connectors
can be placed at the nodes of a tree and interconnected with the devices at the leaf
nodes. This type of network, an example of which is shown in Figure 9, allows communication
between any of the devices at the leaf nodes with higher priority given to those paths
with shorter addresses. The network allows the maximum number of concurrent paths
possible without redundancy, but the probability of conflict is higher than in the
networks described above with the arbiters and selectors grouped into separate trees.
The number of switches required, however, is substantially smaller for the tree of
hexagonal connectors. An example of how this type of network might be used is the
hierarchy of processors and stores shown in Figure 10.
[0021] Networks need not be constructed symmetrically or solely of one type of connector.
Figure 11 shows a network using the arbiter and selector trees of Figure 3 and the
hexagonal connector of Figure 8 to connect a number of processor and store pairs with
a global store and an input/output device.
[0022] The arbiter switch will now be described in relation to Figure 12. As illustrated
in Figure 12 the arbiter switch includes switch circuit 10, arbiter circuit 11, lock
path circuits 12 and 13, address sending circuit 14 and buffer circuit 15.
[0023] It is to be remembered that the arbiter switch receives message signals from two
different stations or nodes, determines which of the messages is to be transmitted
and then transmits that message through the arbiter switch, adding an address bit
at the end of the message to indicate which of the two sending nodes transmitted the
signal.
[0024] Switch circuit 10 receives either data signals d
oo, doll or d
io, d
il as well as the end of message signals EOM
X, (x=0, 1) from one or the other transmitting station and also returns an acknowledge
signal A
x to that station. The respective data signals are also received by . corresponding
lock path circuits 12 and 13 as will be more thoroughly described below. When such
data signals are received by a particular lock path circuit, that circuit transmits
a request signal R
xA to arbiter circuit 11 and when such a request has been accepted, arbiter circuit
11 sends a set signal S
x to switch circuit 10 to set switch circuit 10 to that path for subsequent passage
of the transmitted message to buffer 15. After the transmission of the message, address
sending circuit 14 adds an address bit to the end of the message to indicate which
previous node transmitted the message.
[0025] The selector switch will now be described in relation to Figures 13A-D. As illustrated
in Figure 13A, the selector switch includes address circuit 60, clear circuit 61,
as well as a pair of switch and buffer circuits 62 each with an end of message EOM
circuit. The function of the selector switch is to receive messages having a leading
address from another station or node and to determine to which of two stations or
nodes the message is to be transmitted depending upon the first bit in the address.
The first bit in the address sets the circuit path and the rest of the bits are transmitted
to the same node until completion of the message is detected and the circuit is cleared.
The first bit will then be removed from the address of the following message and the
selector path set accordingly.
[0026] Address circuit 60 of Figure 13A is illustrated in Figure 13B and includes two sets
of C-elements 66 and 67. C-elements 66 receive the incoming data signals do and d,
by way of NAND gates 65. NAND gates 65 also receive an inverted reset signal from
gate 68. C-elements 66 receive a reset signal and transmit set signals ASET
o and ASET, to C-elements 67. In addition, C-elements 67 receive an inverted clear
signal and transmit the set to path signals 5
0 and S, to the respective switch and buffer circuits 62 of Figure 13A. Gate 68 transmits
a reset signal to the clear circuit in the selector switch. Depending upon the state
of the set to path signals So and S
j, one of the two switch and buffer circuits will select the incoming data signals
do and d, for transmission to the next node. C-elements 66 and 67 are illustrated
in detail in Figures 141 and 14J respectively.
[0027] Clear circuit 61 of Figure 13A is illustrated in Figure 13C and includes C-element
74 which receives a gated acknowledge end of message signal AEOM
., from the node to which the message has been transmitted. C-element 74 also receives
a reset signal from address circuit 60 of Figure 13A and produces the acknowledge
end of message signal, AEOM, which is transmitted to the station or node from which
the message was received. This signal is also sent to NAND gate 75 as is the true
output of AND/NAND gate 76. The output of gate 75 is an inverted clear signal that
is transmitted to address circuit 60 of Figure 13A.
[0028] Switch and buffer circuits 62 are illustrated in Figure 13D and each serves as a
two cell queue with storage for one bit of data. It is this queue which allows pipelining
of data through the selector switches. This buffer will not be described in detail
except to say that it receives the incoming data signals do and d, as well as the
end of message signal EOM and, upon selection of particular buffer, transmits those
signals as data signals d
x0, d
x1, and end of message signal EOM
X. C-elements 70, 71, 72 and 73 are illustrated in Figures 14H, 14D, 14E and 14F respectively.
[0029] As described above, the present invention is a speed independent selector switch
for pipelined message transmission through digital communication networks.
1. A selector switch for receiving data signals from a node of a digital communication
network and transmitting those data signals to one of two other nodes, said selector
switch comprising: a pair of switch and buffer circuits
(62) each adapted to receive a set of said data signals; and an address circuit (60)
to receive said data signals preceded by an address signal specifying which of two
nodes is to be selected for subsequent transmission and to signal the corresponding
one of said switch and buffer circuits (62), caracterised in that said selector switch
further includes a pair of end of message circuits , one for each of said switch and
buffer circuits (62) to receive an end of message signal subsequent to the receipt
of a data signal; and a clear circuit (61) adapted to receive an acknowledge end of
message signal from the selected node and to transmit the signal to the original node.
2. A selector switch according to Claim 1, characterised in that said address circuit
(60) includes means to remove the first address bit of the address upon selection
of one of the pair of switch and buffer circuits (62).
3. A selector switch according to Claim 2, characterised in that each of said switch
and buffer circuits (62) serves as a two cell queue to receive a data bit from the
switch means in the first cell and to transfer that bit to the second cell only when
the second cell is empty, thereby enabling pipelining through connected selector switches.
1. Selektorschalter zum Empfang von Datensignalen von einem Knotenpunkt eines digitalen
Kommunikations-Netzwerks und zum Weiterleiten dieser Datensignale zu einem von zwei
anderen Knotenpunkten, mit zwei die Datensignale empfangenden Verteiler- und Pufferschaltungen
(62), und einer Adressenschaltung (60), welche die mit einem vorangestellten Adressensignal,
das angibt, welcher von zwei Knotenpunkten für die nachfolgende Übertragung auszuwählen
ist, versehenen Datensignale empfängt und die betreffende Verteiler-und Pufferschaltung
(62) ansteuert, dadurch gekennzeichnet, daß der Selektorschalter zusätzlich je eine
Ende-der-Nachricht-Schaltung für jede der Verteiler- und Pufferschaltungen (62), die
ein das Ende einer Nachricht anzeigendes Signal nach dem Empfang eines Datensignals
empfängt, und eine Auslöseschaltung zum Empfang eines bestätigten Ende-der-Nachricht-Signals
von dem ausgewählten Knotenpunkt, und zur Ubertragung dieses Signal zu dem ursprünglichen
Knotenpunkt enthält.
2. Selektorschalter nach Anspruch 1, dadurch gekennzeichnet, daß die Adressenschaltung
(60) eine Vorrichtung zum Entfernen des ersten Adressen-Bits der Adresse mit der Aswahl
einer der beiden Verteiler- und Pufferschaltungen (62) enthält.
3. Selektorschalter nach Anspruch 2, dadurch gekennzeichnet, daß jede der Verteiler
und Pufferschaltungen (62) als zweizellige Warteschlange dient, die ein Datenbit von
der Verteilervorrichtung in der ersten Zelle empfängt und das Bit zur zweiten Zelle
nur dann überträgt, wenn die zweite Zelle leer ist und damit ein Weiterleiten durch
die miteinander verbundenen Selektorschalter ermöglicht.