[0001] This invention relates to methods of manufacturing semiconductor devices.
[0002] Figure 3 of the accompanying drawings shows a circuit diagram of a resistor load-type
static random access memory (SRAM) in the form of a semiconductor device having a
semiconductor substrate with a resistor electrically connected to the substrate, and
including field effect transistors (FETs) 12 and resistors 13.
[0003] Figure 1 of the accompanying drawings shows a sectional view of a first previously-proposed
example of the SRAM 11. In this example, an SiO
Z layer 15 is formed on an Si substrate 14. A diffusion region 17 is formed in the
substrate 14 by diffusion through an opening 16 formed in the SiO
Z layer 15. The diffusion region 17 acts as the drain for the FET 12. A polycrystalline
Si layer 18 is formed to cover the diffusion region 17 and the SiO
2 layer 15. The polycrystalline Si layer 18 acts as the resistor 13.
[0004] The stand-by current of the SRAM 11 is determined by the resistance of the resistor
13. In the above example, the polycrystalline Si layer 18 serving as the resistor
13 has a relatively low resistivity of 5 x 10
5 ohm.cm. Therefore, the stand-by current of the SRAM 11 is relatively high, and power
consumption is high. These problems become particularly noticeable when a number of
SRAMs 11 are integrated.
[0005] Figure 2 of the accompanying drawings shows a second previously-proposed example
of the SRAM 11, forming an improvement over the first example. The SRAM 11 of this
example is substantially the same as that of the first example except that a polycrystalline
Si layer 19 containing oxygen is used in place of the pure polycrystalline Si layer
18.
[0006] As disclosed in issued Japanese Patent No. 55/13426, polycrystalline Si containing
oxygen has a very high resistivity: about 2 x 10
6 ohm.cm at an oxygen content of 2%, and about 10
10 ohm.cm at an oxygen content of 20%. A semiconductor device having a layer of polycrystalline
Si containing oxygen formed on a semiconductor substrate is also described in issued
Japanese Patent No. 53/2552.
[0007] The polycrystalline Si layer 19 containing oxygen is formed by a low-pressure chemical
vapour deposition (CVD) method using, for example, SiH
4 (flow rate: 50 cc/min), N
20 (flow rate: 2 cc/min), and N2 or He as needed. In this case, in order to stabilize
the N
20 flow rate, only N
20 is supplied for 1 to 2 minutes before the SiH
4 is supplied. Therefore, the Si surface of the substrate 14 is oxidized, and a thin
SiO
Z layer 20 is formed between the diffusion region 17 and the polycrystalline Si layer
19 containing oxygen.
[0008] When P or As is doped in a connecting portion between the diffusion region 17 and
the polycrystalline Si layer 19 in order to reduce the connection resistance of this
connecting portion, the SiO
2 layer 20 becomes PSG or AsSG. Even if annealing is performed after the polycrystalline
Si layer 19 has been formed, the SiO
2 layer 20 remains unchanged. Therefore, it is very difficult ohmically to connect
the diffusion region 17 and the polycrystalline Si layer 19.
[0009] As can thus be seen, it is difficult to obtain a sufficiently high resistance with
the pure polycrystalline Si layer 18, while it is also difficult ohmically to connect
the polycrystalline Si layer 19 containing oxygen to the diffusion region 17.
[0010] According to the present invention there is provided a method of manufacturing a
semiconductor device, comprising the steps of:
forming a first polycrystalline silicon layer over at least an electrically connecting
portion formed in a semiconductor substrate; and
forming a second polycrystalline silicon layer, containing oxygen, on said first polycrystalline
silicon layer;
characterised by:
annealing said semiconductor substrate on which said first and second polycrystalline
silicon layers are formed.
[0011] In methods embodying the present invention, an oxide formed between the first and
second polycrystalline silicon layers upon formation of the second polycrystalline
silicon layer containing oxygen is dispersed over the first and second polycrystalline
silicon layers, thereby ohmically connecting the electrically connecting portion of
the semiconductor substrate and the second polycrystalline silicon layer. In addition,
a high resistance can be obtained in the second polycrystalline silicon layer.
[0012] The invention will now be described by way of example with reference to the accompanying
drawings, throughout which like parts are referred to by like references, and in which:
Figures 1 and 2 are sectional views of respective previously-proposed examples of
SRAMs;
Figure 3 is a circuit diagram showing an SRAM to which the present invention can be
applied;
Figure 4 is a sectional view showing steps in a first method embodying the present
invention; and
Figure 5 is a sectional view showing a step in a second method embodying the present
invention and corresponding to the step shown in Figure 4E.
[0013] In the first method embodying the invention, as shown in Figure 4A, an SiO
2 layer 15 is formed on an Si substrate 14. A diffusion region 17 is formed in the
substrate 14 by diffusion through an opening 16 formed in the SiO
2 layer 15.
[0014] Subsequently, as shown in Figure 4B, a polycrystalline Si layer 18 having a thickness
of 50 to 200 angstroms (10
-10m) is formed by a low-pressure CVD method on the diffusion region 17 and the SiO
2 layer 15. Since a gas containing oxygen is not used in this step, an SiO
2 layer is not formed between the diffusion region 17 and the polycrystalline Si layer
18.
[0015] As shown in Figure 4C, a polycrystalline Si layer 19 containing 2 to 10 atomic %
of oxygen and having a thickness of 1,500 to 4,000 angstroms (10
-10m) is then formed by a low-pressure CVD method on the polycrystalline Si layer 18.
In this process, as in the case of the example of Figure 2, the polycrystalline Si
layer 18 is oxidized, and an SiO
2 layer 20 having a thickness of about 10 to 30 angstroms (10
-10m) is formed between the first and second Si layers 18 and 19.
[0016] As shown in Figure 4D, in order to reduce the connecting resistance between the diffusion
region 17 and the polycrystalline Si layer 18, P or As ions 21 are ion-implanted in
the connecting portion at a dose of
1 x 1016cm 2 and an acceleration energy of 70 keV.
[0017] The Si substrate 14 on which the polycrystalline Si layers 18 and 19 are formed is
annealed in an N
2 atmosphere at 900 to 1,000°C for 20 to 60 minutes. Then, as shown in Figure 4E, the
Si crystal grains of the polycrystalline Si layers 18 and 19, which had sizes of 20
to 50 angstroms (10
-10m), grow into Si crystal grains 22 having sizes of about 200 angstroms 5 (10" m).
The Si0
2 layer 20, which was sandwiched between the polycrystalline Si layers 18 and 19, is
formed into SiO
2 masses 23 that are dispersed between the Si crystal grains 22.
[0018] As a result, as shown in Figure 4E, the SiO
2 layer 20 disappears. The polycrystalline Si layers 18 and 19 are ohmically connected
and thus the polycrystalline Si layer 19 and the diffusion region 17 are also ohmically
connected.
[0019] When the SRAM 11 is manufactured by this method, a resistor 13 having a resistance
several times to several hundred times that of the example of Figure 1, using only
the polycrystalline Si layer 18, can be formed. The stand-by current can be reduced
to from 1/n to 11100n (where n is a positive integer smaller than 10).
[0020] Furthermore, the SiO
Z layer does not remain as in the case of the example of Figure 2. Therefore, the resistor
13 and the drain of the FET 12 can be ohmically connected.
[0021] Growth of crystal grains as described above is also described in M. Hamasaki et al,
"Crystal graphic study of Semi-insulating polycrystallize silicon (SIPOS) doped with
oxygen atoms", J.A.P. 49(7), July 1978, pp 3987 to 3992, and T. Adachi et al, "AES
and PES studies of Semi-insulating polycrystallize silicon (SIPOS) films", J.E. CS
Vol. 127, No. 7, July 1980, pp 1617 to 1621.
[0022] Figure 5 shows the second method embodying the invention and corresponds to Figure
4E of the first method. The second method has substantially the same steps as those
of the first method except that the polycrystalline Si layer 18 is formed not on the
entire surfaces of the diffusion region 17 and the SiO
2 layer 15, but only on the diffusion region 17 and the portion of the 5i0
2 layer 15 near the diffusion region 17.
[0023] In the SRAM 11, the polycrystalline Si layer 19 is used as a resistor in a direction
along the surface of the Si substrate 14. However, when the polycrystalline Si layer
18 is formed on the entire surface of the Si substrate 14 as shown in Figure 4E, a
current also flows in the polycrystalline Si layer 18.
[0024] Since the polycrystalline Si layer 18 has a lower resistivity than that of the polycrystalline
Si layer 19, the polycrystalline Si layer 18 must be made extremely thin as compared
with the polycrystalline Si layer 19 in order to obtain a high overall resistance.
However, it is not easy to form a very thin polycrystalline Si layer 18, and product
reliability also suffers when such a thin layer is used.
[0025] As in this method, however, if the polycrystalline Si layer 18 is formed only near
the diffusion region 17 to be in ohmic contact with the polycrystalline Si layer 19,
a resistor portion 24 in the polycrystalline Si layer 19 serving as a resistor 13
of the SRAM 11 has a high resistance. Therefore, since the polycrystalline Si layer
18 can be formed to have a thickness of 1,000 to 2,000 angstroms (10
-10m) larger than in the first method, the polycrystalline Si layer 18 can be formed
easily and product reliability is improved.
[0026] In the first and second methods, the present invention is applied to the manufacture
of SRAMs. However, the invention can also be applied to the manufacture of devices
other than SRAMs.
1. A method of manufacturing a semiconductor device (11), comprising the steps of:
forming a first polycrystalline silicon layer (18) over at least an electrically connecting
portion (17) formed in a semiconductor substrate (14); and forming a second polycrystalline
silicon layer (19), containing oxygen, on said first polycrystalline silicon layer
(18);
characterised by:
annealing said semiconductor substrate (14) on which said first and second polycrystalline
silicon layers (18,19) are formed.
2. A method according to claim 1 wherein said electrically connecting portion (17)
is an impurity diffusion region (17) formed in said semiconductor substrate (14).
3. A method according to claim 1 or claim 2 wherein said first and second polycrystalline
silicon layers (18,19) are formed overlying the same region of said semiconductor
substrate (14).
4. A method according to claim 1 or claim 2 wherein said first polycrystalline silicon
layer (18) is formed only near said electrically connecting portion (17).
5. A method according to any one of the preceding claims wherein said first polycrystalline
silicon layer (18) has a thickness of 1,000 to 2,000 angstroms (10" m).
6. A method according to any one of claims 1 to 4 wherein said first polycrystalline
silicon layer (18) has a thickness of 50 to 200 angstroms (10-10m), and said second polycrystalline silicon layer (19) has a thickness of 1,500 to
4,000 angstroms (10-10m).
7. A method according to any one of the preceding claims wherein said second polycrystalline
silicon layer (19) contains 2 to 10 atomic % of oxygen.
8. A method according to any one of the preceding claims wherein said annealing step
is performed in a nitrogen atmosphere at 900 to 1,000°C for 20 to 60 minutes.
9. A method according to any one of the preceding claims wherein said first and second
polycrystalline silicon layers (18,19) serve as a resistor (13) of a SRAM (11).
10. A method according to claim 9 wherein said electrically connecting portion (17)
is a drain region of an FET (12) of said SRAM (11).