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(11) | EP 0 244 991 A2 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Variable delay circuit |
| (57) A data processing system is described comprising a display terminal (10) and a processing
unit (11). The display terminal includes a video timing generator (14) producing synchronisation
signals (VSYNC, HSYNC). This triggers requests (QUAL) for the processing unit to supply
video data. The display terminal includes a variable delay circuit (24) which measures
the time delay between the outgoing request and the incoming data, and causes the
synchronisation signals to be delayed by a corresponding amount. This ensures that
the synchronisation signals are maintained in the correct timing relationship with
the video data, irrespective of any unknown delays between the display terminal and
the processing unit. |
[0002] The invention is particularly, although no exclusively, concerned with a delay circuit for use in a data processing system comprising a processing unit and a display terminal remote from the processing unit. In such a system, the display terminal normally produces synchronisation signals for controlling the scanning of the display. It has been proposed to use these synchronisation signals to generate request signals, which are sent to the processing unit requesting it to supply video data to the terminal. However, a problem arises in that, when the data arrives at the display terminal, it will not be in the correct timing relationship with the synchronisation signals: it will be delayed relative to the synchronisation signals by an amount which depends on the transmission delay between the display terminal and the processing unit. This delay will be unknown, and will vary if the connections between the display terminal and processing unit are altered.
[0003] One object of the present invention is to provide a variable delay circuit which can used to overcome this problem.
Summary of the invention
[0004] According to the invention there is provided a variable delay circuit comprising a variable delay line, characterised by means (30,31) for measuring the time delay between two control signals (QUAL3, ENTER5+), and means for automatically setting the delay of the delay line (31,32) to a value corresponding to the measured delay.
[0005] The two control signals may be, for example, a request signal from a display terminal, requesting a processing unit to supply video data, and a data qualifier signal which is returned to the display terminal along with the requested data, and the delay circuit may be used to delay a synchronisation signal in the display terminal. In this case, it can be seen that the delay circuit can be arranged to automatically adapt itself to compensate for delays between the display terminal and the processing unit, so as to ensure that the synchronisation signal is correctly aligned with the data.
Brief description of the drawings
[0006] One variable delay circuit in accordance with the invention will now be described by way of example with reference to the accompanying drawings.
Figure 1 shows a data processing system including a display terminal and a processing unit, wherein the display terminal includes a variable delay circuit.
Figure 2 shows the variable delay circuit in more detail.
Description of an embodiment of the invention
[0007] Figure 1 shows a data processing system comprising a display terminal 10 and a data processing unit 11 interconnected by an interface 12. The distance between the terminal 10 and processing unit 11 may be typically of the order of 10 metres.
[0008] The display terminal 10 includes a video monitor 13 having a conventional raster-scanned display. The display terminal has a video timing generator 14 for producing the conventional synchronisation signals for the monitor, including a horizontal synchronisation signal HSYNC, a vertical synchronisation signal VSYNC, and a blanking signal BLANK. Normally, the synchronisation signals would be applied directly to the monitor, but in the present system they are delayed, as will be described below. Both the monitor 13 and the video timing generator 14 may be conventional units and will not be described in any further detail.
[0009] The video monitor 13 and the video timing generator 14 are both controlled by a clock signal CLK from a clock generation circuit 15. This clock has a frequency equal to the pixel (picture element) rate of the monitor. The clock CLK is divided in frequency in a circuit 16 by a factor R, equal to the number of pixels represented by each data word supplied by the data processing unit 11, to produce a request clock signal RCLK. For example, if each data word contains 32 bits, and each pixel is represented by four bits, then R=8.
[0010] The display terminal also includes a request generation circuit 17, which receives the request clock RCLK, the vertical synchronisation signal YSYNC, and the blanking signal BLANK. Wherever the signal VSYNC occurs, indicating the start of a frame, the circuit 17 produces a series of request signals QUAL, one for each request clock RCLK for which BLANK is false. Each of these request signals QUAL requests the processing unit 11 to supply a word of video data. The number of QUAL signals produced after each VSYNC is a present number, equal to the number of video data words required to make up a frame.
[0011] The request signal QUAL is transmitted over the interface 12, along with the request clock RCLK, to the processing unit 11. Whenever the processing unit receives a request signal QUAL, it outputs a word of video data, in synchronisation with the received request clock RCLK, and transmits it back to the display terminal 10, along with a data qualifier QUALD which indicates the presence of a data word. The data processing unit 11 also returns the clock signal RCLK to the display terminal along with the data, as a data clock signal DCLK, to which the data is synchronised.
[0012] This technique of re-transmitting the request clock signal back to the requesting unit along with the requested data is the subject of our European Patent Application No. 175564.
[0013] When the data is received by the display Terminal 10, it is clocked through two registers 18,19 by the data clock DCLK. The output of the register 19 is fed to a parallel-to-serial converter 20, which converts each 32-bit data word into a series of groups of 32/R bits, at the pixel clock rate, each group representing one pixel of the display. The output of the converter 20 is then fed to the video monitor 13 where it is converted to analog form to provide the video input signal for the monitor.
[0014] It can be seen that the data input to the monitor 13 is delayed, relative to the original VSYNC signal that produced the request for the data, by five beats of the clock signal RCLK, plus the unknown delay in travelling around the loop from the display terminal to the processing unit and back again. (These five clock beat delays occur respectively in the request generator 17, the processing unit 11, the register 18, the register 19, and the parallel-to-serial converter 20). Thus, the synchronization signals HSYNC and VSYNC will not be in the correct timing relationship with the data, and must be delayed by the same amount (5 clock beats plus the loop delay) before being applied to the monitor. The way in which this is done will now be described.
[0015] The synchronisation signals HSYNC and VSYNC are clocked through a pipeline comprising two registers 21,22 by the request clock signal RCLK. These signals pass through the pipeline twice as shown, to that they emerge four beats later as signals HSYNC4 and VSYNC4. At the same time, the request signal QUAL is clocked once through the pipeline registers 21,22, to emerge two beats later as signal QUAL 3. (The "3" indicates that this signal occurs three clock beats after the original VSYNC signal, including one clock beat delay in the request generator 17).
[0016] The first data qualifier QUALD returning from the processing unit to the display terminal is clocked into a register 23 by the data clock DCLK and is latched there by a feedback connection. this produces a signal ENTER 3+ which remains true until the register 23 is reset by a RESET signal. The "3+" indicates that this signal is delayed relative to the original VSYNC signal by three clock beats (in the request generator 17, the processing unit 11, and the register 23) plus the unknown loop delay in travelling from the display terminal 10 to the processing unit 11 and back again.
[0017] The signal ENTER 3+ is clocked through the pipeline registers 21,22 to emerge two clock beats later as a signal ENTER 5+. This resynchronises this signal to the clock RCLK, eliminating any fraction of a clock beat delay between QUAL 3 and ENTER 5+.
[0018] The signals QUAL 3 and ENTER 5+ are applied to a delay circuit 24, which measures the time delay between these signals in terms of number of beats of the clock RCLK. The delay circuit 24 also receives signals HSYNC4 and VSYNC4 and delays them by an amount one clock beat less than the measured delay between QUAL 3 and ENTER 5+, to produce output synchronisation signals HSYNCOUT and VSYNCOUT for the monitor 13. It can be seen that HSYNCOUT and VSYNCOUT are therefore delayed, relative to the original VSYNC signal, by five beats of RCLK, plus the loop delay in travelling between the display terminal and the processing unit and back again (ignoring any fraction of a clock beat). In other words, these signals HSYNCOUT and VSYNCOUT are delayed by the same number of whole clock beats as the data applied to the video monitor 13.
[0020] Referring to Figure 2, the delay circuit 24 comprises a three-bit binary counter 30 which produces an output signal SQ. When the counter is enabled by a signal ENCOUNT, it counts up from state 0 (SQ=0) to state 7 (SQ=7) at successive beats of the clock RCLK. After state 7, the counter recycles back to state 0.
[0021] The signal SQ controls a multiplexer 31 so as to select one of seven inputs 1-7 according to the value of SQ. Thus, if SQ=1, input 1 is selected, and so on. If SQ=0, no input is selected.
[0022] The delay circuit 24 also includes a shift register 32 which receives the signal VSYNC4 at its serial data input and is controlled by the clock signal RCLK. Thus, the signal VSYNC4 is shifted through successive stages of the shift register at successive beats of RCLK. The outputs of the stages of the register 32 are connected to respective inputs of the multiplexer 31. The output of the multiplexer 31 provides the signal VSYNCOUT.
[0023] Thus, it can be seen that the shift register 32 and the multiplexer 31 together act as a variable delay line which delays the signal VSYNC4 by a number of beats of the clock RCLK, specified by the signal SQ. For example, if SQ=2 then VSYNCOUT is delayed by two clock beats relative to VSYNC4.
[0024] The counter 30 is controlled by a control circuit 33, which receives the signals SQ, QUAL 3 and ENTER 5+, and produced the signal ENCOUNT which enables the counter, and also a signal RESET which resets the counter to state (SQ=7). This control circuit can conveniently be implemented by means of a programmable logic array, and performs the following logic functions:
ENCOUNT is true if either
(1) QUAL 3 is true AND ENTER 5+ is false AND SQ=7
OR (2) ENTER 5+ is false AND SQ=0, 1, 2....6.
Otherwise ENCOUNT is false.
[0027] It is assumed initially that the counter 30 is in state 7 (SQ=7) and that QUAL 3 and ENTER 5+ are both false. The counter is therefore disabled and remains in state 7.
[0028] When the signal QUAL 3 arrives, ENCOUNT is made true, and the counter 30 is therefore enabled, so that it steps forward to state 0 at the next clock beat.
[0029] If ENTER 5+ still remains false, then ENCOUNT will stay true, and hence the counter continues to step forward one state at each clock beat, until ENTER 5+ goes true. The counter 30 is then disabled, and hence is frozen in its current state.
[0030] Thus, it can be seen that QUAL 3 triggers the counter 30 to start counting, and the counter will then count up one at each successive clock beat until ENTER 5+ arrives, whereupon it is frozen. The count value will then indicate the time delay, measured in beats of the clock RCLK, between QUAL 3 and ENTER 5+. For example, if ENTER 5+ occurs 5 clock beats after QUAL 3, then the counter will be frozen in state 4 (SQ=4). (It should be noted that the state number is one less than the measured number of clock beats delay).
[0031] Thus, it can be seen that VSYNCOUT is delayed relative to VSYNC4 by one clock beat less than the measured delay between QUAL 3 and ENTER 5+.
[0032] However, if ENTER 5+ occurs only one beat after QUAL 3, i.e. while SQ=0, then RESET signal is produced, and the counter is forced into state 7. This indicates an error condition since ENTER 5+ should not occur at this time: even if the loop delay between the display terminal and the processing unit is less than a single clock beat, ENTER 5+ should still occur two clock beats after QUAL 3 in the system as shown in Figure 1.
1. A variable delay circuit comprising a variable delay line, characterised by means
(30,31) for measuring the time delay between two control signals (QUAL3, ENTER5+),
and means for automatically setting the delay of the delay line (31,32) to a value
corresponding to the measured delay.
2. A circuit according to Claim 1 wherein the means for measuring the time delay comprises
a counter (30) which is triggered when the first of the two control signals (QUAL3)
arrives, and which then counts beats of a clock signal (RCLK) until the second of
the two control signals (ENTER5+) arrives.
3. A circuit according to Claim 1 or 2 including error detection means for indicating
an error condition if the measured delay between the two control signals is smaller
than a predetermined value.
4. A data processing system comprising
(a) a first unit (10) including means for generating a synchronisation signal (VSYNC, HSYNC) and a request signal (QUAL) in a predetermined timing relationship to the synchronisation signal, and
(b) a second unit (11) remote from the first unit, the second unit being operative upon receipt of said request signal from the first unit to return data to the first unit along with a data qualifier (QUALD) indicating presence of the data,
(c) characterised in that the first unit includes a variable delay circuit (24) having means for measuring the time delay between said request signal and said data qualifier and means for delaying said synchronisation signal by an amount dependent upon the measured time delay.
5. A system according to Claim 4 wherein the first unit is a display terminal and
the second unit is a data processing unit.
6. A system according to Claim 5 wherein the synchronisation signal is a video synchronisation
signal, and the data is video data.
7. A system according to any one of Claims 4 to 6 wherein the means for measuring
the time delay comprises a counter (30) which is triggered by the request signal,
and which then counts beats of a clock signal until the data qualifier arrives.
8. A system according to any one of Claims 4 to 7 wherein the means for measuring
the time delay includes error detection means for indicating an error condition if
the measured time delay is less than a predetermined value.