Modular high-speed multipliers, and integrated circuit chip modules for such multipliers

Description

[0001] This invention relates to high-speed multipliers.

[0002] In the past, multiplication was most often performed in digital data processors by repetitively adding the multiplicand to itself the number of times indicated by the multiplier. As speed increased, this repetitive addition by the machine's adder gave way to the use of individual multiplier circuits. Today, most comtemporary large scale processors utilize specialized networks to accomplish faster multiply operations. These networks are designed to simultaneously process several multiplier bits. Further, a number of specialized algorithms have been developed to simplify the logic used in the building of these arrays. Generally, this simplification involves the decoding of multiplier groups and interaction between the multiplier groups to control the array.

[0003] This approach, of course, complicates the control aspect, while simplifying the array. Such arrays are commonly built of a combination of adders and multiplexers, with multiplier decoders used for control. The adders used may be of the conventional type or they may take the carry/save form.

[0004] Another common feature in past digital data processors has been the inclusion of error detecting networks in all data paths of the machine. However, present day large scale integrated (LSI) devices do not provide for the inclusion of these error detecting networks in the usual manner. This leaves duplication and result comparison as the only available method of error detection for these LSI devices.

[0005] One specific earlier example of a fast multiplier was suggested in the article published in IEEE Transactions on Electronic Computers in an article by C. S. Wallace, entitled "A Suggestion for a Fast Multiplier", on pages 14-17 of the February, 1964 issue. The article suggests that the economics of large scale scientific computers of that day could benefit from greater investment in hardware to mechanize multiplication that was common in computers of a still earlier vintage.

[0006] Multiplication of binary fractions is normally implemented as the addition of a number of summands, each some simple multiple of the multiplicand, chosen from a limited set of available multiples on the basis of one or more multiplier digits. No good reason is known to depart from this general scheme. Acceleration of the process must then be based on one or more of the following expedients: (1) reduction in the number of summands; (2) acceleration of the formation of summands; (3) acceleration of the addition of summands. Acceleration of addition will be discussed initially.

[0007] The basic addition processes usually employed in computers add two numbers together. The possibility exists of adding together more than two numbers in a single adder to produce a single sum. However, the logical complexity of the adder required appears to grow quite disproportionately to the resulting increase in speed, consequently there appears to be no advantage in trying to sum even three numbers at a time into a single sum.

[0008] Another expedient, now quite commonly used, is to employ a pseudoadder which adds together three numbers, but rather than producing a single sum, produces two numbers whose sum equals that of the original three. In the context of the basic problem of adding together many summands, one pass through such an adder reduces the number of summands left to be summed by one, as does a pass through a conventional adder. The advantage of the pseudoadder is that it can operate without carry propagation along its digital stages and hence is much faster than the conventional adder. Thus, rather than allowing the possibility of a carry propagation from the lowest-order digit to the highest-order digit, carry propagation is allowed only to the next-highest-order digit. A simple form for such an adder is a string of full adder circuits of the normal sort, where the carry inputs are used for the third input number, and the carry outputs for the second output number. In multiplication, one pseudoadder is usually used, and storage is provided for two numbers. On each pass through the adder, the two stored numbers and one multiple of the multiplicand are added, and the resulting two numbers returned to storage.

[0009] In any scheme employing pseudoadders, the number of adder passes occurring in a multiplication before the product is reduced to the sum of two numbers will be two less than the number of summands, since each pass through an adder converts three numbers to two, reducing the count of numbers by one. To improve the speed of the multiplication, one must arrange many of these passes to occur simultaneously by providing several pseudoadders.

[0010] Assuming that all summands are generated simultaneously, the best possible first step is to group the summands into threes, and introduce each group into its own pseudoadder, thus reducing the count of numbers by a factor of 1.5 (or a little less, if the number of summands is not a multiple of three). The best possible second step is to group the numbers resulting from the first step into threes and again add each group in its own pseudoadder. By continuing such steps until only two numbers remain, the addition is completed in a time proportional to the logarithm of the number of summands.

[0011] Successive steps may use the same set of pseudoadders (using progressively fewer of the set in each step) by using temporary storage registers for the outputs of the pseudoadders. However, if we use separate adders the equipment cost is little, if at all increased, since the additional pseudoadders required will not need many more components than the flip-flop registers eliminated, and the control circuitry is greatly simplified. Further consideration of this approach will reveal that the purely combinational adder would have a considerable speed advantage. In the simplest form of multiplication, there are as many summands as multiplier digits, each either 0 or 1 times the multiplicand. A wide range of schemes involving recoding the multiplier into a new (possibly redundant) form using some negative diqits have been developed to reduce the number of summands. Since all summands are to be generated simultaneously, and then summed very quickly, it is desirable that the recoding scheme used should (1) require only multiples of the multiplicand obtainable by shifting and complementing, and (2) be a local recoding in which each recoded digit depends only on a small group of original multiplier digits. The best system found gives base-four recoded multiplier digits which can be +2, +1, 0-1 or -2, and each is determined entirely by three adjacent original binary multiplier digits. Considering the process as a base-four recoding, digits, 0, 1, 2, 3 are recoded into digits 0, 1, -2, -1, respectively, if the next less significant original base-four digit is 0 or 1, and into 1,2, -1,0 0 if the next less significant original digit is 2 or 3. The number of summands is half the number of binary multiplier digits. Attempts to reduce the number further appear to require multiples not obtainable by shifting. Some complications arise in the pseudoadder structure because of the negative multiplier digits, which, in a two's complement system, require correction digits to be added in. Howver, detailed examination shows that these problems are surmountable without loss of speed or undue circuit cost.

[0012] Additional schemes for parallel multipliers which are based on different principles and having some advantages over those presented above by C. S. Wallace, have been proposed by L. Dadda in his article entitled Some Schemes for Parallel Adders published in "Alta Frequenza" in March 1965 at pages 349 to 356.

[0013] In his conclusions, Mr. L. Dadda suggests that having established the possibility of a parallel digital multiplier, some considerations can now be made about the important aspects of speed and cost that can be encountered in a pratical design.

[0014] He suggests that if one assumes that a third of all arithmetic operations in scientific computers are multiplications and that these, at present, take about four times as long as additions, the use of a fast multiplier allowing a multiplication in a memory cycle time, would approximately double the speed of computation.

[0015] There is therefore a chance that a parallel multiplier could become a convenient means to improve the value of a computer, owing to the fact that its cost can be shown to be only a few percent of the total computer cost.

[0016] Let us first note that the total multiplication time is composed of two parts: the first is the time elapsed from the application of the signals representing the two factors to the inputs of the multiplier, to the availability of the inputs to the carry-propagating adder; the second part is the delay proper of the adder, mainly consisting in the carry propagation delay.

[0017] In the design of a practical multiplier, one can assume as a goal to obtain a total delay equal or less than the cycle time of the high-speed memory, so that the computer can work at its maximum speed, limited only by the memory speed. The choice of the type of circuits depends therefore on the memory cycle time of present day computers. The increasing use of large scale integration appears to suggest it as the prime path for multipliers as well.

[0018] Among the different type of full adders, the most suitable for the application in parallel multipliers, from the point of view of economy and speed, are those which require input variables of one form only (natural or complemented) so that output variables of the same form only must be generated. If such condition is satisfied, outputs of one stage can be used directly as inputs to the next stages, without the need of inverters, leading in general to a considerable saving in components and to a reduction of stage delay.

[0019] It must be noted that the above restriction can be partially relieved by allowing the use of counters producing outputs of only one form but different from the input's form.

[0020] Another similar multiplier circuit is disclosed in US-A-4 523 210 entitled "Fast Error Checked Multibit Multiplier", by Glen R. Kregness filed June 8, 1982 and assigned to the present assignee. The differences and improvements in the present application will be more clearly understood as one reads and understands the present description. However, generally that earlier application is primarily concerned with the use of a gated carry/save network. Through the use of that network, the need for the decoding of the multiplier bits was eliminated. Although the array itself is increased in complexity, the multiplexers required by earlier systems have been eliminated. In addition, interaction between multiplier groups is no longer required. The net effect is a reduction in logic with faster operation because of the elimination of the decoding.

[0021] Even though it is well known, indeed, that many important features of today's fast computers depend on the fact that during operations that last longer than one memory cycle (typically, during multiplication or division) memory can be made available for other operations (e.g. input-output) it is still desirable to process in parallel. Thus, a unique approach for the construction of an LSI multiplier will now be described which provides a unique logic block for use in creating a multiplication pipeline of arbitrary size.

[0022] Accordingly it is an object of this invention to provide an improved multiplier for use in a large scale digital data processing system, and integrated circuit chips which may be used for building such a network. Each chip includes provision for parity generation.

[0023] "US patent 3 670 956 describes a high speed digital multiplier in which multiplication is carried out by successive ranks of multiplier modules. US patent 3 596 072 describes the use of a predicted parity of a carry signal in a carry save adder."

[0024] A logical building block for use in a binary digital multiplier circuit is disclosed wherein the logical building block may be used to create a multiplication pipeline with parity, which pipeline may be of arbitrary size. The multiply pipeline with parity configuration includes circuits for generating and checking parity. The parity of the output carries leaving the component chips of the multiply pipeline are explicitly generated internally to those chips. By generating output carry parity on-chip, all single-bit errors except for those caused by on-chip internal gate or metallization faults will be detected. Thus, means are provided for detection of single-bit errors in the multiplication circuitry. The proposed multiply pipeline with parity circuit includes a pair of gate arrays, or chips, which participate as follows. A 6-bit by 6-bit multiply with parity chip is used as a building block in a portion of the pipeline in which all logical products are initially generated, and reduction of these logical products, or partial products, commences. A 6-bit by 4-bit adder/register with parity chip is used as a building block in subsequent sections of the pipeline, which are used to further reduce the partial products. This latter chip type also contains a latch register to provide orderly and controlled staging of the intermediate partial products.

[0025] The invention will be further described with reference to the accompanying drawings, in which:

Fig. 1 is a functional block diagram of a multiplier according to the invention.

Fig. 2 is a detailed block diagram of the 6x6 multiply-with-parity gate array used in the multiplier of Fig. 1.

Figure 3 illustrates an individual carry/save adder used in the logical diagram of Fig. 2.

Fig. 4 illustrates the function of the 6x6 multiply-with-parity gate array.

Fig. 5 is a detailed logical block diagram of the 6x4 adder tree/register with parity gate array used in the multiplier of Fig. 1.

Fig. 6 illustrates the logical interconnection of the 6x6 multiplier gate array and the 6x4 adder tree/register gate array to form a 12-bit by 12-bit multiplier.

Fig. 7 is a table showing the formation of logical products in the 6x6 multiplier gate arrays for the multiplier of Fig. 6.

Fig. 8 shows the use of 12-bit by 48-bit multipliers, adder tree/registers, and full binary adders to form a 48-bit by 48-bit multiplication pipeline.

[0026] Fig. 1 shows a simplified block diagram of a 12-bit by n-bit multiplier. The value of n is assumed to be a multiple of six, which may be achieved by appending zeros to the data which is to be used as the multiplicand. The inputs to the multiplier consist of a 12-bit multiplier held in the Multiplier Register 110, and a n-bit multiplicand, held in the Multiplicand Register 112. These registers are clocked simultaneously via clock signal A. The bits in these registers are numbered starting at 1, from left to right. The main outputs of the multiplier consist of a n+12 bit Sums word and a n+12 bit Carries word. These two outputs, when added together after shifting the Carries left one position, will form the desired product. Parity information is included with all input and output data and parity checking of the multiplier is performed.

[0027] Each of the lower ranks (0 and 1) 114 and 118, of the multiplier consists of 6-bit by 6-bit multiplier chips, numbering n/6+1 chips. The outputs of these ranks 114,118 consist of Sums and Carries similar in principle to the overall multiplier outputs, and combined Parity of the Internal, (PIC) and Output (POC) Carries. Internal carries are any carries produced in the process of reducing the summands by addition, but which are not accessible to the pins of the individual chips because of pin limitations.

[0028] The Upper Rank 122 of the multiplier consists of 6-bit-wide by 4-bit adder/register chips, numbering n/6+2 chips. This rank 122 reduces the four inputs from the lower ranks 114, 118 to the Sums and Carries which form the final product, and it also produces the Parities of the Internal (PIC) and Output (POC) Carries separately for error detection.

[0029] Lower rank 0, 118 is fed the most significant six bits of the Multiplier, bits 1 through 6, and Lower Rank 1, 114 is fed the least significant six bits of the Multiplier, bits 7 through 12. The entire Multiplicand 112 is fed to both of the Lower Ranks 114, 118.

[0030] When the Sum and Carry outputs of the Lower Ranks 114, 118 are connected to the Upper Rank 122, the Carries must be logically left-shifted by one bit position relative to the Sums. In addition, the Sum and Carry outputs of Lower Rank 0, 118 must be connected to the Upper Rank 122 six bit positions to the left relative to the respective Lower Rank 1, 114 connections.

[0031] The scheme used for error detection and parity generation will now be described. Let p(x) represent the parity of x, ^* represent the logical AND operator, and E) represent the logical exclusive-OR operator. Equations for parity generation are developed as follows.

[0032] For the outputs of Lower Ranks 0 and 1:

[0033] when Multr stands for Multiplier, Mpcd for Multiplicand, IC for Internal Carries and OC for Output Carries.

[0034] For the Upper Rank, and overall parity:

[0035] where AC stands for combined internal and Output Carries.

[0036] The parity of any of the carries, internal or external, is not readily predicted, and is instead generated directly from the carries inside each chip. External parity generators 124,126 are labelled PG in Fig. 1, and parity checkers 128, 130 which detect single bit errors, are labelled PC. The PC and PG functions are logically identical, and are circuits which perform multiple-bit exclusive-OR functions.

[0037] Fig. 2 shows the internal structure 200 of the 6-bit by 6-bit multiply circuits which are used to build structures 114, 118 of Fig. 1. The triangular structures 250, 254, 258, 262, 268, 272, 276, 278 and 280 represent parity generators with the same function as in the previous discussion. These circuits are well known in the art and require no further discussion. The trapezoidal structures 300 represent carry-save adders, each of whose function will be later described in conjunction with Fig. 3.

[0038] In the simplest form of binary multiplication, as in ordinary pencil-and-paper decimal multiplication, the entire multiplicand is multiplied by each digit of the multiplier. This causes the formation of as many partial products as there are digits in the multiplier. In binary multiplication, the multiplicand is merely copied for non-zero multiplier bits, and all zeros are copied for multiplier bits equal to zero. When the resulting partial products are arranged in a column with respect to the order of the multiplier bits used and in such a manner that all of the bits in a column have the same mathematical weight, a parallelogram is formed, the sum of whose rows produce the desired product.

[0039] The circuit of Fig. 2 generates a 6-bit square of this parallelogram for binary multiplication, and reduces the six rows to two rows termed sums and carries using the network of carry-save adders. There are six columns of four carry-save adders each. The partial product bits are all formed at the inputs to the lowest row of the carry-save adders via AND gates at each adder input. These are not explicitly shown in Fig. 2, but are implied by the structure labelled Adder Control 212. The bits being AND-ed at each input will be later detailed in Fig. 4.

[0040] The main inputs to the circuit chip are the 6-bit Multiplier 208 entering Adder Control 212 which implies the generation of six rows of partial products, and the 11-bit Multiplicand 210. Eleven bits are required since eleven different Multiplier bits participate in a 6-bit wide slice of the partial product parallelogram as the Multiplicand is left-shifted five times. This is also illustrated in Fig. 4.

[0041] The main outputs of the circuit chip are six Sum bits, (noted as out sum 1 through out sum 6) and six Carry bits, (out cy1 through out cy6). When added together as shown in the lower portion of Fig. 4 below the summation bar, along with the Stage Carries to be discussed later, these form the sum of the six original rows of partial products.

[0042] Fig. 3 illustrates the function of a single carry-save adder 300. The function of this structure is to add together three input bits of equal weight x, y, and z to produce a two-bit output sum. The most significant bit of this sum is termed the Carry bit, and the least significant bit is termed the Sum bit. Generalized Boolean equations for these bits are also shown in Fig. 3.

[0043] As shown in Fig. 4, each column of four carry-save adders reduces a column of six partial product bits to two bits, a Sum and a Carry Sn, Cn. Internal carries are allowed to propagate only to the next-highest order column when passing through each of the three ranks of adders in the circuit chip. Carries leaving the highest-order column, and those entering the lowest-order column, are termed Stage Carries. These are provided as pins on the circuit chip to allow unlimited extension of the three adder ranks for wider multiplicands. The parity of the internal carries and output stage carries, the parity of the output carries and their combined parity is also generated and sent to output pins for error checking.

[0044] As previously stated, the function of the 6-bit by 6-bit multiplier chip is illustrated in Fig. 4. The generation of the 6-bit square slice of the partial product parallelogram is also shown in Fig. 4. The Multiplier and Multiplicand bits are numbered to correspond with Fig. 2. Each Multiplier bit is AND-ed with each of the Multiplicand bits on its row. Fig. 4 illustrates the manner in which the output Sums, Carries, and Stage Carries are aligned before addition to produce the sum of the six partial product rows.

[0045] Fig. 5 shows the internal organization of the 6-bit wide by 4-bit adder/register circuit chip 500. This circuit chip 500 reduces four summands A, B, C, and D to two numbers, also termed Sums and Carries, using a network of carry-save adders 512 to 534, as in the multiplier circuit chip. In this case, only four rows A, B, C and D of data are being reduced, so that two ranks of adders are sufficient. Again, carries from the lower rank are allowed to propagate only to the next highest-order column of adders.

[0046] Carries leaving the first rank of adders from the highest-order column 512 and entering the second rank of adders in the lowest-order column 534 are termed Stage Carries. Pins are provided for the Stage Carries to allow unlimited extension of the adder/register structure.

[0047] As previously discussed, the main inputs to the adder/register chip 500 are the four Summands, named A, B, C, and D, each consisting of six bits numbered 1-6. The like-numbered bits of each Summand are applied to the same column of adders. The outputs of the second rank of adders 524, 526, 528, 530, 532 and 534 are six sum bits and six carry bits which are captured in twelve bits of a latch register 540 located on the circuit chip.

[0048] Parity of the internal carries and the output Stage Carry is generated and latched in the remaining bit of the 13-bit latch register 540.

[0049] The main outputs of the circuit chip are the Sum and Carry output signals and the parity of the output Carries which is generated on the circuit chip directly from the register outputs via parity generator 542. The Sum and Carry outputs 544, 546 and internal carry parity 548 come directly from the latch register 540.

[0050] Fig. 6 illustrates the detailed interconnection of the Multiplier 610 and Multiplicand 612 registers, the two Lower Ranks of 6-bit by 6-bit multiplier chips 200, the Upper Rank of 6-bit by 4-bit adder/register chips 500, and external error detection gating necessary to build a 12-bit by 12-bit multiplier. To form the resulting 24-bit product, a 24-bit full binary adder may be used to add the output Sums from the Upper Rank to the left-shifted output Carries from the Upper Rank. This adder is not shown.

[0051] Fig. 6 further clearly illustrates how the Carry outputs from each of the Lower Ranks 0 and 1 are, in effect, left-shifted before being fed forward to the Upper Rank. Several important points should also be noted. The first point is that bit 1 of the Carries is not connected to any subsequent logic for any of the ranks. This is because these Carry bits will always be zero if the multiply array is connected in this scheme. If these bits were non-zero, the product would be forced to be one bit wider than is mathematically possible for a given rank. Another point is that the Stage Carries out of the left end of any given rank are also left unconnected for the same reason. The relationship of the Lower Ranks 0 and 1 to the Upper Rank and to each other is also clearly shown. The Lower Ranks 0 and 1 are offset from each other by six bit positions, since each takes a separate but adjacent six-bit slice of the Multiplier. Each of the Lower Ranks 0 and 1 takes identical Multiplicand connections as shown. The scheme of these connections will be better understood when studying Fig. 7.

[0052] Fig. 7 shows a chart of how the partial products are formed in each of the Lower Ranks and the necessary Multiplier and Multiplicand connections for the 12-bit by 12-bit multiplier of Fig. 6. This chart can be extended to show the necessary connections for a 12-bit by n-bit multiplier where n is a multiple of 6. Note that this chart is reversed top-for-bottom with respect to the logical connection scheme of Fig. 6, to present its information in a natural mathematical sense.

[0053] Fig. 7 illustrates how the multiplication operation may be thought of as taking shifted copies of the Multiplicand 710, ANDing each of the shifted copies with a particular bit of the Multiplier 712, and summing the resultant logical products. Each of the six-bit square areas 714, 716, 718, 720, 722, 724 outlined in Fig. 7 represents the area of logical products covered by a single 6-bit by 6-bit multiply chip. By inspecting the centre square 716 of the top row, the need for eleven different bits of Multiplicand to be applied to each multiply chip is clear. Note that roughly one-half of each of the end multiply chips is wasted due to zero-filling. As the width of the Multiplicand increases, the fraction of the multiplication array wasted due to zero-filling decreases proportionally.

[0054] A multiplication pipeline built from the chips and structures previously discussed is presented in Fig. 8. The pipeline implementation shown is designed to multiply a 48-bit Multiplier 810 and a 48-bit Multiplicand 812 to form a 96-bit Product. Since this is a pipeline, a new Product may be formed at the clock cycle rate of the pipeline. There are four structure types identified besides the latch registers holding the Multiplier, Multiplicand, and Product previously described.

[0055] Each of the first structure type A's included in dotted area 801 consists of two ranks of 6-bit by 6-bit multiply circuit chips and one rank of 6-bit by 4-bit adder/register chips as shown in Figs. 1 and 6. There are four copies of structures type A, 814, 816, 818, 820, all sharing the same Multiplier and Multiplicand registers 810, 812. The ranks of multiply circuit chips are nine chips wide, and the rank of adder/register chips is ten chips wide. These structures form the original 48 partial product rows, and reduce them to 8 partial product rows.

[0056] Each of the second structure type B's included in dotted area 802 consists of a rank of twelve 6-bit by 4-bit adder/register chips, interconnected as shown in Fig. 6. These structures reduce the 8 rows of partial products to 4 rows. Structure type C 826 shown in dotted area 803 is a similar arrangement of sixteen adder/register chips, and reduces the 4 remaining partial product rows to 2 rows.

[0057] Structure type D, 828 shown in dotted area 804 is an ordinary full binary adder, which reduces the two remaining partial products to the final product.

[0058] Note that the Carries are left-shifted by one position as they are fed forward and that none of the highest-order Carries are connected as discussed earlier. Also observe that the A type structures are offset from each other by twelve bits since each takes a separate twelve-bit slice of the Multiplier. Although error detection logic is not shown in this figure, it may easily be extended from the schemes shown in Figs. 1 and 6 by those skilled in this art.

[0059] In summary, the inputs to a multiplier consists of a 12-bit multiplier (MULTR) and an n-bit multiplicand (MPCD); outputs consist of an n+12 bit sum word (SUM) and an n+12 bit carry word (CY). Parity is included with all input and output data.

[0060] Ranks 0 and 1 gate arrays each consist of (n+6)/6 chips, and perform n-bitx6-bit multiplies. Outputs consist of an n+6 bit sum word and an n+6 bit carry word, and the parity of all carries generated (Plod.

[0061] The higher rank of gate arrays consists of (n+12)/6 chips, and sums four n+12 bit input words resulting in an n+12 bit sum word and an n+12 bit carry word, which are then latched. Parity of the internal carries (P,_c) and of the output carry word (P_oc) are also provided.

[0062] The inputs to the higher rank of gate arrays consist of the sum and carry outputs of ranks 0 and 1 of lower gate arrays. The outputs of rank 0 are logically shifted left six positions relative to those from rank 1 before being fed to the next higher rank.

[0063] The sum and carry words from this higher rank may be summed using a full binary adder to completely resolve the n+12 bit product. If a multiplier of arbitrary size is desired, subsequent ranks of these chips followed by a full binary adder may be used.

[0064] The scheme for checking the parities of the outputs of the multiplier was also presented. Let P_x represent the parity of X.

[0065] For the outputs of rank 0 of the lower gate arrays:

[0066] For the rank of upper gate arrays:

[0067] 



The carry parity (internal or output) is not predictable at any point, but is generated directly from the carries inside each circuit chip. Parity may be generated directly from data using a parity generator (PG) and checked using a parity checker (PC). These functions are logically identical, and are exclusive-OR functions.

[0068] The lower level gate array forms a six bit by six bit square slice of the parallelogram of logical products formed in a binary multiplication. Inputs include 11 bits of a multiplicand and six bits of multiplier; outputs include a six bit sum word and a six bit carry word. Internal to the circuit chip is a tree of carry/save adders. Logical products are formed at the inputs to a first rank of carry-save adders. Stage carry inputs and outputs for extending the carry-save adder array beyond circuit chip boundaries are provided. The parity of the internal carries, output carries and their combination are provided for error checking.

[0069] We have also illustrated the upper level circuit chip referred to earlier which is the 6x4 adder tree register with parity gate array. This circuit chip reduces four six-bit summands to two six-bit outputs. Inputs include four six-bit summands: Al-A6, B1-B6, Cl-C6 and Dl-D6. Outputs include a six-bit sum with a six-bit carry. The circuit consists of a six-bit wide, four-bit deep carry-save adder tree followed by a latch which captures the six-bit sum and six-bit carry outputs of the adder tree and the parity of the carries generated in the adder tree.

[0070] The internal carry parity (latched) and the output carry parity (taken from the latch outputs) are again provided for error checking.

Claims

1. A multiply pipeline building block comprising

a first rank (118) of carry-save adders (300, Figure 2) receiving at their inputs the nxN logical products (AND) of the N multiplicand bits and the n least significant bits of the multiplier to reduce these n partial products of N bits to two partial sums of N+n bits (SUM, CY);

a second rank (114) of carry save-adders (300, Figure 2) receiving at their inputs the nxN logical products (AND) of the N multiplicand bits and the n next significant bits of the multiplier to reduce these n partial products of N bits to two partial sums of N+n bits; and

a final rank (122) of carry-save adders (512-534, Figure 5) receiving the four partial sums of the first and second ranks and further reducing these four partial sums to two partial sums (SUM, CT) each of N+2n bits;

characterized in that the building block further includes:

Means (250-272, 276, 278, 280:536) at each first, second and final rank to calculate the respective parities PACO, PAC1, and PIC of all carries internally generated by the carry-save adders; and

Check means (116, 120, 128, 124) to check the parity relation:

where P_SUM is the parity generated from the final partial sum (SUM) and (P_MULTR^*P_MPCD) is the logical product of the parity of the multiplier with the parity of the multiplicand.

2. A multiply pipeline building block according to Claim 1 in which n=6 and which is arranged to operate on a six-bit by six-bit square slice of the parallelogram of logical products formed in a binary multiplication.

3. A multiply pipeline building block according to Claim 1 or Claim 2 in which the carry-save adders of the final rank include means for providing carries which do not ripple more than one bit position.

Ansprüche

1. Multiplizier-Pipeline-Baueinheit mit

einer ersten Ebene (118) von Übertrag-Sicherstellungs-Addierern (Carry-Save-Addierer) (300, Figur 2), die an ihren Eingängen die logischen nxN-Produkte (AND) aus den N Multiplikanden-Bits und den n niedrigstwertigen Bits des Multiplikators empfangen, um diese n Teilprodukte mit N Bits auf zwei Teilsummen mit N+n Bits (SUM, CY) zu verringern;

einer zweiten Ebene (114) von Übertrag-Sicherstellungs-Addierern (Carry-Save-Addierer) (300, Figur 2), die an ihren Eingängen die logischen nxN-Produkte (AND) aus den N Multiplikanden-Bits und den n nächstwertigen Bits des Multiplikators empfangen, um diese n Teilprodukte mit N Bits auf zwei Teilsummen mit N+n Bits zu verringern; und

einer letzten Ebene (122) von Übertrag-Sicherstellungs-Addierern (Carry-Save-Addierer) (512 bis 534, Figur 5), die die vier Teilsummen der ersten und zweiten Ebene empfangen und diese vier Teilsummen weiter auf zwei Teilsummen (SUM, CT) mit jeweils N+2n Bits verringern;

dadurch gekennzeichnet, daß die Baueinheit weiterhin enthält:

Einrichtungen (250 bis 272, 276, 278, 280: 536) jeweils auf der ersten, zweiten und letzten Ebene zur Berechnung der jeweiligen Paritäten PACO, PAC1 und PIC von allen durch die Übertrag-Sicherstellungs-Addierer intern erzeugten Überträgungen; und

Prüfeinrichtungen (116, 120, 128, 124) zur Prüfung der Paritätsbeziehung:

wobei P_SUM die aus der letzten Teilsumme (SUM) erzeugte Parität und (PMULTR*PMPCO) das logische Produkt der Parität des Multiplikators mit der Parität des Multiplikanden ist.

2. Multiplizier-Pipeline-Baueinheit nach Anspruch 1, in der n=6, und die so angeordnet ist, daß sie auf einer 6 Bit auf 6 Bit Quadratischeibe des Parallelogramms von in einer binären Multiplikation gebildeten logischen Produkten arbeitet.

3. Multiplizier-Pipeline-Baueinheit nach Anspruch 1 oder Anspruch 2, in der die Übertrag-Sicherstellungs-Addierer der letzten Ebene Einrichtungen für die Lieferung von Überträgen enthalten, die auf nicht mehr als eine Bit-Position durchschlagen.

Revendications

1. Module pipeline multiplicateur, comprenant:

un premier niveau (118) d'additionneurs à sauvegarde de report ou de retenue (300, fig. 2) qui reçoivent à leurs entrées les nxN produits logiques (ET) des N bits du multiplicande et des n bits de plus faible poids du multiplicateur, pour réduire ces n produits partiels de N bits en deux sommes partielles de N+n bits (SUM, CY);

un deuxième niveau (114) d'additionneurs à sauvegarde de report (300 fig. 2) qui reçoivent à leurs entrées les nxN produits logiques (ET) des N bits du multiplicande et des n bits de poids suivant du multiplicateur, pour réduire ces n produits partiels de N bits en deux sommes partielles de N+n bits; et

un niveau final (122) d'additionneurs à sauvegarde de report (512-534, fig. 5) qui reçoivent les quatre sommes partielles des premier et deuxième niveaux et réduisent encore ces quatre sommes partielles en deux sommes partielles (SUM, CT) de N+2n bits chacune;

caractérisé en ce qu'il comprend en outre:

des moyens (250-272, 276, 278, 280:536) dans chacun du premier niveau, du deuxième niveau et du niveau final pour calculer les parités respectives PACO, PAC1 et PIC de tous les reports générés intérieurement par les additionneurs à sauvegarde de report; et

des moyens de contrôle (116, 120, 128, 124) pour contrôler la relation de parité

dans laquelle P_SUM est la partié produite à partir de la somme partielle finale (SUM) et (PMULTR*PMpcD) est le produit logique de la parité du multiplicateur avec la parité du multiplicande. 2. Module pipeline multiplicateur selon la revendication 1, dans lequel n=6 et qui est agencé de façon à opérer sur une tranche carrée de six bits sur six bits du parallélogramme de produits logiques formé dans une multiplication binaire.

3. Module pipepline multiplicateur selon la revendication 1 ou 2, dans lequel les additionneurs à sauvegarde de report du niveau final contiennent des moyens pour fournir des reports qui ne se transmettent pas ou qui ne se reportent pas au-delà de plus d'une position binaire.

Drawing