Dual port voltage controlled emitter coupled multivibrator

Abstract

 A voltage controlled oscillator includes an emitter coupled multivibrator in which a capacitor determines the frequency of oscillation along with a pair of load resistors (14, 15) and a pair of current sources (16, 17). A differential amplifier (20, 21) is coupled to operate in parallel with the multivibrator and its tail current is oper­ated differentially, with respect to the currents in the pair of sources (16, 17), in response to the input voltage at a first modulation input port. Thus, a constant current flows in the multivibrator loads even when the frequency is modulated. A second input port is coupled to vary the tail current in the differential amplifier to comprise a dual port control of the voltage controlled oscil­lator. The circuit can be operated at a relatively low supply voltage and can be temperature compensated. Furthermore, the input ports can include circuitry having a logarithimic response for digital signaling processing.

Description

[0001] The invention relates to voltage controlled oscil­lator (VCO) circuits in which the frequency of oscillation is a function of an applied voltage. Such oscillators find use in phase locked loop (PLL) systems where an oscillator is forced to oscil­late at a frequency and phase that is related to an input signal. For IC applications the oscillator of choice is typically the well-­known emitter-coupled multivibrator. This circuit employs all NPN transistors and is thus capable of operating at relatively high frequencies. This basic circuit is the subject of US-A- 3,857,110. A improved version is disclosed in US-A- 4,468,636

[0002] The teaching in these two patents is incorporated here­in by reference.

[0003] One of the remaining problems associated with the prior art VCO's is their limitation of a single input control voltage for controlling the operating frequency and phase. The present invention as defined in claim 1 is based on the discovery that where a system includes more than one PLL and the individual loops must be coupled together, the VCO can perform this function if it has plural inputs. Desirably, these inputs are iso­lated and can enjoy predetermined voltage-to-frequency sensitivity so that system performance can be predetermined.

[0004] The circuit of the invention to provide a VCO in which a constant current flows while being modulated.

[0005] The invention further provide a VCO circuit which has more than one frequency-sensitive input voltage port.

[0006] It is still another advantage of the invention to employ a VCO circuit that has plural voltage inputs and a config­ uration in which oscillation frequency responds to a differential input voltage which partitions oscillator current between active and passive portions.

[0007] The plural input VCO of the invention operates at a single +5V supply and can easily be temperature compensated.

[0008] It is possible to configure the modulation input stage to provide a logarithmic digital signal processing function.

[0009] These and other objects are achieved in a circuit as follows. An emitter coupled multivibrator includes a capacitor that can be charged in two directions as a function of the currents in a pair of constant current elements which are operated as a function of an input voltage and coupled to the emitters of a pair of oscillator transistors. The multivibrator includes a parallel connected differential feedback stage which has its tail current operated differentially with respect to the constant current elements. The differential amplifier has its inputs and outputs connected in parallel with the oscillator transistors. A pair of emitter followers cross-couple the oscillator transistors conven­tionally to create a high gain multivibrator configuration. The output signal can be taken from the oscillator transistor collec­tors as a square wave. Alternatively, a sawtooth output can be taken from the emitters. The tail current of the differential feedback stage can be obtained from a second differentially con­trolled current supply and can be modulated by a second voltage input which also acts to vary the oscillator frequency. These two isolated voltage inputs can each be designed to provide the desired control sensitivity. As a general consideration, the con­stant current modulation elements in the oscillator transistor emitters provide the higher frequency-to-voltage sensitivity while the differential amplifier feedback current control provides a vernier frequency/phase control action. The voltage inputs can include circuitry that also provides a logarithmic digital signal processing function.

Figure 1 is a schematic diagram showing the circuit of the invention.

Figure 2 is a schematic diagram of an alternative embodiment of the invention.

[0010] In the circuit of figure 1 a power supply is con­nected + to V_CC terminal 10 and - to ground terminal 11. The heart of the circuit is oscillator transistors 12 and 13. Their collectors are returned to +V_CC by way of matched load resistors 14 and 15 respectively. Their emitters are returned to ground by way of constant current transistors 16 and 17 which have their bases coupled together to control terminal 18. Transistors 16 and 17 have their emitters commonly connected to the collector of con­stant current supply transistor 19 and their collectors connected to a frequency determining capacitor 28.

[0011] Transistors 20 and 21 form a differential amplifier with degeneration resistors 22 and 23 in their respective emitters. Transistors 24 and 25 in parallel balance transistors 16 and 17 and act to provide the tail current flowing in transistors 20 and 21. Since the bases of transistors 24 and 25 are connected to input terminal 26 the tail current can be modulated by the differential input coupled between terminals 18 and 26. Since transistor 19 provides a constant current in the combination of transistors 16, 17, 24 and 25, the differential control terminals will act to direct the current flowing in transistor 19 to either oscillator transistors 12 and 13 or differential amplifier transistors 20 and 21.

[0012] The bases and collectors of transistors 20 and 21 parallel the equivalent elements of oscillator transistors 12 and 13 respectively. The collectors of transistors 12 and 20 directly drive emitter follower transistor 26 which in turn couples to the bases of transistors 13 and 21. Likewise, emitter follower tran­sistor 27 couples the collectors of transistors 13 and 21 to the bases of transistors 12 and 20. This cross-coupling will render transistors 12 and 13 oscillatory, as is well-known in the art as taught in US-A- 3,857,110. Capacitor 28, which is connected between the emitters of transistors 12 and 13, will charge and discharge linearly which produces a sawtooth waveform thereacross. When transistors 16 and 17 have their currents modu­lated to very the frequency of the VCO, the current changes are reflected in transistors 20 and 21. Thus, the total current flow is constant and oscillator gain is constant.

[0013] Transistor 29, with its emitter resistor 30, pro­vides a constant current load for emitter follower transistor 26 and transistor 31, with its emitter resistor 32, provides a con­stant current load for emitter follower transistor 27. Emitter follower 33 couples the collectors of transistors 13 and 21 to output terminal 34 and emitter follower transistor 35 couples the collectors of transistors 12 and 20 to output terminal 36. Thus, the output at terminals 34 and 36 is a square wave. Constant current transistor 37 with its emitter resistor 38 acts as a load for transistor 33 and constant current transistor 39, with its emitter resistor 40 acts as a load for transistor 35. The bases of transistors 29, 31, 37 and 39 are operated at V_BG above the ground potential by connecting a bandgap level voltage source (not shown) to bias terminal 41. This source is configured so that the potential at terminal 41 will decrease with temperature. It can be seen that as V_BG falls with temperature, the V_BE of each of the transistors will also fall, thus making the potentials across the associated emitter resistors substantially independent of tem­perature. This means that the currents in transistors 29, 31, 37 and 39 are substantially temperature independent and of a value determined by the emitter resistors.

[0014] Diode connected transistor 44 is returned to V_BG terminal 41 by resistor 43. Thus I₁, which flows in resistor 43, is:
I₁ = (V_BG-V_BE44)/R43
where R43 is the value of resistor 43.

[0015] Since both V_BG and V_BE fall with increasing temperature, their difference will cancel and the magnitude current I₁ will not only be determined by resistor 43, its temperature coefficient will be determined by the temperature coefficient of resistor 43. Transistor 19 is made to have four times the area of transistor 44 and is connected as a current mirror that will sink 4I₁. Transistor 48, which has one-half of the area of transistor 44, is connected as a current mirror that will sink I₁/2.

[0016] As shown above, I₁ has a temperature coefficient that is determined by the temperature coefficient of resistance of resistor 43. This is selected to match that of resistors 14 and 15 in such a way that the frequency of the VCO will not vary signifi­cantly with temperature over the operating temperature range of -55°C to 125°C. Thus, while resistors 14 and 15 will vary with temperature and will act to change oscillator frequency, the temperature coefficient of resistor 43 will offset temperature drift.

[0017] Under quiescent conditions, when terminals 18 and 26 are shorted together, I₁ will flow in each of transistors 16, 17, 24 and 25. It has been determined that the free running oscillator frequency for the circuit of figure 1 is:
f₀ ≈ 1/_17RC
wherein R is the value of resistors 14 and 15 and C is the value of capacitor 28.

[0018] This frequency varies very little over the range from -55°C to over 125°C because of the temperature current characteristics of I₁ and the VCO bias currents as described above.

[0019] If terminal 18 is raised and terminal 26 is lowered differentially, conduction in transistors 16 and 17 will be increased while the currents flowing in transistors 24 and 25 will similarly be decreased. This will cause the charge cycle for capacitor 28 to speed up thereby producing an oscillator frequency increase. A lowering of the voltage at terminal 18, along with a rise at terminal 26, will lower frequency. The frequency-to-voltage relationship is linear and a relatively wide range control is avail­able. It can be seen that as the current in oscillator transistors 12 and 13 is increased the current in differential amplifier tran­sistor 20 and 21 will decrease a like amount. Thus, as the oscil­lator frequency is modulated or varied the currents flowing in resistors 14 and 15 will be constant and the output amplitude will remain constant.

[0020] Transistors 60 and 45 operate to provide a vernier frequency control input. They are connected differentially and their bases are respectively connected to input terminals 46 and 47 which comprise a second differential input port. The constant tail current for transistors 60 and 45 is provided by transistor 48 which has its base returned to the bases of transistor 19 and 60. Typically, transistor 48 is scaled to have one-half of the area of transistor 44 so that I₁/2 flows therein. The collector of transistor 60 is connected to the collectors of transistors 24 and 25 so that it will conduct a portion of the tail current flowing in differential transistors 20 and 21. The modulation is achieved by steering more or less current from common collectors of transis­tors 24 and 25 by changing the relative voltage at bases of transis­tors 60 and 45. The finite change in voltage is reflected, as des­cribed above for terminals 18 and 26, to appear across capacitor 28. Any such voltage change will result in a finite frequency change.

[0021] Diode connected transistors 49 and 50 return the collector of transistor 45 to +V_CC and are present to balance the control action of transistors 60 and 45. It will be noted that since transistor 19 is returned to -V_EE, the emitters of tran­sistors 16, 17, 24 and 25 can be lowered closed to V_SAT or a fraction of a volt. This maximizes the circuit common mode range and permits a low supply voltage. Typically, the circuit will operate at five volt supply.

[0022] Figure 2 is a schematic diagram of an alternative embodiment of the invention. Where the various parts perform as those of figure 1, the same designations are used. The bias net­work is virtually identical. the collector of transistor 45 is directly returned to + V_CC rather than via diodes. This will have the effect of slightly reducing the accuracy of current steering, but will otherwise hve little effect. A two times area transistor 48 provides 2I₁ as tail current for transistors 60 and 45. This current distribution slightly increases the sensi­tivity of the vernier control input at terminals 46 and 47 over that of figure 1.

[0023] The main difference is how the main control input at terminals 18 and 26 is applied to the VCO. The input circuit provides level shifting, a high input impedance and a digital signal processing function. The input circuit operates as follows. The I₁ flowing in transistor 44 is mirrored in a four times area transistor 51 as 4I₁. This current is caused to flow in transis­tors 52-55. Transistors 52 and 53 bias transistors 16 and 17 in the VCO while transistors 54 and 55 bias transistors 24 and 25. Input transistors 56 and 57 operate from the main control input terminals 18 and 26 as emitter followers. Transistor 56 drives transistors 52 and 53 by way of level shifting diode connected transistor 58. Transistor 57 drives transistors 54 and 55 through level shifting diode connected transistor 59. Thus, the differen­tial input signal voltage at terminals 18 and 26 will frequency modulate the VCO as described in connection with figure 1. However, the input impedance of the main control input is high and will not appreciably load the input source.

[0024] If digital control information is applied to control terminals 18 and 26 the circuit also responds logarithmically to produce a current related input voltage. Such digital signal pro­cessing is disclosed in US-A- 4,001,603 and its teaching is incorporated herein by reference. Transistors 52 and 53 operating as a unit will develop a voltage related to the cur­rent flowing in them as will transistors 54 and 55. These tran­sistors will develop a ΔV_BE which is related to the differential currents as follows:

where: V_T is the thermal voltage and the currents are those of the indicated transistors. It can be seen that ΔV_BE will be log related to the current ratio and is applied as a differential input to transistors 16-17 and 24-25. This sort of response has benefit in digital input signal processing as set forth in the referenced patent.

[0025] It is to be understood that, while the input circuit in figure 2 is shown only at the main control input, an identical input control circuit can, if desired, be coupled between terminals 46 and 47 and the bases of transistors 60 and 45.

Example

[0026] The circuit of figure 1 was fabricated using conven­tional monolithic epitaxial silicon PN junction isolation construc­tion parts. Capacitor 28 was fabricated on chip by employing a pair of square metal plates 195 microns on a side separated by an oxide 0.78-microns thick. The nominal capacitance was close to 1.86 picofarads. Resistors 14 and 15 were each 274.5 ohms and resistors 22 and 23 were each 100 ohms. All other resistors had a value of about 2000 ohms which made I₁ equal to about 0.3 microamperes at 300°K. The NPN transistors were operated at a current density of about 80 microamperes per square micron. The circuit was operated with a 5 volt power supply and the operation was compatible with standard ECL specifications. The free running VCO operated at 125.3 MHz and could easily be pulled to exactly 125 MHz. The modulation sensitivity of terminals 18 and 26 was measured at 0.327 MHz per millivolt of differential signal. At terminals 47 and 46 the differential sensitivity was 0.152 MHz per millivolt. The VCO has a lock range of about 6.4 MHz and a capture range of about 0.3 MHz.

[0027] The invention has been described and an example detailed. When a person skilled in the art reads the foregoing description, alternatives and equivalents, within the spirit and intent of the invention, will be apparent. For example, additional modulation ports could be added if desired. Accordingly, it is intended that the scope of the invention be limited only by the claims that follow.

Claims

1. In an emitter coupled multivibrator circuit comprising a pair of differentially operated transistors, a capacitor coupled between the emitters of said pair of transistors, load means coupled between the collectors of said pair of tran­sistors and a first power supply reference terminal, a pair of current sources coupled between said emitters of said pair of transistors and a second power supply terminal, a pair of emitter followers cross-coupled between the collectors and bases of said pair of transistors to provide oscillatory feedback therebetween, and a first modulation port for controlling the conduction of said current sources for varying the frequency of oscillation of said pair of transistors, the improvement comprising:
a first differential amplifier having differ­ential input terminals coupled to the bases of said pair of transistors, differential outputs coupled to the collectors of said pair of transistors and a third constant current source coupled to pass the tail current in said first differential amplifier to said second power supply terminal; and
means responsive to the voltage of said first port for modulating said tail current in said differential amplifier differentially with respect to the currents in said pair of current sources.

2. The improvement of claim 1 further comprising a second modulation port with means for modulating said current in said differential amplifier as a function of the voltage at said second port.

3. The improvement of claim 2 wherein each of said modulation ports include means for responding to differential inputs.

4. The improvement of claim 2 wherein all three of said constant current sources are commonly coupled to said second power supply terminal through a fourth constant current source.

5. The improvement of claim 3 wherein said second modulation port comprises a second differential amplifier having a pair of input terminals comprising said second port input, an output coupled to the juncture of said third current source and the tail current connection of said first differential amplifier and a tail current supply coupled to said second power supply terminal.

6. The improvement of claim 3 wherein said means for responding to differential inputs further includes means for responding logarithmically to the input voltage whereby nonlinear response to a digital input is achieved.

Drawing