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(11) | EP 0 372 547 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Bias circuit for a subranging analog to digital converter |
| (57) Through first and second external terminals (T₂, T₃), fixed potentials are applied
to both ends of a first stage of ladder resistor network. A second stage of ladder
resistor network is connected at one end to a second transistor (Q₂). The first external
terminal (T₂) is connected to a first transistor (Q₅) through a resistor (RM), the resistor (RM) and the resistors of the first and second stage of ladder resistor networks being
of the same kind. A positive input terminal of an operational amplifier (1) is connected
to a node (A) between the resistor (RM) and the first transistor (Q₅). A negative input terminal of the amplifier (1) receiving
a reference voltage is connected to the second external terminal (T₃). The first and
second transistors (Q₂, Q₅) are driven by the output signal of the amplifier (1).
The amplifier (1) cooperates with the first transistor (Q₅) such that a potential
at the node (A) is equal to the potential of the reference voltage. As a result, a
current (I₂/M (M = constant)) flowing through the resistor (RM) is proportional to a current (I₂) flowing through the first stage of ladder resistor
network. Since the current, which is based on the operation of the second transistor
(Q₂), flows into the second stage of ladder resistor network, the current flowing
through the first transistor (Q₅) is proportional to a current (I₃) flowing through
the second stage of ladder resistor network. |