(19)
(11) EP 0 517 013 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
09.02.1994 Bulletin 1994/06

(43) Date of publication A2:
09.12.1992 Bulletin 1992/50

(21) Application number: 92108062.8

(22) Date of filing: 13.05.1992
(51) International Patent Classification (IPC)5G06F 9/38, G06F 15/78
(84) Designated Contracting States:
DE FR GB NL

(30) Priority: 14.05.1991 JP 107721/91

(71) Applicant: NEC CORPORATION
Tokyo (JP)

(72) Inventor:
  • Nishikawa, Takeshi
    Minato-ku, Tokyo (JP)

(74) Representative: VOSSIUS & PARTNER 
Postfach 86 07 67
81634 München
81634 München (DE)


(56) References cited: : 
   
       


    (54) Information processing system capable of operating a plurality of vector pipeline sets in two different modes


    (57) In an information processing system including a vector processor (132) which has a plurality of vector pipeline sets operable under control of an instruction controller (32,33) the vector pipeline sets are operable in a parallel mode or an individual mode with reference to an operation mode flag kept in a mode flag register (35). The instruction controller includes a plurality of vector instruction control units (42) which correspond to the respective vector pipeline sets and which monitor states of the vector instruction control units one another to detect whether or not an error takes place in each of the vector instruction control units. The vector pipeline sets are connected to a vector data memory (21) through a pipeline crossbar switch to fetch a common data signal from the vector data memory on demand.







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