Background of the Invention
(1) Field of the Invention
[0001] The present invention relates to a semiconductor integrated circuit apparatus using
a dielectric separation substrate, particularly to a semiconductor integrated circuit
apparatus having high withstand voltage and high integration density.
(2) Description of the Prior Art
[0002] A dielectric separation substrate having the high withstand voltage and capable of
downsizing the region for separating elements are presently used as a substrate of
a semiconductor integrated circuit dealing high voltages, in stead of a pn separation
method. An existing dielectric separation substrate has the constitution wherein semiconductor
islands such as n- type semiconductor islands each of which are surrounded by oxide
films (Si0
2) are embedded together in one side of a supporter made from poly-silicon and high
impurity concentration layers (n
+ ) are formed along with the oxide film at the places adjoining other islands for suppressing
the elongation of a depletion layer. The dielectric separation substrate has the following
problems. The first problem is one related to product processing. The substrate producing
process comprises the steps of;
{1} forming V character form grooves on one side of a n- type semiconductor substrate
by the anisotropic etching using a mixture of potassium hydroxide(KOH), water and
N-propanol,
{2} injecting impurities to make the n+ layers on the faces of the grooves and the side of the semiconductor substrate,
{3} forming oxide films along with on the faces of the grooves and one side of the
semiconductor substrate,
{4} accumulating poly-silicon on the oxide films, and
{5} chipping down the other side of the semiconductor substrate to the bottom of the
grooves and forming the semiconductor islands separated by the oxide films.
[0003] The above-mentioned producing process of the dielectric separation substrate has
the first problem that the producing process is not easy since it is necessary to
form a thick poly-silicon layer. The second problem is that the element integration
density decreases in accordance with increase of the withstand voltage. It is needed
to enlarge the region of the depletion layer for increasing the withstand voltage,
which requires the formation of deep semiconductor islands. Since the side face of
the semiconductor island makes an angle of 55 to its exposed face due to the above-mentioned
anisotropic etching, the area of the exposed face becomes larger and the integrated
density decreases as the depth of the semiconductor island increases. As such a dielectric
separation substrate as solves the first problem, the constitution of the substrate
described in a Japan Patent Laid Open 292934/1986 is known. The dielectric separation
substrate has the constitution wherein the semiconductor islands are made more shallow,
the poly-silicon layer is formed a little thicker than it can bury the grooves and
the semiconductor substrate having a oxide film on its surface is stuck on the poly-silicon
layer. By the constitution, the producing process becomes easier since accumulation
of the deep poly-silicon is not needed. However, the dielectric separation substrate
has the defect that the integration density considerably decreases in accordance with
increase of the withstand voltage, which is explained by Fig.18. In the figure, a
semiconductor island 100, a poly-silicon layer 101 in which the semiconductor island
100 is buried and supported by a silicon oxide film 102, a semiconductor substrate
103 stuck to a poly-silicon layer 101 with a silicon oxide film 104 between, etc.
are shown. For a case of a diode, the semiconductor island 100 includes a n- type
region 100a, and a p
+ type region 100b and a n
+ type region 100c which are formed separated from each other at the exposed face of
the n- type region. An anode electrode 105 and a cathode electrode 106 are connected
by an ohmic contact to the p
+ type region 100b and the n
+ type region 100c, respectively. In the constitution, when the reverse bias voltage
is applied to the pn junction formed between the p
+ region 100b and the n- type region 100a by the anode electrode 105 and the cathode
electrode 106, a depletion layer is considerably extended to the n- type region side.
Since the depth of the semiconductor island 100 is shallow, the depletion layer can
not be extended to the perpendicular direction but to the lateral direction. In the
case, the field strength and the equipotential lines are as shown in the figure. An
unusual high peak of the field strength appears in the vicinity of the boundary between
the n- type region 100a and the n
+ type region 100c where the extension of the depletion layer is stopped. Decreasing
the interval between the p
+ type region 100b and the n
+ type region 100c can suppress the peak, however, which makes the semiconductor larger
and reduces the integration density.
[0004] As mentioned above, by the semiconductor integrated circuit apparatus using the existing
dielectric separation substrate, it is impossible to realize the high withstand voltage
and the high integration density at the same time since increasing the withstand voltage
impedes the high integration density and vice versa. The increasing trend of the commercial
power voltage from 100 V to 200 V renders it impossible to avoid the increase of the
withstand voltage in the field of the semiconductor integrated circuit using a dielectric
separation substrate. The decrease of the integration density of the semiconductor
integrated circuit apparatus means the functional deterioration of one-chip circuit
and brings about the loss of the largest merit in using an integrated circuit apparatus
for an electric circuit.
Summary of the Invention
(1) Objects of the Invention
[0005] The present invention has been achieved in consideration of the above-mentioned problems
and is aimed at providing a new semiconductor integrated circuit using a dielectric
separation substrate for realizing the high withstand voltage and the high integration
density.
(2) Method Solving the Problems
[0006] One of the features, the first features, of the present invention is that a semiconductor
integrated circuit apparatus of the present invention has the constitution comprising
a means for extending a depletion layer of a main junction beyond a insulating layer
sandwiched between a supporter and semiconductor islands to a supporter by applying
the bias voltage to the supporter and the semiconductor islands. That is, in the constitution,
an electrode is provided at the surface of the supporter and connected to a main electrode
of the selected island. The above-mentioned main junction is the pn junction to which
the reverse bias voltage for securing the withstand voltage of the semiconductor element
is applied.
[0007] The second features is that the impurity density and the thickness of the region
between the bottom part of the semiconductor island and the circuit element regions
is set so as the region between the bottom part of the semiconductor island and the
circuit element regions is fully depleted by lower voltage than the avalanche breakdown
occurs in a semiconductor island supported by the supporter with a insulating film
between. That is, the distance between the bottom part of the semiconductor island
and the main junction of a selected semiconductor island supported by the supporter
with the insulating film between is set less than J2xesixV/(qxNd) (
ESi: dielectric constant of Si, q: elementary charge, Nd: impurity concentration of the
semiconductor island) when the withstand voltage of the circuit element is V volts.
The supporter used for the semiconductor integrated circuit apparatus of the present
invention is made by such material or layer composition as the laminate piled up with
the first semiconductor layer of the first type conduction and the second semiconductor
layer of the first type conduction adjoining the first semiconductor, having higher
impurity concentration than the first semiconductor, the laminate having a insulating
material layer sandwiched between the first semiconductor layer and the second semiconductor
layer, the transformed laminate of the above-mentioned laminates and so forth. And
silicon is used as the first semiconductor and poly-silicon or mono-crystal silicon
is used as the second semiconductor.
[0008] Therefore, the present invention has the following effects:
{1} It is possible to reduce the area of a semiconductor island and attain the high
integration density due to the decrease of the field strength at the surface of the
semiconductor island.
{2} It is possible to reduce the area of a semiconductor island and attain the high
integration density due to the considerable decrease of the depth of a semiconductor
island by the extension of the depletion layer beyond the insulating film into the
supporter.
{3} It is possible to decrease the field strength at the surface of the semiconductor
island and attain the high withstand voltage by the extension of the depletion layer
beyond the insulating film into the supporter.
{4} It is possible to bring about easy producing process of a dielectric separation
substrate due to the considerable decrease of the depth of a semiconductor island.
Brief Description of the Drawings
[0009]
Fig.1 is a sectional outline drawing showing the first embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.2 is a sectional outline drawing showing the second embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.3 is a plane drawing of the semiconductor integrated circuit apparatus by the
present invention shown in Fig.2.
Fig.4 is a sectional outline drawing showing the third embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.5 is a sectional outline drawing showing the forth embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.6 is a sectional outline drawing showing the fifth embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.7 is a plane drawing of the semiconductor integrated circuit apparatus by the
present invention shown in Fig.6.
Fig.8 is a sectional outline drawing showing the sixth embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.9 is a sectional outline drawing showing the seventh embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.10 is a sectional outline drawing showing the eighth embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.11 is a sectional outline drawing showing the ninth embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.12 is a sectional outline drawing showing the tenth embodiment of the semiconductor
integrated circuit apparatus by the present invention.
Fig.13 is a process diagram showing an example producing method of the dielectric
separation substrate used to the semiconductor integrated circuit apparatus by the
present invention.
Fig.14 is an outline drawing showing an example of the monolithic inverter IC using
the semiconductor integrated circuit apparatus by the present invention.
Fig.15 is an outline drawing showing another example of the monolithic inverter IC
using the semiconductor integrated circuit apparatus by the present invention.
Fig.16 is a layout figure of the monolithic inverter IC shown by Figs.14 and 15.
Fig.17 is a perspective outline figure showing the method for putting the semiconductor
integrated circuit by the present invention into a package.
Fig.18 is a sectional outline drawing showing an existing semiconductor integrated
circuit apparatus.
Detailed Description of the Embodiments
[0010] Hereinafter, detail of the present invention is explained based on embodiments referring
to drawings.
(Embodiment 1)
[0011] Fig.1 is a sectional outline drawing showing the embodiment 1 of the semiconductor
integrated circuit( abbreviated to SIC ) apparatus by the present invention. As shown
in Fig.1, the SIC apparatus comprises a semiconductor island( abbreviated to merely
island ) 1 and a supporter 2 including a poly-silicon layer 22 supporting the island
1 with a silicon oxide film between, and a n type semiconductor substrate 23 having
higher impurity concentration than the poly-silicon layer 22 stuck to the face opposite
to the exposed surface of the island 1 buried in the poly-silicon 22. And the island
1 comprises the first n type layer 11 extending inside from the exposed surface, the
second p type layer 12 of higher impurity concentration than the first n type layer
11 extending inside from the surface of the first layer 11 and forming the pn junction
J with the first layer 11, and the third n type layer 13 of higher impurity concentration
than the first layer 11 extending inside at a place apart from the second layer 12
of the surface of the first layer 11. And reference numeral 31 designates the first
main electrode ohmicly contacted to the second layer 13, 32 the second main electrode
ohmicly contacted to the third layer 13, and 33 a auxiliary electrode ohmicly contacted
to a semiconductor substrate 23 which is connected to the second main electrode 32
by a lead 34 and kept in the same potential as the second main electrode 32. In the
above-mentioned constitution, by applying the voltage having such polarity as reversely
biases the pn junction J (where the second main electrode 32 has the positive potential
and the first main electrode 31 the negative potential) to the first main electrode
31 and the second main electrode 32, the depletion layer is formed around the pn junction
J. Since the depletion layer mostly extends to the side of the first layer 11 of low
impurity concentration and the auxiliary electrode 33 has the same potential as the
second electrode 32, the perpendicular extension of the depletion layer becomes larger
and the depletion layer extending to the side of the first layer 11 goes beyond the
silicon layer 21 into the poly-silicon layer 22 as shown by the dotted lines in the
figure. Thereby, the lateral extension of the depletion layer at the surface of the
island 1 is suppressed and the peak of the field strength at the vicinity of the boundary
of the third layer 13 and the first layer 11 remarkably decreases. The reason why
the lateral extension of the depletion layer is suppressed is because the quantity
of electric charge swept out by the extension of the depletion layer are constant
if the pn junction area and its potential are kept constant and the lateral extension
of the depletion layer at the surface of the island 1 is reduced in inverse proportion
to the perpendicular extension. By the above-mentioned operations of the SIC apparatus
of the present invention, the following effects are expected:
{1} It is possible to reduce the distance between the third layer 13 and the first
layer 11 and consequently the area of a island 1, and to attain the high integration
density due to the decrease of the field strength at the surface of the island 1.
{2} It is possible to reduce the area of a island 1 and to attain the high integration
density due to the considerable decrease of the depth of the first layer 11 by the
extension of the depletion layer beyond the silicon oxide film 21 into the poly-silicon
layer 22.
{3} It is possible to decrease the field strength at the surface of the island 1 and
to attain the high withstand voltage by the extension of the depletion layer beyond
the silicon oxide film 21 into the poly-silicon layer 22.
[0012] In the constitution, the impurity concentration of the first layer 11 and the thickness
of the region between the bottom part of the second layer 12 and the silicon oxide
film 21 are set so as the region between the bottom part of the second layer 12 and
the silicon oxide film 21 is fully depleted by lower voltage than the avalanche breakdown
occurs in the first layer 11. That is, if the voltage by which the avalanche breakdown
occurs in the first layer 11 is Vb, the impurity concentration of the first layer
11 is Nd, and the perpendicular distance between the bottom of the second layer 12
and the silicon oxide film 21 is L, then the values of Vb, Nd and L are determined
so as they satisfy Eq.(1).
[0013] Since Vb, Nd and L are determined so as to satisfy Eq.(1), the region between the
bottom part of the second layer 12 and the silicon oxide film 21 is fully depleted
by lower voltage than the avalanche breakdown occurs in the first layer 11 and the
depletion layer extends beyond the silicon oxide film 21 into the poly-silicon layer
22. And since the applied voltage is divided and each of the divided voltages is applied
to the first layer 11, the silicon oxide film 21 and the poly-silicon layer 22, respectively,
the voltage applied to the first layer 11 is lower than the voltage applied to the
whole apparatus and the increase of the withstand voltage can be realized in spite
of the thinner first layer 11. Further, it is preferable that the depletion layer
extending in the poly-silicon layer 22 reaches the semiconductor substrate 23. Thereby,
the ratio of the applied voltage that the poly-silicon layer 22 shares becomes larger
and the withstand voltage is further improved. Now, the potential E1 applied to the
first layer 11 is expressed by the following equations;
where t
ox is the film capacitance thickness of the silicon oxide film 21, Lp
oly is the thickness of the poly-silicon layer 22,
EOX is the dielectric constant of the silicon oxide film 21, and V is the applied voltage.
[0014] In the existing SIC apparatus, the thickness of the first layer is 50 µm and the
withstand voltage is 700 V. Then, the potential of the avalanche breakdown becomes
14 V/jn.m. By using the equation of Emax, and letting t
ox=2 µm and Lpoly = 45 µm, then the thickness of the first layer by the present invention
is calculated as 4.3 µm from Eq.(2) - Eq.(4) and reduced to the 1/10 thickness of
the existing one. Since the silicon is scraped with the angle of 55 degrees by using
the KOH solution as the etching fluid, the surface area of the separation region becomes
larger than by vertical etching. In the present invention, the enlargement by the
etching using KOH solution is not so much due to the thin thickness of the mono-crystal
region in the present invention. So the thickness of the separation region is reduced
from 49 µm ( existing value: 50 µm / tan 55
° ) to 4
/1.m ( value by the present invention ). It is made known by Eq.(2) - Eq.(4) that the
same withstand voltage can be obtained even if the thickness of the first layer 11
is reduced, as the thickness of the poly-silicon increases. Therefore, it is desirable
to increase the thickness of the poly-silicon layer within the limits of producing
time and cost. And, from the relation of 14V/am between the withstand voltage and
the thickness of the first layer 11, if the withstand voltage is 700 V, then the thickness
of the first layer 11 in the existing one is calculated as 50( = 700x 1/14) µm which
is larger than that of the present invention SIC apparatus. Since the supporter of
the semiconductor substrate 23 has higher impurity concentration than the poly-silicon
layer 22, the depletion layer extending from the pn junction is stopped at the semiconductor
substrate 23, which prevent the depletion layers extending from the adjoining islands
from being connected and interfering each other in the semiconductor substrate 23.
And the high density impurity in the semiconductor substrate 23 reduces the contact
resistance of the auxiliary electrode 33 thereto. Further, the voltage for fully depleting
the first layer 11 between the bottom of the second layer 12 and the silicon oxide
film 21 is desirably set to the rated voltage. Then, since the avalanche voltage is
higher than the rated voltage, higher integration density can be realized by making
the thickness of the first layer further thinner. Now, it is needed to determine the
distance L
23 between the second layer 12 and the third layer 13 so as the avalanche voltage is
higher than the rated voltage, since the whole potential between the second layer
13 and the third layer 13 is applied to the first layer 11. That is, if the rated
voltage is designated by Vs, L
23 is determined by Eq.(5).
[0015] Then, the distance L
23 is set so as to be larger than the thickness of the first layer 11. Since the depletion
layer extends into the poly-silicon layer 22 before the avalanche breakdown occurs
thereby, the same withstand voltage can be secured even if the first layer 11 is set
thinner,so the integration density is further improved. Although the magnitude of
the voltage is not restricted if only the voltage applied to the auxiliary electrode
33 has such polarity as inversely biases the pn junction J, the applied voltage is
preferably set close to the rated voltage in order to fully extend the depletion layer
into the poly-silicon layer 22.
(Embodiment 2)
[0016] Fig.2 is a sectional outline drawing showing the embodiment 2 of the SIC apparatus
by the present invention. The embodiment 2 is different from the embodiment 1 in that
the semiconductor element formed at the island 1 is MOSFET(Metal Oxide Semiconductor
Field Effect Transistor), the forth n type layer 14 having higher impurity concentration
than the first layer 11 is formed between the first layer 11 and the silicon oxide
film 21 at the side of the island 1, and a silicon oxide film 24 is provided between
the poly-silicon layer 22 and the semiconductor substrate 23. In the figure, reference
numeral 15 designates the fifth n type layer having higher impurity concentration
than the second layer 12 which has the role of a source formed in the second layer
12, and 35 a gate electrode of poly-silicon provided on a insulating film 41 formed
on the second layer 12 between the first layer 11 and the fifth layer 15. The gate
electrode 35 extends on the insulating film 41 formed on the first layer 11 in the
lateral direction and has the role of a field plate for relaxing the formed high field.
The part of the insulating film 41 to which the second layer 12 is contacted is made
thinner than the other part. The first main electrode 31 is ohmicly contacted to the
second layer 12 and the fifth layer 15. The second main electrode 32 extends on the
insulating film 41 formed on the first layer 11 in the lateral direction and has the
role of suppressing the peak of the potential strength induced by the depletion layer
extending from the side of the second layer 12 and reaching the third layer 13. In
the embodiment, the flow of transient current by voltage changes into the semiconductor
substrate 23 is obstructed by the silicon oxide film 24 between the poly-silicon layer
22 and the semiconductor substrate 23. A higher withstand voltage than the embodiment
shown in Fig.1 is realized in the present embodiment since the oxide film 21 also
shares the applied voltage. Since the forth n type layer 13 is formed between the
first layer 11 and the silicon oxide film 21 in the side direction of the island 1,
the depletion layer extending in the lateral direction is stopped by the forth layer
14 , and the depletion layers extending from the adjoining islands is prevented from
joining together and interfering each other in the poly-silicon layer 22 thereby.
Fig.3 is a plane drawing of the apparatus shown in Fig.1. In the figure, the fifth
layer 15, the gate electrode 35 and the first electrode 31 are omitted. The forth
layer 14 is formed along with the round of the silicon oxide layer 21. Thereby, the
interferences with other element are prevented even if a lead is drawn in any direction.
And the third layer 13 is formed partially contacting to the forth layer 14. Since
the carriers are gathered from the round of the forth layer 14 thereby, the on-resistance
can be reduced. Further, a lead can be drawn from the part without the third layer
13 since the third layer 13 is formed partially to the forth layer 14.
(Embodiment 3)
[0017] Fig.4 is a sectional outline drawing showing the embodiment of the present invention.
A high impurity concentration region 221 is provided inside from the surface of the
poly-silicon layer 22 between the adjoining islands respectively separated by the
silicon oxide films 21. Since the extension of the depletion layer in the lateral
direction is stopped by the region 221, the mutual interference of the adjoining islands
1 is prevented without longing the interval between the islands 1. It is desirable
that the region 221 is not contacted to the silicon oxide film 21 and provided apart
from it. The reason is because the distance between the second layer 12 and the silicon
oxide film 21 can be reduced due to the share of the applied voltage in the lateral
direction by the first layer 11, the silicon oxide film 21 and the poly-silicon layer
22 into which the depletion layer extends also. Therefore, the same withstand voltage
as obtained by the embodiment described in Fig.3 is secured without forming the forth
layer 14 shown in Fig.3 and the withstand voltage is more improved if the forth layer
14 is further provided.
(Embodiment 4)
[0018] Fig.5 is a sectional outline drawing showing the forth embodiment. In the embodiment,
the high impurity concentration region 222 is formed between the silicon oxide films
21 and 24. Since the extension of the depletion layer in the lateral direction is
stopped by the region 222 and the mutual interference of the adjoining islands 1 is
prevented, the region for separating the islands 11 can be further narrowed.
(Embodiment 5)
[0019] Fig.6 is a sectional outline drawing of the fifth embodiment in which the present
invention is applied to a diode. In the embodiment, the third electrode 36 having
the same potential as the second electrode 32 is newly provided on the insulating
film 41 at the circumference of the island 1. The extending region of the depletion
layer is indicated by dotted lines. The third electrode 36 is provided so as to reach
the part above the first layer 11 passing the part above the forth layer 14 from the
part above the silicon oxide film 21. The poly-silicon is desirable as material for
the third electrode 36. The first electrode 31 is drawn into regions besides the island
1, insulated from the third electrode 36 by the insulating film 42. As for the bias
state of each electrode, the first electrode 31 is earthed and the positive potential
is applied to the second electrode 32, the auxiliary electrode 33 and the third electrode
36. The above-mentioned constitution brings about the following effects. The depletion
layer has the trend of extending in the lateral direction and reaches the forth layer
14 by lower voltage since the depletion layer is extended in the lateral direction
by the potential of the first electrode 31 near the surface of the first layer 11
in the region from which the first electrode 31 is drawn. When the depletion layer
reaches the forth layer 14 and can not extend further in the lateral direction, the
potential centralizes at the surface of the boundary of the first layer 11 and the
forth layer 14, which decreases the withstand voltage. One method for preventing the
withstand voltage decrease is to relax the centralized potential between the first
electrode 31 and the first layer 11 by increasing the thickness of the insulating
films 41 and 42 under the first electrode 31. However, the method has the problem
that, by increase of the differences in level, the resolution of an aligner deteriorates
and the producing accuracy by a photoresist also deteriorates, which consequently
lowers the integration density. Since the third electrode 36 is provided and the positive
potential is applied to it by the second electrode 32 in the present embodiment, the
depletion layer extension in the lateral direction to the second electrode 32 is suppressed
by the third electrode 36. Then, the depletion layer is extended in the perpendicular
direction and the potential centralization in the lateral direction is relaxed, which
consequently improves the withstand voltage. The thickness of the insulating film
41 between the third electrode 36 and the forth layer 14 can be decreased due to the
suppression of the potential centralization on the forth layer 14 by the potential
relaxation in the lateral direction, which consequently improves the producing accuracy
by a photo resist and increases the integration density. By the prior arts, about
6 /1.m is required as the thickness of the insulating film 41 to the 700 V withstand
voltage, on the other hand, the thickness of the insulating film 41 can be reduced
to 2.5 /1.m and the minimum producing size is improved by 3 /1.m by the present embodiment.
Fig.7 is a plane drawing of the embodiment shown by Fig.6. The third electrode 36
is provided at the circumference of the island 1 except the vicinity of the region
where the third layer 13 is formed. The first electrode 31 can be drawn from the second
layer 12 in any direction except the direction to the third layer 13, which increases
the layout freedom of a SIC apparatus.
(Embodiment 7)
[0020] Fig.8 is a sectional outline drawing showing the seventh embodiment of the present
invention. In the embodiment, the sixth n type layer 16 having higher impurity concentration
than the first layer 11 is formed along with the whole boundary face of the first
layer 11 and the silicon oxide film 21. The thickness and the impurity concentration
of the sixth layer 16 are determined so as the depletion layer reaches the silicon
oxide film 21 by lower voltage than the avalanche breakdown occurs. In the embodiment,
the shared potential by the island 1 covered with the silicon oxide film 21, namely,
the shared potential by the first layer 11 and the sixth layer 16 has higher ratio
of the applied voltage comparing with the shared voltage by the island 1 without the
sixth layer 16 since the impurity density is higher than the first layer 11. Thereby,
the voltage applied to the silicon oxide films 21 and 24 and the poly-silicon layer
22 is suppressed, and the thickness of the silicon oxide films 21 and 24 and the poly-silicon
layer 22 can be reduced.
(Embodiment 8)
[0021] Fig.9 is a sectional outline drawing showing the eighth embodiment by the present
invention. In the embodiment, three layers of the silicon oxide films 25 are stratiformly
scattered in the poly-silicon layer 22. By the above-mentioned constitution, five
layers of the silicon oxide films exist in the apparatus,therefore, the voltage applied
to a layer is decreased, and the thickness of each silicon oxide film and poly-silicon
layer is reduced, which shortens the producing time and makes the producing process
easier.
(Embodiment 9)
[0022] Fig.10 is a sectional outline drawing showing the ninth embodiment by the present
invention. In the embodiment, a layer of the silicon oxide film 25 is provided in
the poly-silicon layer 22, surrounding the island 1 and its brim reaches the surface
of the island 1. And, in the poly-silicon layer 22 divided into two parts by the silicon
oxide film 25, the island 1 side layer 223 has lower impurity concentration than the
semiconductor substrate 23 side layer 224. By the above-mentioned constitution, the
depletion layer extends into the low impurity concentration layer 223 in both the
lateral and the perpendicular direction, and stopped by the high impurity concentration
layer 224. Thereby, the voltage applied to the first layer 11 is lower than the applied
voltage and the lateral distance between the second layer 12 and the silicon oxide
layer 21 can be reduced, which improves the integration density, since the applied
voltage is shared by the silicon oxide film 21, the layer 223 of the poly-silicon
layer 22 and the silicon oxide film 25 in the lateral direction as well as in the
perpendicular direction. And the lateral extension of the depletion layer is prevented
by the layer 224 of the poly-silicon layer 22 and the separation region among the
islands 1 is narrowed, which improves the integration density further more.
(Embodiment 10)
[0023] Fig.11 is a sectional outline drawing showing the tenth embodiment by the present
invention. The embodiment has the constitution wherein the side wall of the island
1 meets at right angles to the exposed surface. The constitution is realized by processing
the side wall of the island 1 with anisotropic dry etching. By the constitution, the
separation region between the islands 1 is reduced. Although the dry etching has a
defect of the long processing time, the dry etching processing is applicable to the
present embodiment due to the thin thickness of the first layer 11, thereby, the high
integration density is realized.
(Embodiment 11)
[0024] Fig.12 is a sectional outline drawing showing the eleventh embodiment by the present
invention. The embodiment presents the SIC apparatus having a dielectric separation
substrate on which both a high withstand voltage element and low withstand voltage
elements are formed. A high withstand voltage element is formed in a island 1 a and
plural low withstand voltage elements are formed in a island 1 b. The forth layer
14 is formed along with the side wall of the island 1 a in which a high withstand
voltage element is provided and the sixth layer 16 is formed along with the whole
face of the silicon oxide film 21 of the island 1 b in which plural low withstand
voltage elements are provided. In the island 1 b, the high integration density is
realized since the separation regions can be more narrowed due to separation of the
low withstand voltage elements by the pn junctions than a method for forming a element
in a island by the dielectric separation.
[0025] Figs.13(1 )-13(6) show a outline process diagram showing an example production method
of the dielectric separation substrate used to the SIC apparatus of the present invention.
The process comprises the steps of;
{1} preparing a n type semiconductor wafer,
{2} forming selectively a silicon oxide film, making grooves by etching, preferably
with the KOH anisotropic etching or the dry etching, a surface of the semiconductor
wafer on which the silicon oxide film is masked, forming n type layers by doping phosphorus
or arsenic into the surfaces of the grooves at the semiconductor wafer utilizing the
silicon oxide film as masks,
{3} removing the silicon oxide film from the surface of the semiconductor wafer, forming
a silicon oxide film at the whole face including the surfaces of the grooves,
{4} accumulating a poly-silicon layer on the silicon oxide layer so as to fully bury
the grooves, grinding the surface of the poly-silicon layer,
{5} affixing the silicon substrate having a silicon oxide film thereon to the poly-silicon
layer, by facing its silicon oxide film surface to the poly-silicon layer, and
{6} scraping the other surface of the semiconductor wafer until the grooves are exposed
at the surface of the wafer.
[0026] By the above-mentioned process, the dielectric separation substrate used for the
present invention is produced.
(Embodiment 12)
[0027] Fig.14 is an outline drawing showing the twelfth embodiment wherein the SIC apparatus
by the present invention is applied to an monolithic inverter IC. The SIC is an invertor
for generating a three phase alternating current power by inputting a direct current
obtained with a rectified alternating current and comprises six power switching elements
101 at the output stage, six diodes 102 connected thereto in inversely parallel, an
upper arm driving circuit 103 and a lower arm driving circuit 104 for driving the
power switching elements of an upper arm and a lower arm, respectively, a level shift
circuit 105 for transmitting signals from elements having low potentials to the upper
arm driving circuit 103 having a high potential, a current detection circuit 106 for
detecting currents flowing in the power switching elements, a logic circuit 107 for
generating driving signals and a rotation frequency control circuit 108 for controlling
the rotation frequency accepting a rotor position detection signal and a rotation
direction signal from the outside. In the case of dealing with large currents, it
is difficult to integrate all elements in a dielectric separation substrate, so it
is practical to integrate the power switching elements 101 and the diodes 102 connected
thereto in the different dielectric substrates, respectively, or to use elements separately.
(Embodiment 13)
[0028] Fig.15 is an outline drawing showing the thirteenth embodiment wherein the SIC apparatus
of the present invention is applied to a monolithic inverter IC. Since fine producing
process is adoptable to the dielectric separation substrate used in the present invention
as mentioned above, which makes it possible to integrate a micro-processor, a digital
signal processor(DSP), or memories. In the SIC of the present embodiment, the microprocessor
or the DSP is integrated in the substrate and a motor is controlled by a program stored
in the memories 110. The invertor circuit can be provided inside motor due to downsizing
of the invertor.
[0029] Fig.16 is a plane layout outline drawing showing the monolithic inverter IC described
in Figs.14 and 15. As mentioned in the embodiment 11, a high withstand voltage element
is formed in a island and plural low withstand voltage elements are formed in a island.
In the figure, plural elements are integrated in a island at the region indicated
by oblique lines, which improves the integration density since the plural low withstand
voltage elements bring about narrow separation regions. The present invention is more
effective to the apparatus having the higher ratio of the separation region to the
active region in which currents flow. And the apparatus having elements required high
withstand voltages gains larger effectiveness by the present invention since an element
required a high withstand voltage needs a large separation region. Therefore, the
present invention is particularly effective to the circuit regions except the IGBT(Insulated
Gate Bipolar Transistor)s having large active regions and the diode connected thereto.
If the withstand voltage is 700 V, the separation region is required 64
/1.m as explained in the embodiment 1 and the minimum producing size is 10 /1.m as explained
in the embodiment 5, in a SIC apparatus by the prior arts. The 20 /1.m of the separation
region and the 3 µm of the producing size are realized by the present invention. Thereby,
the area of a SIC including about 1000 elements can be reduced to 20 mm
2, that is, to about 1/3 of the existing one having 50 mm
2 of the area.
[0030] By referring Fig.17, a method for providing the SIC apparatus into a package is explained.
Fig.17 is a perspective drawing of the SIC apparatus of the present invention mounted
in a package. The SIC apparatus of the present invention mounted in a package is covered
with a protection film such as resin. The SIC chip 203 is mounted on a radiation plate
with a metal layer 204 between and plural lead terminals 205 (2051-2056) are provided
on the plate. The chip 203 is electrically connected to outer circuits through which
signal exchanging or power supplying are done. The chip 203 is connected to the lead
terminals 205 by bonding wires 207 made from gold or aluminum linked between wiring
pads 206 and the lead terminals 205. The lead terminals 205 are connected to the highest
potential power source and the metal layer 204. Thereby, the supporter 2 (not shown
in the figure) of the chip 203 is connected to the highest potential power source
and the reverse bias potential is applied to the pn junction formed in the first layer
11 (not shown in the figure). Since the supporter 2 is electrically connected to the
highest potential lead terminal as mentioned above, the chip has not to be connected
to the high potential power source outside the package. And, even if the back face
of the chip has high potential, the radiation plate 201 is kept low potential since
the lead terminals 205 are provided at the insulating substrate mounted on the radiation
plate 201 and an electric shock can be prevented if the radiation plate 201 is attached
to a wall of the equipment containing the apparatus. Since the chip 203 thermally
conducts to the radiation plate 201 through the metal layer 204 and the insulating
substrate 202, low thermal resistance material, especially nitric aluminum, is desirably
used to the insulating substrate 202. Exchanging the n type semiconductor for the
p type one in the above-mentioned embodiments also brings about the similar effects
as the above-mentioned embodiments. Although the applications to a diode and a MOSFET
are described in the embodiments, the applications of the present invention are not
restricted to those ones and the present invention is applicable to all the elements
having pn junctions.
[0031] The effectiveness of the present invention is briefly mentioned in the followings.
[0032] In a dielectric separation substrate comprising the first plural island-wise semiconductor
layers of the first type conduction, semiconductor layers of the second type conduction
formed in the first semiconductor layers, the first insulating films for surrounding
the first semiconductor layers and separating the island elements, a semiconductor
substrate for a supporter having high impurity concentration, the second insulating
film formed on the semiconductor substrate and a poly-silicon layer formed between
the first insulating films and the second insulating film, the first semiconductor
layer between the bottoms of the second semiconductors layer and the first insulating
films can be fully depleted by lower voltage than the avalanche breakdown occurs in
the first semiconductor layer, by adequately setting the impurity concentration of
the first semiconductor layer and the distance between the bottoms of the second semiconductor
layers. The voltage applied to the first semiconductor layer is lower than the applied
voltage since the applied voltage is shared by the first insulating films, the high
impurity density semiconductor substrate for the supporter, the second insulating
film formed on the semiconductor substrate and the poly-silicon layer. The thickness
of the semiconductor layers forming the elements can be thinner by the above-mentioned
constitution, which makes the area of the element separating regions more narrow,
improves the integration density and brings on easier producing process. The extension
of the depletion layer is stopped at the surface of the high impurity density semiconductor
substrate and each depletion layers of the elements can be prevented from joining
in the substrate and interfering each other. And the contact resistances to electrodes
can be also reduced.
1. A semiconductor integrated circuit, comprising:
- a supporter (2) including a first semiconductor layer (22) of first type conduction
(n-) and a second semiconductor layer (23) with higher impurity concentration (n+) than the first semiconductor layer (22), and
- one or more semiconductor islands (1) being disposed on the surface of the first
layer (22) and being insulated against the first layer (22) by an insulating film
(21), wherein circuit elements are formed in said islands (1),
characterized in further comprising
an auxiliary electrode (33) provided at the second semiconductor layer (23) of the
supporter (2).
2. A semiconductor integrated circuit, comprising:
- a supporter (2) including a first semiconductor layer (22) of first type conduction
(n-) and a second semiconductor layer (23) with higher impurity concentration (n+) than the first semiconductor layer (22), and
- one or more semiconductor islands (1) being disposed on the surface of the first
layer (22) and being insulated against the first layer (22) by an insulating film
(21), wherein circuit elements are formed in said islands (1),
characterized in that
the island (1) including the circuit element to which the highest potential is applied
has such a depth that a depletion layer formed by reversely biasing a main junction
of said circuit element provided in said island reaches said first layer (22) of said
supporter (2).
3. A semiconductor integrated circuit according to claim 1,
characterized in that
for reversely biasing a main junction of a circuit element having the highest applied
potential of the circuit elements formed in the islands (1) a potential is applied
to the auxiliary electrode (33).
4. A semiconductor integrated circuit according to one of the claims 1 to 3,
characterized in that
one or more insulating films (24,25) are interposed between the first and the second
semiconductor layers (22, 23) or the first layer (22).
5. A semiconductor integrated circuit according to one of the claims 1 to 4, characterized
in that
each of the islands (1) comprises
- a third layer (11) of the first type conduction (n),
- a fourth layer (12) of a second type conduction (p) with higher impurity concentration
than the third layer (11) and extending from the surface of the island (1) into its
inside,
- a fifth layer (13) of the first type conduction (n) with higher impurity concentration
than the third layer (11) and extending from the surface of the island (1) into its
inside at a place apart from the fourth layer (12), and
- first and second electrodes (31, 32) respectively provided at said fourth and fifth
layer (12, 13).
6. A semiconductor integrated circuit according to claim 5,
characterized in further comprising
a sixth layer (14) of the first type conduction (n) with higher impurity concentration
than the third layer (11) provided between the insulating film (21) and the third
layer (11) of the island (1).
7. A semiconductor integrated circuit according to one of the claims 1 to 6,
characterized in that
high impurity concentration regions (221) are provided between the islands (1) in
the first semiconductor layer (22) of the supporter (2).
8. A semiconductor integrated circuit according to one of the claims 1 to 6,
characterized in that
a high impurity concentration region (222) is provided at each bottom of the islands
(1) in the first semiconductor layer (22) of the supporter (2).
9. A semiconductor integrated circuit having
- a supporter including layers piled up with a poly-silicon layer of first type conduction,
a first insulating film and a semiconductor substrate of first type conduction with
higher impurity concentration than the poly-silicon layer, and
- plural semiconductor islands supported by the poly-silicon layer of the supporter
with a second insulating film between, and in which circuit elements are formed,
characterized in that
the impurity concentration and the thickness of a region between the bottom of the
island and the circuit element region are set so that the region between the bottom
of the island and the circuit element region is fully depleted by a voltage lower
than that at which an avalanche breakdown occurs in the island.
10. A semiconductor integrated circuit according to claim 9, characterized in that
each of the islands comprises
- a first poly-silicon layer of the first type conduction,
- a second layer forming the circuit element of the second type conduction with higher
impurity concentration than the first layer, extending from the surface of the island
into its inside,
- a third layer forming said circuit element of the first type conduction with higher
impurity concentration than the first layer, extending into said first layer from
the surface of the island at a place apart from the second layer, and
- a first electrode and a second electrode provided at the second layer and the third
layer, respectively.
11. A semiconductor integrated circuit according to Claim 10,
characterized in further comprising
a fourth layer of the first type conduction with higher impurity concentration than
the first layer, provided between said insulating film and the first layer of said
island.
12. A semiconductor integrated circuit having
- a supporter including layers piled up with a poly-silicon layer of first type conduction
and a semiconductor substrate adjoining said poly-silicon layer of first type conduction
with higher impurity concentration than the poly-silicon layer, and
- plural semiconductor islands supported by the poly-silicon layer of the supporter
with an insulating film between, and in which circuit elements are formed, characterized
in that
- the distance between the main junction of the circuit element formed in the island
and the bottom of the island is set less than 1/14xV /1.m when the withstand voltage of the circuit element formed in the island is V volts.
13. A semiconductor integrated circuit having
- a supporter including layers piled up with a poly-silicon layer of first type conduction,
a first insulating film and a semiconductor substrate of first type conduction with
higher impurity concentration than the poly-silicon layer, and
- plural semiconductor islands supported by the poly-silicon layer of the supporter
with a second insulating film between and in which circuit elements are formed,
characterized in that
the distance between the main junction of said circuit element formed in said island
and the bottom of the island is set less than 1/14xV µm when the withstand voltage
of the circuit element formed in said island is V volts.